Hi Philippe,
On Tue, Jul 01, 2025 at 04:39:34PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 1 Jul 2025 16:39:34 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 26/68] accel/tcg: Implement get_[vcpu]_stats()
> X-Mailer: git-send-email 2.49.0
>
> Signed-off-by: Philippe Mathieu-Da
On 6/20/2025 5:27 PM, Zhao Liu wrote:
> Modern Intel CPUs use CPUID 0x4 leaf to describe cache information
> and leave space in 0x2 for prefetch and TLBs (even TLB has its own leaf
> CPUID 0x18).
>
> And 0x2 leaf provides a descriptor 0xFF to instruct software to check
> cache information in 0x4
On 7/3/2025 12:14 PM, Mi, Dapeng wrote:
> On 6/20/2025 5:27 PM, Zhao Liu wrote:
>> For a long time, the default cache models used in CPUID 0x2 and
>> 0x4 were inconsistent and had a FIXME note from Eduardo at commit
>> 5e891bf8fd50 ("target-i386: Use #defines instead of magic numbers for
>> CPUID
I have a college project where I want to take Tasmota, an open source ESP32
project and emulate the firmware in QEMU. I however keep running into issues
related to WI-FI initiation. I just wanted to ask if emulating Tasmota in the
expressif fork of QEMU is possible or not without removing WI-FI
Am 17. Juni 2025 20:34:35 UTC schrieb Bernhard Beschow :
>When compiling QEMU against fuse3-3.17.1 with --enable-werror the build fails
>with:
>
> In file included from ../src/block/export/fuse.c:33:
> /usr/include/fuse3/fuse.h:959:5: error: redundant redeclaration of
> ‘fuse_main_real_versio
On 7/2/25 23:42, Cédric Le Goater wrote:
On 7/1/25 14:16, Cédric Le Goater wrote:
On 7/1/25 12:04, Philippe Mathieu-Daudé wrote:
On 30/6/25 19:23, Cédric Le Goater wrote:
When grabbing a patch series, the link trailer is replaced with a
Message-ID, which is not useful compared to an URL. Fix
On 7/2/25 23:58, Steve Sistare wrote:
NOTE: this V6 series depends on the patch
vfio-user: do not register vfio-user container with cpr
which is in vfio-next.
Support vfio and iommufd devices with the cpr-transfer live migration mode.
Devices that do not support live migration can still suppo
On 7/2/25 23:41, Cédric Le Goater wrote:
On 6/30/25 19:20, Cédric Le Goater wrote:
Both quilt, to apply patches, and cscope, to navigate in the code, are
useful tools. Make sure source files that quilt saves when applying
patches are not taken into account when building the cscope database.
Sig
On 7/2/25 23:58, Steve Sistare wrote:
Save the MSI message area as part of vfio-pci vmstate, and preserve the
interrupt and notifier eventfd's. migrate_incoming loads the MSI data,
then the vfio-pci post_load handler finds the eventfds in CPR state,
rebuilds vector data structures, and attaches
On 7/2/25 23:58, Steve Sistare wrote:
Preserve vfio INTx state across cpr-transfer. Preserve VFIOINTx fields as
follows:
pin : Recover this from the vfio config in kernel space
interrupt : Preserve its eventfd descriptor across exec.
unmask : Ditto
route.irq : This could perhaps be r
The ast2700a0-evb machine represents the first revision of the AST2700 and
serves as the initial engineering sample rather than a production version.
A newer revision, A1, is now supported, and the ast2700a1-evb should replace
the older A0 version.
Signed-off-by: Jamin Lin
---
docs/about/depreca
Hi,
On 6/30/25 2:31 PM, Jonathan Cameron wrote:
> On Fri, 27 Jun 2025 12:00:51 +0200
> Eric Auger wrote:
>
>> Hi,
>>
>> On 6/27/25 11:55 AM, Eric Auger wrote:
>>> Changes relate to the introduction of pieces related to
>>> acpi-index static support along with root ports with no hotplug.
>>>
>>> +
Hi Shaoqin,
On 7/3/25 3:28 AM, Shaoqin Huang wrote:
> Set the "use-legacy-x86-rom" property to false by default, and only set
> it to true on x86 since only x86 will need it.
>
> At the same time, set the "use-legacy-x86-rom" property to true on those
> historical versioned machine types in order
Il mer 2 lug 2025, 23:36 Xiaoyao Li ha scritto:
> The reason why accelerator's instance_init() was moved to post_init, was
> just it needs to consider other factors. Please see commit 4db4385a7ab6
> ("i386: run accel_cpu_instance_init as post_init")
>
You're right and this can be a problem with
On Thu, Jun 26, 2025 at 10:23:33PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
> ---
Minor comments inline ...
> hw/cxl/cxl-mailbox-utils.c | 79 +++
On Thu, Jun 26, 2025 at 10:23:32PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
> ---
Minor comments inline...
> hw/cxl/cxl-mailbox-utils.c | 106 +
On 6/20/2025 5:27 PM, Zhao Liu wrote:
> For a long time, the default cache models used in CPUID 0x2 and
> 0x4 were inconsistent and had a FIXME note from Eduardo at commit
> 5e891bf8fd50 ("target-i386: Use #defines instead of magic numbers for
> CPUID cache info"):
>
> "/*FIXME: CPUID leaf 2 desc
On Thu, Jun 26, 2025 at 10:23:31PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> Prepatory patch for following FMAPI Add/Release Patches. Refactors part
> of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
> function to create DC Event Records and insert in the event log.
On 7/3/2025 11:08 AM, Zhao Liu wrote:
On Thu, Jul 03, 2025 at 09:03:10AM +0800, Xiaoyao Li wrote:
Date: Thu, 3 Jul 2025 09:03:10 +0800
From: Xiaoyao Li
Subject: Re: [Regression] Re: [PULL 35/35] qom: reverse order of
instance_post_init calls
On 7/3/2025 2:54 AM, Paolo Bonzini wrote:
Il mer
Record the interrupt vector and the apic id of the vcpu that calls
TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT.
Inject the interrupt to TD guest to notify the completion of
when notify interrupt vector is valid.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 3 +++
target/i386/kvm/tdx-s
KVM reports the supported TDVMCALL sub leafs in TDX capabilities.
one for kernel-supported
TDVMCALLs (userspace can set those blindly) and one for user-supported
TDVMCALLs (userspace can set those if it knows how to handle them)
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 11 +
To fetch the update of TDX
Signed-off-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 8 +++-
linux-headers/linux/kvm.h | 4
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index cd275ae76d25..f0c1a730d9c3 10064
GHCI is finalized with the being one of the base VMCALLs, and
not enuemrated via .
Adjust tdx_handle_get_tdvmcall_info() to match with GHCI.
Opportunistically fix the wrong indentation and explicitly set the
ret to TDG_VP_VMCALL_SUCCESS (in case KVM leaves unexpected value).
Signed-off-by: Xiao
It ends up as is one of the base TDG.VP.VMCALL leaf, and it's
not enumerated via bit 0 of out R11 (the bit 0 becomes reserved).[1]
So patch 1 updates the handling of tdx_handle_get_tdvmcall_info().
[1] https://cdrdv2.intel.com/v1/dl/getContent/858626
Paolo,
Patch 2-4, enables in QEMU. They ba
On Thu, Jul 03, 2025 at 09:03:10AM +0800, Xiaoyao Li wrote:
> Date: Thu, 3 Jul 2025 09:03:10 +0800
> From: Xiaoyao Li
> Subject: Re: [Regression] Re: [PULL 35/35] qom: reverse order of
> instance_post_init calls
>
> On 7/3/2025 2:54 AM, Paolo Bonzini wrote:
> > Il mer 2 lug 2025, 09:25 Xiaoyao L
>-Original Message-
>From: Steve Sistare
>Subject: [PATCH V6 13/21] migration: vfio cpr state hook
>
>Define a list of vfio devices in CPR state, in a subsection so that
>older QEMU can be live updated to this version. However, new QEMU
>will not be live updateable to old QEMU. This i
>-Original Message-
>From: Steve Sistare
>Subject: [PATCH V6 12/21] vfio/iommufd: register container for cpr
>
>Register a vfio iommufd container and device for CPR, replacing the generic
>CPR register call with a more specific iommufd register call. Add a
>blocker if the kernel does n
在 2025/7/2 下午5:59, Bibo Mao 写道:
On 2025/7/2 下午3:21, gaosong wrote:
在 2025/7/2 上午11:15, Bibo Mao 写道:
On 2025/6/27 上午11:01, Song Gao wrote:
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 44
+++
On 7/3/2025 2:54 AM, Paolo Bonzini wrote:
Il mer 2 lug 2025, 09:25 Xiaoyao Li ha scritto:
IIRC that's on rhel QEMU which ports the TDX code before it's merged
upstream. Now TDX is upstreamed, it works with upstream compat property
and I think future new compat property won't affect TDX or anyt
Add field for the south bridge in machine state to have both north and
south bridges in it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index
Move the chipset reset which is pegasos2 specific out from machine
reset to a separate function and move parts not specific to pegasos2
form build_fdt in machine reset so now build_fdt contains pegasos2
specific parts and renamed accordingly.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c |
Store the bus frequency in the machine state and set it from instance
init method.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 25 -
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index f7999520e4..ae3f01231d
These are not needed any more now that VOF can handle it.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index e15cf96427..73995624e5 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegas
We generate a flattened device tree programmatically for VOF. Change
this to load the static parts from a device tree blob and only
generate the parts that depend on run time conditions such as CPU
type, memory size and PCI devices. Moving the static parts in a dts
makes the board code simpler and
The Pegasos II is a redesign of the original Pegasos (later marked I)
that replaces the north bridge and has updated firmware but otherwise
these are very similar. The Pegasos uses the same north bridge that
AmigaOne used which we already emulate so we can also easily emulate
Pegasos I.
Signed-off
Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler
versions with less parameters based on that. This is inspired by how
the OBJECT_DEFINE macros do this in a similar way to allow using the
shortened definition in more complex cases too.
Signed-off-by: BALATON Zoltan
---
include/
The FDT does not normally store name properties but reconstructs it
from path but Open Firmware specification says each node should at
least have this property. This is correctly handled in getprop but
nextprop should also return it even if not present as a property.
Explicit name properties are s
This series changes how the fdt for VOF is generated in pegasos2 by
moving the static parts to a dtb and only generate the changing parts
such as memory size and PCI devices programmatically. This simplifies
the code and allows simply adding emulation of Pegasos I which has a
different north bridge
Rename machine state struct to PegasosMachineState as it will be used
for pegasos1 too.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 66 ---
1 file changed, 34 insertions(+), 32 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
Use more generic name for the field used to store the north bridge in
the machine state.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/pegasos2.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/
When running without firmware ROM using Virtual Open Firmware we need
to do some hardware initialisation and provide the device tree as the
machine firmware would normally do.
Signed-off-by: BALATON Zoltan
---
MAINTAINERS | 1 +
hw/ppc/pegasos2.c| 140 +
Collect steps of setting up PCI IRQ routing in one function.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 66 +++
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 66bceec5ef..26a571f82
The machine class has a field for storing the fdt so we don't need our
own and can use that instead.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 646755a3cc..7dc7803c64 1
On Wed, Jul 02, 2025 at 01:30:51PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> We don't have any automatic regression tests for these machines and
> when asking the usual suspects on the mailing list we came to the
> conclusion that nobody tests these machines manually, too, so it seems
> l
The mmcfg field in PCIHostState is only used by raven for the PCI
config direct access but is not actually needed as the memory region
lifetime can be managed by the object given during init so use that
and remove the unused field from PCIHostState.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/
The bit that is supposed to control if ISA IO ports are accessed with
discontiguous addresses was not connected so it did nothing. We can
now directly enable or disable the discontiguous region so allow the
bit to function. This did not cause a problem so far as nothing seems
to use this bit or dis
Move the lines related to creating the bus master address space
together and reduce the number of memory regions stored in the device
state. These are used once to create the address space and can be
tracked with their owner object so no need to keep track of them in
the device state. Keep only the
No need to use an or-irq to map interrupt lines to a single IRQ as the
PCI code can handle this internally so simplify by dropping the or-irq.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 39 +++
hw/ppc/prep.c | 5 -
2 files changed, 19 i
Use ctz instead of an open coded version and rename function to better
show what it does.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index a400a22df3..66dab28
Export memory regions as sysbus mmio regions and let the board code
map them similar to how it is done in grackle.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 37 -
hw/ppc/prep.c | 11 +--
2 files changed, 21 insertions(+), 27 deletio
The PCI configuration direct access region occupies 8 MiB at offset
0x80 in PCI IO space so model that accordingly.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/r
Convert to using DEFINE_TYPES macro and move raven_pcihost_class_init
so methods of each object are grouped together.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 57 +
1 file changed, 26 insertions(+), 3
Instead of passing unneeded enclosing objects to the config direct
access ops that only need the bus we can pass that directly thus
simplifying the functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 14 +++---
1 file changed, 7 inserti
The raven PCI device does not need a state struct as it has no data to
store there any more, so we can remove that to simplify code.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 30 +-
1 file changed, 1 insertion(+), 29 deletions(-)
diff --git a/hw/pci-hos
Rename memory io ops implementing PCI configuration direct access to
mmcfg which describes better what these are for.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/rave
Hello,
This series cleans up and simplifies the raven model which does some
strange stuff that no other pci-host is doing and does it in a
convoluted way and also has some legacy bits that can be removed.
Apart from making the model much more readable this also fixes the
non-contiguous IO control
Instead of doing it manually use pci_register_root_bus() to create and
register the PCI bus.
Signed-off-by: BALATON Zoltan
---
hw/pci-host/raven.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index e0f98afebf..5
PREP allows remapping of the 64k ISA IO addresses from the normal
contiguous IO space into a discontiguous 8MB region and can switch
between the two modes. We can implement this in a simpler way than is
done currently using an io region that forwards access to the
contiguous pci_io region and enabl
Use OBJECT_DECLARE_SIMPLE_TYPE macro instead of open coding it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index 172f01694c..878c915
cc Paolo.
After incorporating Peter's feedback, IMO this version reads well:
* kvm exports kvm_close
* vfio exports vfio_kvm_device_close
* vfio-cpr registers a notifier that calls vfio_kvm_device_close
- Steve
On 7/2/2025 5:58 PM, Steve Sistare wrote:
cpr-transfer breaks vfio network co
On Wed, Jul 02, 2025 at 11:38:53PM +0200, Cédric Le Goater wrote:
> On 7/1/25 22:34, Ed Tanous wrote:
> > GB200nvl72 is a system for for accelerated compute. This is a model for
> > the BMC target within the system.
>
> Could you please add a comment saying it is based on DT :
>
> aspeed-bmc-n
Define vfio_device_free_name to free the name created by
vfio_device_get_name. A subsequent patch will do more there.
No functional change.
Signed-off-by: Steve Sistare
Reviewed-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
---
include/hw/vfio/vfio-device.h | 1 +
hw/vfio/ap.c
Skip allocation of, and attachment to, hwpt_id. Recover it from CPR state.
Signed-off-by: Steve Sistare
Reviewed-by: Zhenzhong Duan
---
hw/vfio/iommufd.c | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
in
Register a vfio iommufd container and device for CPR, replacing the generic
CPR register call with a more specific iommufd register call. Add a
blocker if the kernel does not support IOMMU_IOAS_CHANGE_PROCESS.
This is mostly boiler plate. The fields to to saved and restored are added
in subseque
Reconstruct userland device state after CPR. During vfio_realize, skip all
ioctls that configure the device, as it was already configured in old QEMU.
Skip bind, and use the devid from CPR state.
Skip allocation of, and attachment to, ioas_id. Recover ioas_id from CPR
state, and use it to find
Save the MSI message area as part of vfio-pci vmstate, and preserve the
interrupt and notifier eventfd's. migrate_incoming loads the MSI data,
then the vfio-pci post_load handler finds the eventfds in CPR state,
rebuilds vector data structures, and attaches the interrupts to the new
KVM instance.
NOTE: this V6 series depends on the patch
vfio-user: do not register vfio-user container with cpr
which is in vfio-next.
Support vfio and iommufd devices with the cpr-transfer live migration mode.
Devices that do not support live migration can still support cpr-transfer,
allowing live update to
Update documentation to say that cpr-transfer supports vfio and iommufd.
Signed-off-by: Steve Sistare
Reviewed-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
---
docs/devel/migration/CPR.rst | 5 ++---
qapi/migration.json | 6 --
2 files changed, 6 insertions(+), 5 deletions(-)
Preserve vfio INTx state across cpr-transfer. Preserve VFIOINTx fields as
follows:
pin : Recover this from the vfio config in kernel space
interrupt : Preserve its eventfd descriptor across exec.
unmask : Ditto
route.irq : This could perhaps be recovered in vfio_pci_post_load by
callin
Use IOMMU_IOAS_MAP_FILE when the mapped region is backed by a file.
Such a mapping can be preserved without modification during CPR,
because it depends on the file's address space, which does not change,
rather than on the process's address space, which does change.
Signed-off-by: Steve Sistare
R
Add the helper function cpr_get_fd_param, to use when preserving
a file descriptor that is opened externally and passed to QEMU.
cpr_get_fd_param returns a descriptor number either from a QEMU
command-line parameter, from a getfd command, or from CPR state.
When a descriptor is passed to new QEMU
cpr-transfer will use the device name as a key to find the value
of the device descriptor in new QEMU. However, if the descriptor
number is specified by a command-line fd parameter, then
vfio_device_get_name creates a name that includes the fd number.
This causes a chicken-and-egg problem: new QEM
Define the change process ioctl
Signed-off-by: Steve Sistare
Reviewed-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
---
include/system/iommufd.h | 3 +++
backends/iommufd.c | 24
backends/trace-events| 1 +
3 files changed, 28 insertions(+)
diff --git a
VFIO iommufd devices will need access to ioas_id, devid, and hwpt_id in
new QEMU at realize time, so add them to CPR state. Define CprVFIODevice
as the object which holds the state and is serialized to the vmstate file.
Define accessors to copy state between VFIODevice and CprVFIODevice.
Signed-o
Define a list of vfio devices in CPR state, in a subsection so that
older QEMU can be live updated to this version. However, new QEMU
will not be live updateable to old QEMU. This is acceptable because
CPR is not yet commonly used, and updates to older versions are unusual.
The contents of each
If an invariant device name cannot be created, block CPR.
Signed-off-by: Steve Sistare
Reviewed-by: Zhenzhong Duan
---
include/hw/vfio/vfio-cpr.h | 1 +
hw/vfio/device.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/include/hw/vfio/vfio-cpr.h b/include/hw/vfio/vfi
cpr-transfer breaks vfio network connectivity to and from the guest, and
the host system log shows:
irq bypass consumer (token a03c32e5) registration fails: -16
which is EBUSY. This occurs because KVM descriptors are still open in
the old QEMU process. Close them.
Cc: Paolo Bonzini
Si
vfio_cpr_[un]register_container is no longer used since they were
subsumed by container type-specific registration. Delete them.
Signed-off-by: Steve Sistare
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
---
include/hw/vfio/vfio-cpr.h | 4
hw/vfio/cpr.c | 13 ---
Define qemu_ram_get_fd_offset, so CPR can map a memory region using
IOMMU_IOAS_MAP_FILE in a subsequent patch.
Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
Reviewed-by: Zhenzhong Duan
---
include/exec/cpu-common.h | 1 +
system/physmem.c | 5 +
2 files changed, 6 insertions(
During cpr-transfer load in new QEMU, the vfio_memory_listener causes
spurious calls to map and unmap DMA regions, as devices are created and
the address space is built. This memory was already already mapped by the
device in old QEMU, so suppress the map and unmap callbacks during incoming
CPR.
Define iommufd_backend_map_file_dma to implement IOMMU_IOAS_MAP_FILE.
This will be called as a substitute for iommufd_backend_map_dma, so
the error conditions for BARs are copied as-is from that function.
Signed-off-by: Steve Sistare
Reviewed-by: Zhenzhong Duan
---
include/system/iommufd.h | 3
Finish CPR by change the owning process of the iommufd device in
post load.
Signed-off-by: Steve Sistare
Reviewed-by: Zhenzhong Duan
---
hw/vfio/cpr-iommufd.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/vfio/cpr-iommufd.c b/hw/vfio/cpr-iommufd.c
index
Save the iommu and vfio device fd in CPR state when it is created.
After CPR, the fd number is found in CPR state and reused.
Signed-off-by: Steve Sistare
Reviewed-by: Zhenzhong Duan
---
backends/iommufd.c| 35 +--
hw/vfio/cpr-iommufd.c | 10 ++
hw/vf
On 7/1/25 14:16, Cédric Le Goater wrote:
On 7/1/25 12:04, Philippe Mathieu-Daudé wrote:
On 30/6/25 19:23, Cédric Le Goater wrote:
When grabbing a patch series, the link trailer is replaced with a
Message-ID, which is not useful compared to an URL. Fix that by
dropping the linktrailermask confi
On 6/30/25 19:20, Cédric Le Goater wrote:
Both quilt, to apply patches, and cscope, to navigate in the code, are
useful tools. Make sure source files that quilt saves when applying
patches are not taken into account when building the cscope database.
Signed-off-by: Cédric Le Goater
---
Makefi
On 7/1/25 22:34, Ed Tanous wrote:
GB200nvl72 is a system for for accelerated compute. This is a model for
the BMC target within the system.
Could you please add a comment saying it is based on DT :
aspeed-bmc-nvidia-gb200nvl-bmc.dts
from
https://github.com/openbmc/linux/blob/dev-6.6/ar
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
In order to dispatch over AccelOpsClass::get_virtual_clock(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::get_virtual_clock() mandatory.
Register the default cpus_kick_thread() for each accelerator.
On 7/1/25 22:33, Ed Tanous wrote:
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c | 2 ++
include/hw/arm/aspeed.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
inde
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
In order to dispatch over AccelOpsClass::get_virtual_clock(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::get_virtual_clock() mandatory.
Register the default cpus_kick_thread() for each accelerator.
On 7/2/25 21:20, etanous wrote:
On Wed, Jul 02, 2025 at 09:04:25AM +0200, Philippe Mathieu-Daudé wrote:
Hi,
On 2/7/25 08:47, Cédric Le Goater wrote:
Hello Ed,
On 7/1/25 22:33, Ed Tanous wrote:
From: Ed Tanous
There are arm targets that are connected to this io expander,
specifically some
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
In order to dispatch over AccelOpsClass::get_elapsed_ticks(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::get_elapsed_ticks() mandatory.
Register the default cpus_kick_thread() for each accelerator.
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
In order to dispatch over AccelOpsClass::kick_vcpu_thread(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::kick_vcpu_thread() mandatory.
Register the default cpus_kick_thread() for each accelerator.
S
On 7/2/25 21:31, etanous wrote:
On Wed, Jul 02, 2025 at 09:00:53AM +0200, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 7/1/25 22:33, Ed Tanous wrote:
This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspee
On 7/2/25 21:27, etanous wrote:
On Wed, Jul 02, 2025 at 09:00:20AM +0200, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
On 7/1/25 22:33, Ed Tanous wrote:
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
Altough we aren't going to re-use rr_cpu_exec(), factor
it out to have RR implementation matches with MTTCG one.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops-rr.c | 31 ---
1 file changed, 20 i
On 7/2/25 11:53 AM, Philippe Mathieu-Daudé wrote:
Although unreachable, still unregister the RCU before exiting
the thread, as documented in "qemu/rcu.h":
/*
* Important !
*
* Each thread containing read-side critical sections must be registered
* with rcu_register_thread() before
On 7/2/25 11:52 AM, Philippe Mathieu-Daudé wrote:
We need the QEMU binary signed to be able to use HVF.
Improve the following:
$ ./qemu-system-aarch64-unsigned -M virt -accel hvf
qemu-system-aarch64-unsigned: -accel hvf: Error: ret = HV_DENIED
(0xfae94007, at ../../accel/hvf/hvf-accel-ops
On 7/2/2025 9:46 AM, Duan, Zhenzhong wrote:
-Original Message-
From: Steven Sistare
Subject: Re: [PATCH V5 35/38] vfio/iommufd: change process
On 6/25/2025 7:40 AM, Duan, Zhenzhong wrote:
-Original Message-
From: Steve Sistare
Subject: [PATCH V5 35/38] vfio/iommufd: change pro
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_cpu_synchronize_state() stub is not
necessary.
Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/stub
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