On 1/7/25 21:42, Thomas Huth wrote:
From: Thomas Huth
While Tribbles are cute, it should be "triple store" here,
not "trible store".
Signed-off-by: Thomas Huth
---
target/s390x/cpu_features_def.h.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
:)
Reviewed-by: Philippe Mathieu-
On 2/7/25 08:42, Zhao Liu wrote:
On Wed, Jul 02, 2025 at 08:03:19AM +0200, Thomas Huth wrote:
Date: Wed, 2 Jul 2025 08:03:19 +0200
From: Thomas Huth
Subject: [PATCH] accel/kvm: Adjust the note about the minimum required
kernel version
From: Thomas Huth
Since commit 126e7f78036 ("kvm: requ
Hello Ed,
On 7/1/25 22:33, Ed Tanous wrote:
From: Ed Tanous
There are arm targets that are connected to this io expander,
specifically some varieties of Aspeed 2600 BMCs. Add it to Kconfig to
allow use.
Signed-off-by: Ed Tanous
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
di
On 7/1/25 22:33, Ed Tanous wrote:
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 43d27d83cb..be
Hello,
Should we switch the alias to point to 'ast2700a1-evb' in QEMU 10.1.0 ?
and deprecate the A0 SoC and machine if it is no longer planned to support
them.
Sorry for the late reply and delay in processing this task.
I’ve been postponing this because our customers do not have "AST2700 A1 E
On 7/2/25 08:27, Cédric Le Goater wrote:
Adding more maintainers,
+Eric (ARM smmu),
+Peter (ARM, GIC, virt),
On 6/24/25 19:51, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This property allows configuring whether to start the config load only
after all iterables were loaded.
Such i
Adding more maintainers,
+Eric (ARM smmu),
+Peter (ARM, GIC, virt),
On 6/24/25 19:51, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This property allows configuring whether to start the config load only
after all iterables were loaded.
Such interlocking is required for ARM64 due to t
On Wed, Jul 02, 2025 at 08:03:19AM +0200, Thomas Huth wrote:
> Date: Wed, 2 Jul 2025 08:03:19 +0200
> From: Thomas Huth
> Subject: [PATCH] accel/kvm: Adjust the note about the minimum required
> kernel version
>
> From: Thomas Huth
>
> Since commit 126e7f78036 ("kvm: require KVM_CAP_IOEVENTFD
> > +{
> > +.version = 3,
> > +.note = "with the cache info",
>
> I realize that my previous use of "cache info" was not precise; "cache
> model" is more appropriate. Please help me adjust accordingly, thank you.
Nope, will fix.
> > +.c
From: Thomas Huth
Since commit 126e7f78036 ("kvm: require KVM_CAP_IOEVENTFD and
KVM_CAP_IOEVENTFD_ANY_LENGTH") we require at least kernel 4.4 to
be able to use KVM. Adjust the upgrade_note accordingly.
While we're at it, remove the text about kvm-kmod and the
SourceForge URL since this is not act
On 6/16/25 21:20, Sean Wei wrote:
Several source comments still refer to docs with the old .txt
extension that were previously converted to reStructuredText.
Update these references to use the correct .rst extensions to
maintain accurate in-tree documentation pointers.
No functional changes.
> One more question, now the qemu doesn't have the hw_compat_10_1, should I
> first add another patch to add it just like the commit:
> 0a7c438a42 hw: add compat machines for 10.0
Hi Shaoqin, I think you can add compat option in hw_compat_10_0. Then
the compat property will be applied for v10.0 an
On 6/24/2025 3:43 PM, Dongli Zhang wrote:
> PMU MSRs are set by QEMU only at levels >= KVM_PUT_RESET_STATE,
> excluding runtime. Therefore, updating these MSRs without stopping events
> should be acceptable.
>
> In addition, KVM creates kernel perf events with host mode excluded
> (exclude_host =
On 6/24/2025 3:43 PM, Dongli Zhang wrote:
> + uint32_t sel_base = MSR_K7_EVNTSEL0;
> + uint32_t ctr_base = MSR_K7_PERFCTR0;
> + /*
> + * The address of the next selector or counter register is
> + * obtained by incrementing the address of the current selector
> + * or counter register by one.
> +
On Tue, Jul 01, 2025 at 07:28:07PM +0200, Magnus Kulke wrote:
> Hey all,
>
[...]
>
> Magnus Kulke (27):
> accel: Add Meson and config support for MSHV accelerator
> target/i386/emulate: Allow instruction decoding from stream
> target/i386/mshv: Add x86 decoder/emu implementation
> hw/intc
On Tue, Jul 01, 2025 at 07:28:31PM +0200, Magnus Kulke wrote:
> Add the main vCPU execution loop for MSHV using the MSHV_RUN_VP ioctl.
>
> A translate_gva() hypercall is implemented. The execution loop handles
> guest entry and VM exits. There are handlers for memory r/w, PIO and
> MMIO to which t
On 7/2/2025 1:01 PM, Zhao Liu wrote:
Thanks Igor for looking here and thanks Konrad's explanation.
On 7/1/2025 6:26 PM, Zhao Liu wrote:
unless it was explicitly requested by the user.
But this could still break Windows, just like issue #3001, which enables
arch-capabilities for EPYC-Genoa. Th
On 6/24/2025 3:43 PM, Dongli Zhang wrote:
> When PMU is enabled in QEMU, there is a chance that PMU virtualization is
> completely disabled by the KVM module parameter kvm.enable_pmu=N.
>
> The kvm.enable_pmu parameter is introduced since Linux v5.17.
> Its permission is 0444. It does not change
> > > > Could you please tell me what the Windows's wrong code is? And what's
> > > > wrong when someone is following the hardware spec?
> > >
> > > the reason is that it's reserved on AMD hence software shouldn't even try
> > > to use it or make any decisions based on that.
> > >
> > >
> > > PS
Philippe Mathieu-Daudé writes:
> 'info accel' dispatches to the AccelOpsClass::get_stats()
> and get_vcpu_stats() handlers.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Acked-by: Richard Henderson
Standard question for new HMP commands that don't wrap around QMP
commands: why is the functionali
On Tue, Jul 01, 2025 at 07:28:25PM +0200, Magnus Kulke wrote:
> Write CPU register state to MSHV vCPUs. Various mapping functions to
> prepare the payload for the HV call have been implemented.
>
> Signed-off-by: Magnus Kulke
> ---
> include/system/mshv.h | 15 +++
> target/i386/mshv/mshv
On Tue, Jul 01, 2025 at 07:28:15PM +0200, Magnus Kulke wrote:
> Create the MSHV virtual machine by opening a partition and issuing
> the necessary ioctl to initialize it. This sets up the basic VM
> structure and initial configuration used by MSHV to manage guest state.
>
> Signed-off-by: Magnus K
On Tue, Jul 01, 2025 at 07:28:09PM +0200, Magnus Kulke wrote:
> Introduce a new helper function to decode x86 instructions from a
> raw instruction byte stream. MSHV delivers an instruction stream in a
> buffer of the vm_exit message. It can be used to speed up MMIO
> emulation, since instructions
Thanks Igor for looking here and thanks Konrad's explanation.
> > > > On 7/1/2025 6:26 PM, Zhao Liu wrote:
> > > > > > unless it was explicitly requested by the user.
> > > > > But this could still break Windows, just like issue #3001, which
> > > > > enables
> > > > > arch-capabilities for E
On 2025/4/15 0:38, Cornelia Huck wrote:
From: Eric Auger
We want to give a chance to override the value of host ID regs.
In a previous patch we made sure all their values could be fetched
through kvm_get_one_reg() calls before their modification. After
their potential modification we need to
On 2025/6/27 上午11:01, Song Gao wrote:
LoongArchVirtMachinState adds avecintc features, and
it use to check whether virt machine support advance interrupt controller
and default set avecintc = ON_OFF_AUTO_ON.
LoongArchVirtMachineState adds misc_feature and misc_status for
misc fetures and statu
On 6/24/2025 3:43 PM, Dongli Zhang wrote:
> The initialization of 'has_architectural_pmu_version',
> 'num_architectural_pmu_gp_counters', and
> 'num_architectural_pmu_fixed_counters' is unrelated to the process of
> building the CPUID.
>
> Extract them out of kvm_x86_build_cpuid().
>
> In additio
On 6/24/2025 3:43 PM, Dongli Zhang wrote:
> Although AMD PERFCORE and PerfMonV2 are removed when "-pmu" is configured,
> there is no way to fully disable KVM AMD PMU virtualization. Neither
> "-cpu host,-pmu" nor "-cpu EPYC" achieves this.
>
> As a result, the following message still appears in t
Hi Eric,
On 7/2/25 10:24 AM, Shaoqin Huang wrote:
Hi Eric,
Thanks for your review.
On 7/1/25 1:17 PM, Eric Auger wrote:
Hi,
On 7/1/25 5:05 AM, Shaoqin Huang wrote:
Set the "use-legacy-x86-rom" property to false by default, and only set
it to true on x86 since only x86 will need it.
At the
On Mon, Jun 16, 2025 at 11:06:32AM +0200, Philippe Mathieu-Daudé wrote:
> Date: Mon, 16 Jun 2025 11:06:32 +0200
> From: Philippe Mathieu-Daudé
> Subject: [RFC PATCH] target/i386: Report TPR accesses to HVF
> X-Mailer: git-send-email 2.49.0
>
> HVF should be able to handle task priority register a
On 7/1/25 08:39, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-all.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 2025/6/27 上午11:01, Song Gao wrote:
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 ++
2 files changed, 14 insertions(+), 2 del
On 2025/6/27 上午11:01, Song Gao wrote:
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/
On 2025/6/27 上午11:01, Song Gao wrote:
ntroduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongAr
On 2025/6/27 上午11:01, Song Gao wrote:
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.c | 7 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 25
On 7/1/25 08:39, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 2 +-
accel/kvm/kvm-all.c | 4 ++--
system/memory.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On Fri, May 23, 2025 at 03:44:31PM +, Kirill Martynov wrote:
> Date: Fri, 23 May 2025 15:44:31 +
> From: Kirill Martynov
> Subject: [PATCH] x86/cpu: Handle SMM mode in x86_cpu_dump_state for softmmu
> X-Mailer: git-send-email 2.43.0
>
> Certain error conditions can trigger x86_cpu_dump_st
On 2025/6/27 上午11:01, Song Gao wrote:
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 21 +
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3
On 7/1/25 04:31, William Kosasih wrote:
This patch adds alignment checks in the load operations in the VLDR
instruction.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
Signed-off-by: William Kosasih
---
target/arm/tcg/mve_helper.c | 41 -
1 f
Hi Eric,
Thanks for your review.
On 7/1/25 1:17 PM, Eric Auger wrote:
Hi,
On 7/1/25 5:05 AM, Shaoqin Huang wrote:
Set the "use-legacy-x86-rom" property to false by default, and only set
it to true on x86 since only x86 will need it.
At the same time, set the "use-legacy-x86-rom" property to
On 7/1/25 04:31, William Kosasih wrote:
This patch adds alignment checks in the load operations in the VLLDM
instruction, and in the store operations in the VLSTM instruction.
Manual alignment checks in the both helpers are retained because they
enforce an 8-byte alignment requirement (instead o
Hi Cédric
> Subject: Re: [PATCH v1 00/18] Support AST2700 A1
>
> Hi,
>
> On 1/31/25 08:34, Cédric Le Goater wrote:
> > Hello Jamin,
> >
> > On 1/21/25 08:04, Jamin Lin wrote:
> >> v1:
> >> 1. Refactor INTC model to support both INTC0 and INTC1.
> >> 2. Support AST2700 A1.
> >> 3. Create as
On 2025/6/27 上午11:01, Song Gao wrote:
move som machine define to virt.h and define avec feature and status bit.
Use the IOCSRF_AVEC bit for avdance interrupt controller drivers
avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit
IOCSRM_AVEC_EN.
and set the default value of t
To address this, patch #6 in the series introduces a new helper
function pci_setup_iommu_per_bus(), which explicitly sets the
iommu_per_bus field in the PCIBus structure. This allows
pci_device_get_iommu_bus_devfn() to retrieve IOMMU ops based
on the specific bus.
This patch
On 7/2/2025 3:47 AM, Konrad Rzeszutek Wilk wrote:
On Tue, Jul 01, 2025 at 05:47:06PM +0800, Xiaoyao Li wrote:
On 7/1/2025 5:22 PM, Alexandre Chartre wrote:
On 7/1/25 10:23, Xiaoyao Li wrote:
On 6/30/2025 9:30 PM, Alexandre Chartre wrote:
KVM emulates the ARCH_CAPABILITIES on x86 for both Int
* Daniel Henrique Barboza (dbarb...@ventanamicro.com) wrote:
>
>
> On 6/30/25 9:07 PM, Dr. David Alan Gilbert wrote:
> > * Daniel Henrique Barboza (dbarb...@ventanamicro.com) wrote:
> >
> > Hi Daniel,
> >
> > > The RISC-V target has *a lot* of CPU registers, with more registers
> > > being adde
On 6/30/25 9:07 PM, Dr. David Alan Gilbert wrote:
* Daniel Henrique Barboza (dbarb...@ventanamicro.com) wrote:
Hi Daniel,
The RISC-V target has *a lot* of CPU registers, with more registers
being added along the way when new extensions are added. In this world,
'info registers' will throw a
Thanks to 72d277a7, 1ed2cb32, and others, EDID (Extended Display
Identification Data) is propagated by QEMU such that a virtual display
presents legitimate metadata (e.g., name, serial number, preferred
resolutions, etc.) to its connected guest.
This change adds the ability to specify the EDID nam
Thanks to 72d277a7, 1ed2cb32, and others, EDID (Extended Display
Identification Data) is propagated by QEMU such that a virtual display
presents legitimate metadata (e.g., name, serial number, preferred
resolutions, etc.) to its connected guest.
This change adds the ability to specify the EDID nam
GB200nvl72 is a system for for accelerated compute. This is a model for
the BMC target within the system.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c| 79 ++
hw/arm/aspeed_eeprom.c | 21 +++
hw/arm/aspeed_eeprom.h | 3 ++
3 files changed
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 43d27d83cb..bec0a1dfa8 100644
--- a/docs/system/arm/
This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspeed 2600 SOC.
Ed Tanous (4):
hw/arm: Add PCA9554 to ARM target
hw/arm/aspeed: Add second SPI chip to Aspeed model
docs: add support for gb200-bmc
hw/arm/aspeed: Add GB200 BMC target
docs
From: Ed Tanous
There are arm targets that are connected to this io expander,
specifically some varieties of Aspeed 2600 BMCs. Add it to Kconfig to
allow use.
Signed-off-by: Ed Tanous
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c | 2 ++
include/hw/arm/aspeed.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d0b333646e..3ef7f6c5b2 100644
--- a/h
Implement signal handling for MSHV vCPUs to support asynchronous
interrupts from the main thread.
Signed-off-by: Magnus Kulke
---
accel/mshv/mshv-all.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index 04900a2b
Implement MSHV-specific hooks for vCPU creation and teardown in the
i386 target.
Signed-off-by: Magnus Kulke
---
target/i386/mshv/mshv-cpu.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c
inde
On Tue, Jul 01, 2025 at 03:05:00PM +0200, Igor Mammedov wrote:
> On Tue, 1 Jul 2025 20:36:43 +0800
> Zhao Liu wrote:
>
> > On Tue, Jul 01, 2025 at 07:12:44PM +0800, Xiaoyao Li wrote:
> > > Date: Tue, 1 Jul 2025 19:12:44 +0800
> > > From: Xiaoyao Li
> > > Subject: Re: [PATCH] i386/cpu: ARCH_CAPAB
Implement ioeventfd registration in the MSHV accelerator backend to
handle guest-triggered events. This enables integration with QEMU's
eventfd-based I/O mechanism.
Signed-off-by: Magnus Kulke
---
accel/mshv/mshv-all.c | 116
accel/mshv/trace-events |
..snip..
> OK, back to the original question "what should the code do?"
>
> My answer is, it can behave with any of below option:
>
> - Be vendor agnostic and stick to x86 architecture. If CPUID enumerates a
> feature, then the feature is available architecturally.
Exactly. That is what we belie
On 7/1/25 13:04, Michael Tokarev wrote:
On 30.06.2025 18:28, Richard Henderson wrote:
The scalar constant must be replicated for dup.
Cc: qemu-sta...@nongnu.org
Fixes: bab1671f0fa ("tcg: Manually expand INDEX_op_dup_vec")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3002
Signed-off-b
Create the MSHV virtual machine by opening a partition and issuing
the necessary ioctl to initialize it. This sets up the basic VM
structure and initial configuration used by MSHV to manage guest state.
Signed-off-by: Magnus Kulke
---
accel/mshv/mshv-all.c| 210 ++
Handle region_add events by invoking the MSHV memory registration
ioctl to map guest memory into the hypervisor partition. This allows
the guest to access memory through MSHV-managed mappings.
Note that this assumes the hypervisor will accept regions that overlap
in userspace_addr. Currently that'
Hi Magnus,
On 1/7/25 19:28, Magnus Kulke wrote:
QEMU maps certain regions into the guest multiple times, as seen in the
trace below. Currently the MSHV kernel driver will reject those
mappings. To workaround this, a record is kept (a static global list of
"slots", inspired by what the HVF accele
On Tue, Jul 01, 2025 at 05:47:06PM +0800, Xiaoyao Li wrote:
> On 7/1/2025 5:22 PM, Alexandre Chartre wrote:
> >
> > On 7/1/25 10:23, Xiaoyao Li wrote:
> > > On 6/30/2025 9:30 PM, Alexandre Chartre wrote:
> > > > KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD
> > > > cpus, althoug
On 16/06/2025 17.50, Sean Wei wrote:
The entry for the VMware PVSCSI spec uses "vwm" instead of "vmw",
which does not match any file in the tree.
Correct the path so scripts/get_maintainer.pl can match the file.
Signed-off-by: Sean Wei
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+),
From: Thomas Huth
While Tribbles are cute, it should be "triple store" here,
not "trible store".
Signed-off-by: Thomas Huth
---
target/s390x/cpu_features_def.h.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/cpu_features_def.h.inc
b/target/s390x/cpu_featur
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> This property allows configuring whether to start the config load only
> after all iterables were loaded.
> Such interlocking is required for ARM64 due to this platform VFIO
> dependency on interrupt controller being loaded first.
>
On 30.06.2025 18:28, Richard Henderson wrote:
The scalar constant must be replicated for dup.
Cc: qemu-sta...@nongnu.org
Fixes: bab1671f0fa ("tcg: Manually expand INDEX_op_dup_vec")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3002
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 2
Connect the x86 instruction decoder and emulator to the MSHV backend
to handle intercepted instructions. This enables software emulation
of MMIO operations in MSHV guests. MSHV has a translate_gva hypercall
that is used to accessing the physical guest memory.
A guest might read from unmapped memor
Add the main vCPU execution loop for MSHV using the MSHV_RUN_VP ioctl.
A translate_gva() hypercall is implemented. The execution loop handles
guest entry and VM exits. There are handlers for memory r/w, PIO and
MMIO to which the exit events are dispatched.
In case of MMIO the i386 instruction dec
On 16/06/2025 17.47, Sean Wei wrote:
The documentation tree has been converted to reStructuredText, but
two entries in MAINTAINERS still point to the removed *.txt files.
This prevents scripts/get_maintainer.pl from matching the documents.
Update those entries to *.rst so the maintainer script
On 01/07/2025 20.06, Sean Wei wrote:
On 2025/7/1 1:24 PM, Thomas Huth wrote:
On 16/06/2025 17.48, Sean Wei wrote:
Several files were renamed in previous commits, causing their entries
in MAINTAINERS to reference outdated paths.
This prevents scripts/get_maintainer.pl from correctly matching
the
Hi Daniel--
Thanks for the followup and the background. What you say makes sense to
me, but i don't know enough about the plumbing to know how i would go
about trying to help make it happen. I ask a few questions below for
hints on how i might move forward.
On Tue 2025-07-01 10:38:02 +0100, Dan
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> There's already a max in-flight VFIO device state buffers *count* limit,
> add also max queued buffers *size* limit.
>
> Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Fabiano Rosas
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Allow capping the maximum count of in-flight VFIO device state buffers
> queued at the destination, otherwise a malicious QEMU source could
> theoretically cause the target QEMU to allocate unlimited amounts of memory
> for buffers-
Convert the guest CPU's CPUID model into MSHV's format and register it
with the hypervisor. This ensures that the guest observes the correct
CPU feature set during CPUID instructions.
Signed-off-by: Magnus Kulke
---
target/i386/mshv/mshv-cpu.c | 199
1 file c
On 2025/7/1 1:24 PM, Thomas Huth wrote:
On 16/06/2025 17.48, Sean Wei wrote:
Several files were renamed in previous commits, causing their entries
in MAINTAINERS to reference outdated paths.
This prevents scripts/get_maintainer.pl from correctly matching
these files to their maintainers.
Update
Add support for writing general-purpose registers to MSHV vCPUs
during initialization or migration using the MSHV register interface. A
generic set_register call is introduced to abstract the HV call over
the various register types.
Signed-off-by: Magnus Kulke
---
include/system/mshv.h |
Peter Xu writes:
> There're a few things off here in that logic, rewrite it. When at it, add
> rich comment to explain each of the decisions.
>
> Since this is very sensitive path for migration, below are the list of
> things changed with their reasonings.
>
> (1) Exact pending size is only ne
From: Philippe Mathieu-Daudé
Trace memory mapped / unmapped in the guest.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20250623121845.7214-8-phi...@linaro.org
Signed-off-by: Peter Maydell
---
meson.build | 1 +
accel/hvf/trace.h | 2 +
Hi Paolo, Peter, Fabiano,
This patch needs review. CPR for vfio is broken without it.
Soft feature freeze July 15.
- Steve
On 6/10/2025 11:39 AM, Steve Sistare wrote:
cpr-transfer breaks vfio network connectivity to and from the guest, and
the host system log shows:
irq bypass consumer (to
Steve Sistare writes:
> cpr-transfer breaks vfio network connectivity to and from the guest, and
> the host system log shows:
> irq bypass consumer (token a03c32e5) registration fails: -16
> which is EBUSY. This occurs because KVM descriptors are still open in
> the old QEMU process.
ohno, I planned to drop this commit (we do not receive hlt exits
from the hypervisor anymore), plz ignore.
Fetch standard register state from MSHV vCPUs to support debugging,
migration, and other introspection features in QEMU.
Fetch standard register state from a MHSV vCPU's. A generic get_regs()
function and a mapper to map the different register representations are
introduced.
Signed-off-by: Magnus
On 16/06/2025 17.51, Sean Wei wrote:
After the docs directory restructuring, several comments
refer to paths that no longer exist.
Replace these references to the current file locations
so readers can find the correct files.
Related commits
---
189c099f75f (Jul 2021)
docs:
QEMU maps certain regions into the guest multiple times, as seen in the
trace below. Currently the MSHV kernel driver will reject those
mappings. To workaround this, a record is kept (a static global list of
"slots", inspired by what the HVF accelerator has implemented). An
overlapping region is no
Build and register the guest vCPU's model-specific registers using
the MSHV interface.
Signed-off-by: Magnus Kulke
---
accel/mshv/meson.build | 1 +
accel/mshv/msr.c| 372
include/system/mshv.h | 23 +++
target/i386/cpu.h |
Am 01.07.2025 um 16:46 hat Hanna Czenczek geschrieben:
> On 30.06.25 13:27, Fiona Ebner wrote:
> > If a node below a filter node is resized, the size of the filter node
> > is now also refreshed (recursively for filter parents).
> >
> > Signed-off-by: Fiona Ebner
> > ---
> > block.c
Introduce the initial scaffold for the MSHV (Microsoft Hypervisor)
accelerator backend. This includes the basic directory structure and
stub implementations needed to integrate with QEMU's accelerator
framework.
Signed-off-by: Magnus Kulke
---
accel/meson.build | 1 +
accel/mshv/meson.bui
Push current model-specific register (MSR) values to MSHV's vCPUs as
part of setting state to the hypervisor.
Signed-off-by: Magnus Kulke
---
target/i386/mshv/mshv-cpu.c | 68 +++--
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/target/i386/mshv/ms
Added mshv to the list of accelerators in doc text.
Signed-off-by: Magnus Kulke
---
docs/devel/codebase.rst | 2 +-
qemu-options.hx | 16
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/docs/devel/codebase.rst b/docs/devel/codebase.rst
index 2a3143787a..6
Implemented handler for HVMSG_X64_HALT exit messages from the
hypervisor.
Signed-off-by: Magnus Kulke
---
accel/mshv/mshv-all.c | 3 +++
include/system/mshv.h | 1 +
target/i386/mshv/mshv-cpu.c | 26 ++
3 files changed, 30 insertions(+)
diff --git a/accel/m
Introduce headers for the Microsoft Hypervisor (MSHV) userspace ABI,
including IOCTLs and structures used to interface with the hypervisor.
These definitions are based on the upstream Linux MSHV interface and
will be used by the MSHV accelerator backend in later patches.
Note that for the time be
To set the local interrupt controller state, perform hv calls retrieving
partition state from the hypervisor.
Signed-off-by: Magnus Kulke
---
target/i386/mshv/mshv-cpu.c | 117
target/i386/mshv/x86.c | 3 +-
2 files changed, 119 insertions(+), 1 deleti
From: Philippe Mathieu-Daudé
Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8".
See arch/arm64/boot/dts/foundation-v8.dts:
https://github.com/torvalds/linux/commit/90556ca1ebdd
Cc: qemu-sta...@nongnu.org
Fixes: 26861c7ce06 ("target-arm: Add minimal KVM AArch64 support")
Fixes: 58
Retrieve special registers (e.g. segment, control, and descriptor
table registers) from MSHV vCPUs.
Various helper functions to map register state representations between
Qemu and MSHV are introduced.
Signed-off-by: Magnus Kulke
---
include/system/mshv.h | 1 +
target/i386/mshv/mshv-cpu
Write CPU register state to MSHV vCPUs. Various mapping functions to
prepare the payload for the HV call have been implemented.
Signed-off-by: Magnus Kulke
---
include/system/mshv.h | 15 +++
target/i386/mshv/mshv-cpu.c | 239
2 files changed, 254 inse
Implement initial interrupt handling logic in the MSHV backend. This
includes management of MSI and un/registering of irqfd mechanisms.
Co-authored-by: Stanislav Kinsburskii
Signed-off-by: Magnus Kulke
---
accel/mshv/irq.c| 369
accel/mshv/meson
Create MSHV vCPUs using MSHV_CREATE_VP and initialize their state.
Register the MSHV CPU execution loop loop with the QEMU accelerator
framework to enable guest code execution.
The target/i386 functionality is still mostly stubbed out and will be
populated in a later commit in this series.
Signed
Add memory listener hooks for the MSHV accelerator to track guest
memory regions. This enables the backend to respond to region
additions, removals and will be used to manage guest memory mappings
inside the hypervisor.
Actually registering physical memory in the hypervisor is still stubbed
out.
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