Hi,
On 6/19/25 4:49 PM, Eric Auger wrote:
> The only change compared to v5 is the linux header update against
> kvm main branch. As discussed on the mailing list, KVM_ARM_VCPU_EL2_E2H0
> (non VHE version of the NV support) will be dealt with in a separate
> add-on series. Also the fallback to TCG d
On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard
>
> We were marking vadc and vsbc as vm=1 instructions, which meant
> vext_check_input_eew wouldn't detect mask vs source register
> overlaps.
>
> Signed-off-by: Anton Blanchard
> Reviewed-by: Max Chou
> Signed-off-by: Max Chou
> ---
On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard
>
> Handle the overlap of source registers with different EEWs.
>
> Signed-off-by: Anton Blanchard
> Reviewed-by: Max Chou
> Signed-off-by: Max Chou
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 22 --
> 1
On 6/30/25 9:01 AM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Friday, June 27, 2025 12:52 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol
Fabiano Rosas writes:
> The MigrationState is a QOM object with TYPE_DEVICE as a parent. This
> was done about eight years ago so the migration code could make use of
> qdev properties to define the defaults for the migration parameters
> and to be able to expose migration knobs for debugging via
On 6/30/25 9:12 AM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Friday, June 27, 2025 1:37 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.c
On 6/30/25 9:11 AM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Friday, June 27, 2025 1:36 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.c
Fabiano Rosas writes:
> Caught by inspection, but ASAN also reports:
>
> Direct leak of 16 byte(s) in 1 object(s) allocated from:
> #0 in malloc
> #1 in g_malloc
> #2 in g_memdup
> #3 in qapi_clone_start_struct ../qapi/qapi-clone-visitor.c:40:12
> #4 in qapi_clone_start_list ../qapi/qapi-clo
Hi,
On 7/1/25 5:05 AM, Shaoqin Huang wrote:
> Set the "use-legacy-x86-rom" property to false by default, and only set
> it to true on x86 since only x86 will need it.
>
> At the same time, set the "use-legacy-x86-rom" property to true on those
> historical versioned machine types in order to avoi
Hi Shaoqin,
On 7/1/25 5:05 AM, Shaoqin Huang wrote:
> Currently the ramfb device loads the vgabios-ramfb.bin unconditionally,
> but only the x86 need the vgabios-ramfb.bin, this can cause that when
> use the release package on arm64 it can't find the vgabios-ramfb.bin.
>
> Because only seabios wi
On 6/27/2025 9:21 PM, Max Chou wrote:
> According to the RISC-V instruction set manual, the minimum VLEN needs
> to respect the following extensions:
>
>Extension Minimum VLEN
> * V 128
> * Zve64[d|f|x] 64
> * Zve32[f|x] 32
>
> Signed-off-by: Max Chou
> ---
> target/ris
On 7/1/2025 11:00 AM, Jay Chang wrote:
> RISC-V Privileged Spec states:
> "In harts with S-mode, the medeleg and mideleg registers must exist, and
> setting a bit in medeleg or mideleg will delegate the corresponding trap
> , when occurring in S-mode or U-mode, to the S-mode trap handler. In
> hart
On 7/1/2025 11:00 AM, Jay Chang wrote:
> RISC-V AIA Spec states:
> "For a machine-level environment, extension Smaia encompasses all added
> CSRs and all modifications to interrupt response behavior that the AIA
> specifies for a hart, over all privilege levels. For a supervisor-level
> environment
Patch 1 adds a predicate to restrict access to "medeleg, mideleg, and
medelegh" to harts that support S-mode.
Patch 2 adds a privilege check for the "midelegh" CSR, which is defined by
the AIA extension and only valid when Smaia is supported. This is enforced
via an updated predicate in aia_sm
Currently the ramfb device loads the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specifi
Set the "use-legacy-x86-rom" property to false by default, and only set
it to true on x86 since only x86 will need it.
At the same time, set the "use-legacy-x86-rom" property to true on those
historical versioned machine types in order to avoid the memory layout
being changed.
Signed-off-by: Shao
RISC-V Privileged Spec states:
"In harts with S-mode, the medeleg and mideleg registers must exist, and
setting a bit in medeleg or mideleg will delegate the corresponding trap
, when occurring in S-mode or U-mode, to the S-mode trap handler. In
harts without S-mode, the medeleg and mideleg registe
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentially the same as Smai
Currently the ramfb device loads the vgabios-ramfb.bin unconditionally,
but only the x86 need the vgabios-ramfb.bin, this can cause that when
use the release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specifi
On Wed, Jun 18, 2025 at 11:58 PM Laurent Vivier wrote:
>
> This commit introduces support for passt as a new network backend.
> passt is an unprivileged, user-mode networking solution that provides
> connectivity for virtual machines by launching an external helper process.
>
> The implementation
On Wed, Jun 18, 2025 at 11:57 PM Laurent Vivier wrote:
>
> Previously, the vhost_net_get_feature_bits() function in
> hw/net/vhost_net.c used a large switch statement to determine
> the appropriate feature bits based on the NetClientDriver type.
>
> This created unnecessary coupling between the ge
On Wed, Jun 18, 2025 at 11:57 PM Laurent Vivier wrote:
>
> Currently, several parts of the codebase check if a network client is a
> vhost-user backend by directly comparing its type against the
> NET_CLIENT_DRIVER_VHOST_USER enum. This creates a tight coupling
> between virtio/vhost-net drivers a
On 6/30/2025 1:20 PM, Zhao Liu wrote:
+if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
+*ecx = *edx = 0;
+break;
+}
current code guarantees ecx and edx to be 0 for !IS_AMD_CPU(). I think the
patch is unnecessary.
Hi, could you please tell me why?
* Daniel Henrique Barboza (dbarb...@ventanamicro.com) wrote:
Hi Daniel,
> The RISC-V target has *a lot* of CPU registers, with more registers
> being added along the way when new extensions are added. In this world,
> 'info registers' will throw a wall of text that can be annoying to deal
> with
On Mon, Jun 16, 2025 at 5:02 PM wrote:
>
> Address an error in migration when aia is configured as 'aplic-imsic' in
> riscv kvm vm by adding riscv_aplic_state_needed() and
> riscv_imsic_state_needed() to determine whether the corresponding sates are
> needed.
>
> Previously, the fields in the vmsd
On Mon, 30 Jun 2025 at 21:22, Bernhard Beschow wrote:
>
>
>
> Am 30. Juni 2025 09:09:31 UTC schrieb Peter Maydell
> :
> >On Sun, 29 Jun 2025 at 21:49, Bernhard Beschow wrote:
> >>
> >> Allows the imx8mp-evk machine to be run with KVM acceleration as a guest.
> >>
> >> Signed-off-by: Bernhard Bes
Am 30. Juni 2025 08:58:22 UTC schrieb "Philippe Mathieu-Daudé"
:
>Hi,
>
>On 29/6/25 22:48, Bernhard Beschow wrote:
>> Allows the imx8mp-evk machine to be run with KVM acceleration as a guest.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> docs/system/arm/imx8mp-evk.rst | 7 +++
>> hw
Hi,
On 1/31/25 08:34, Cédric Le Goater wrote:
Hello Jamin,
On 1/21/25 08:04, Jamin Lin wrote:
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
With the patch applied, QEMU now supports two machines for running AST2700 SoC
Am 30. Juni 2025 09:09:31 UTC schrieb Peter Maydell :
>On Sun, 29 Jun 2025 at 21:49, Bernhard Beschow wrote:
>>
>> Allows the imx8mp-evk machine to be run with KVM acceleration as a guest.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> docs/system/arm/imx8mp-evk.rst | 7 +++
>> hw/arm/f
On 6/30/25 12:23 PM, mindentropy wrote:
On Tue, Jul 1, 2025 at 12:27 AM Pierrick Bouvier
wrote:
You can get verbose command for building by using make V=1, or ninja -v,
depending which command you like to use.
Then, you can get a preprocessed output by using '-E' gcc option.
Don't forget to r
Allow migrate_start_set_capabilities() to set the config object
instead of setting the capabilities via calls to
migrate-set-capabilities.
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration/framework.c | 31 +++
tests/qtest/migration/framework.h | 1 +
2 files ch
Use the existing file tests to test the new way of passing parameters
to the migration via the config argument to qmp_migrate*.
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration/file-tests.c| 68 +++
tests/qtest/migration/framework.c | 9 ++--
tests/qtest/mi
Adapt the convergence routines migrate_ensure_[non_]converge to
receive a config argument and set the convergence parameters in it
instead of using migrate-set-parameters.
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration/framework.c | 10 +-
tests/qtest/migration/migration-qmp.
The documentation of qobject_from_jsonv() states that it takes
ownership of any %p arguments passed in.
Next patches will add config-passing to the tests, so take an extra
reference in the migrate_qmp* functions to ensure the config is not
freed from under us.
Signed-off-by: Fabiano Rosas
---
t
Convert the code in migrate_params_test_apply() from an open-coded
copy of every migration parameter to a copy using visitors. The
current code has conditionals for each parameter's has_* field, which
is exactly what the visitors do.
This hides the details of QAPI from the migration code and avoid
Use QAPI_CLONE_MEMBERS instead of making an assignment. The QAPI
method makes the handling of the TLS strings more intuitive because it
clones them as well.
Signed-off-by: Fabiano Rosas
---
migration/options.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
dif
The QERR_INVALID_PARAMETER_VALUE macro is documented as not to be used
in new code. Remove the usage from migration/options.c.
Signed-off-by: Fabiano Rosas
---
migration/migration.c | 3 +--
migration/options.c| 56 +++---
migration/page_cache.c | 6 ++-
The MigrationParameter (singular) enumeration is not part of the
migration QMP API, it's only used for nicely converting HMP strings
into MigrationParameters (plural) members and for providing readline
completion.
Documenting this enum only serves to duplicate documentation between
MigrationParame
MigrationParameters needs to have all of its has_* fields marked as
true when used as the return of query_migrate_parameters because the
corresponding QMP command has all of its members non-optional by
design, despite them being marked as optional in migration.json.
Extract this code into a functi
Last patch added capabilities to s->parameters. Now we can replace all
instances of s->capabilities with s->parameters:
- The -global properties now get set directly in s->parameters.
- Accessors from options.c now read from s->parameters.
- migrate_caps_check() now takes a MigrationParameters o
Add capabilities to MigrationParameters. This structure will hold all
migration options. Capabilities will go away in the next patch.
Also add capabilities to MigrationParameter as the enum needs to be
kept in sync with MigrationParameters. This affects the parsing of
migration HMP commands so mak
Allow the migrate and migrate_incoming commands to pass the migration
configuration options all at once, dispensing the use of
migrate-set-parameters and migrate-set-capabilities.
The motivation of this is to simplify the interface with the
management layer and avoid the usage of several command i
Now that the TLS options have been made the same between
migrate-set-parameters and query-migrate-parameters, a single type can
be used. Remove MigrateSetParameters.
The TLS options documentation from MigrationParameters were replaced
with the ones from MigrateSetParameters which was more complete
The QAPI converts an empty list on the block-bitmap-mapping input into
a NULL BitmapMigrationNodeAliasList. The empty list is a valid input
for the block-bitmap-mapping option, so commit 3cba22c9ad ("migration:
Fix block_bitmap_mapping migration") started using the
s->parameters.has_block_bitmap_ma
Instead of setting parameters one by one, use the temporary object,
which already contains the current migration parameters plus the new
ones and was just validated by migration_params_check(). Use cloning
to overwrite it.
This avoids the need to alter this function every time a new parameter
is a
Each migration parameters has a default value, store them for later
use in resetting s->parameters. Values overridden via the command line
with the debugging option -global migration. will be included.
Make the structure const and change the appropriate signatures to make
sure its values are not c
The concept of capabilities is being merged into the concept of
parameters. From now on, the commands that handle capabilities are
deprecated in favor of the commands that handle parameters.
Affected commands:
- migrate-set-capabilities
- query-migrate-capabilities
Signed-off-by: Fabiano Rosas
The migration parameters tls_creds, tls_authz and tls_hostname
currently have a non-uniform handling. When used as arguments to
migrate-set-parameters, their type is StrOrNull and when used as
return value from query-migrate-parameters their type is a plain
string.
Not only having to convert betwe
The migration parameters validation produces a temporary structure
which is the merge of the current parameter values (s->parameters,
MigrationParameters) with the new parameters set by the user
(former MigrateSetParameters).
When copying the values from s->parameters into the temporary
structure,
QAPI_CLONE_MEMBERS is a better option than copying parameters one by
one because it operates on the entire struct and follows pointers. It
also avoids the need to alter this function every time a new parameter
is added.
For this to work, the has_* fields of s->parameters need to be already
set bef
Do a cleanup of hmp_info_migrate_parameters() before adding more lines
into it:
- Make sure every parameter asserts that the has_* field is
set. qmp_query_migrate_parameters should have set them all. (except
for block-bitmap-mapping)
- Remove the if (params), qmp_query_migrate_parameters neve
Some migration parameters are updated immediately once they are set
via migrate-set-parameters. Move that work outside of
migrate_params_apply() and leave that function with the single
responsibility of setting s->parameters and not doing any
side-effects.
Reviewed-by: Peter Xu
Signed-off-by: Fab
Caught by inspection, but ASAN also reports:
Direct leak of 16 byte(s) in 1 object(s) allocated from:
#0 in malloc
#1 in g_malloc
#2 in g_memdup
#3 in qapi_clone_start_struct ../qapi/qapi-clone-visitor.c:40:12
#4 in qapi_clone_start_list ../qapi/qapi-clone-visitor.c:59:12
#5 in visit_start_l
Merge migration capabilities and parameters in MigrationState and
deprecate migration capabilities QMP commands.
v2:
- TLS options:
- Normalize to "abc"|"" during parameter handling.
- Normalize to "abc"|NULL when exposing to rest of migration
code.
- Reverted block_bitmap_mapping to tru
The MigrationState is a QOM object with TYPE_DEVICE as a parent. This
was done about eight years ago so the migration code could make use of
qdev properties to define the defaults for the migration parameters
and to be able to expose migration knobs for debugging via the
'-global migration' command
On 6/6/25 6:31 AM, Daniel P. Berrangé wrote:
> On Wed, Jun 04, 2025 at 05:56:31PM -0400, Zhuoying Cai wrote:
>> Create a certificate store for boot certificates used for secure IPL.
>>
>> Load certificates from the boot-certificate parameter of s390-ccw-virtio
>> machine type option into the cert s
On 6/24/25 11:03 AM, Jared Rossi wrote:
>
>
> On 6/20/25 11:45 AM, Zhuoying Cai wrote:
>> On 6/6/25 10:00 AM, Daniel P. Berrangé wrote:
>>> On Wed, Jun 04, 2025 at 05:56:29PM -0400, Zhuoying Cai wrote:
Add boot-certificates as a parameter of s390-ccw-virtio machine type
option.
>>
On Tue, Jul 1, 2025 at 12:27 AM Pierrick Bouvier
wrote:
>
> You can get verbose command for building by using make V=1, or ninja -v,
> depending which command you like to use.
>
> Then, you can get a preprocessed output by using '-E' gcc option.
> Don't forget to remove -o option, emitting the obj
Hi Gautam,
On 6/28/25 3:18 AM, mindentropy wrote:
Hi,
Is there an option to generate preprocessor output while building the
QEMU code? It makes it easier to understand some of the macro template
function generation.
-Gautam.
You can get verbose command for building by using make V=1, or nin
On 6/20/25 9:59 PM, liu.xuem...@zte.com.cn wrote:
From: Xuemei Liu
This adds powerdown support by implementing the ACPI GED.
Signed-off-by: Xuemei Liu
Co-authored-by: Björn Töpel
---
Changes in v3:
- Added missing param to virt_is_acpi_enabled
- Fixed failure of bios-tables-test
hw/ri
On 6/30/25 1:00 PM, Philippe Mathieu-Daudé wrote:
Hi Daniel,
On 30/6/25 15:22, Daniel Henrique Barboza wrote:
The RISC-V target has *a lot* of CPU registers, with more registers
being added along the way when new extensions are added. In this world,
'info registers' will throw a wall of text
On Fri, 27 Jun 2025 16:38:16 +
Anisa Su wrote:
> On Fri, Jun 27, 2025 at 10:48:59AM +0100, Jonathan Cameron wrote:
> > On Thu, 26 Jun 2025 23:41:15 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > Per the spec, FMAPI commands (0x51-0x59) must be bound with
> >
When grabbing a patch series, the link trailer is replaced with a
Message-ID, which is not useful compared to an URL. Fix that by
dropping the linktrailermask config.
Cc: Signed-off-by: Philippe Mathieu-Daudé
Cc: Jiaxun Yang
Fixes: 838cf72b5d2c ("Add a b4 configuration file")
Signed-off-by: Cé
Both quilt, to apply patches, and cscope, to navigate in the code, are
useful tools. Make sure source files that quilt saves when applying
patches are not taken into account when building the cscope database.
Signed-off-by: Cédric Le Goater
---
Makefile | 1 +
1 file changed, 1 insertion(+)
dif
On 6/26/25 12:19 PM, Matthew Rosato wrote:
> On 6/9/25 12:44 PM, Rorie Reyes wrote:
>> Handle interception of the CHSC SEI instruction for requests
>> indicating the guest's AP configuration has changed.
>>
>> If configuring --without-default-devices, hw/s390x/ap-stub.c
>> was created to handle suc
On Thu, 26 Jun 2025 22:23:33 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
A few more long line related tweaks.
> ---
> hw/cxl/cxl-mailbox-utils.c | 79 ++
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
Simplify PMU logic by rewriting '!KVM' as 'TCG || HVF'
(ignoring QTest, because vCPUs are not available there).
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 2 +-
target/arm/machine.c | 10 +-
2 files changed, 6
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
Simplify PMU logic by rewriting '!KVM' as 'TCG || HVF'
(ignoring QTest, because vCPUs are not available there).
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 2 +-
target/arm/machine.c | 10 +-
2 files changed, 6
On Thu, 26 Jun 2025 22:23:32 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
There are a few long lines in here check patch doesn't like.
I tweaked as described inline whilst picking them up.
>
> Si
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/tlb_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index 23c72a99f5c..df04ef351d1 100644
--- a/
Generation of a QEMU based instruction set simulator from a processor
description in OpenVADL (SAMOS’25)
QEMU (Quick EMUlator) is a generic and open source machine emulator and
virtualizer which employs
Dynamic Binary Translation (DBT) to emulate a guest architecture on a host
architecture. Ope
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
It is useful to compare PSCI calls of the same guest running
under TCG or HVF.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/hvf/hvf.c| 3 ++-
target/arm/tcg/psci.c | 3 +++
target/arm/trace-events | 3 +++
3 files changed, 8 i
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
Re-use arm_is_psci_call() instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/hvf/hvf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Pierrick Bouvier
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
Only allow disabling NEON when using TCG.
This avoids confusing user experience:
$ qemu-system-aarch64 -M virt -accel hvf \
-cpu host,neon=off,vfp=off,vfp-d32=off
qemu-system-aarch64: AArch64 CPUs must have both VF
On 6/30/25 6:09 AM, Philippe Mathieu-Daudé wrote:
Commit 34c45d53026 ("target-arm: kvm - re-inject guest debug
exceptions") removed CPU_INTERRUPT_EXITTB from KVM, but it
also appears on HVF. Better to restrict it to TCG.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
Currently, execlog searches for a space separator between the
instruction mnemonic and operands, but some disassemblers, e.g. Alpha's,
use a tab separator instead; this results in a null pointer being passed
as the haystack in g_strstr during a subsequent register search, i.e.
undefined behavior, b
This patch adds the GDB XML feature file that describes Alpha's core
registers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2569
Reviewed-by: Richard Henderson
Signed-off-by: Yodel Eldar
---
configs/targets/alpha-linux-user.mak | 1 +
configs/targets/alpha-softmmu.mak| 1 +
This patch adds TCG plugin register tracking support for the Alpha
target and resolves gitlab issue #2569:
https://gitlab.com/qemu-project/qemu/-/issues/2569
As mentioned in the bug report by Alex Bennée, the register list is
built using the target's corresponding GDB XML feature file, but the
On Thu, 26 Jun 2025 22:23:26 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section
> 7.6.7.6.2
>
> Reviewed-by: Fan Ni
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 103
On Sat, 28 Jun 2025 at 20:57, Gustavo Romero wrote:
>
> Since v2:
> - Fixed no_tcg_its inverted logic (rth)
>
> Since v3:
> - Fixed remappings in the IORT table when ITS is no present
> - Rebased on master and resoled conflics, like no more "no_its"
> flag in VirtMachineClass
> - Dropped patch 1
On Mon, Jun 30 2025, Peter Maydell wrote:
> On Tue, 17 Jun 2025 at 16:39, Cornelia Huck wrote:
>>
>> Mostly addressed Peter's feedback:
>> - make sure every inbetween stage compiles (also fixed some bonus issues)
>> - try to make the scripts more robust, add a note the generated file,
>> and m
Hi Daniel,
On 30/6/25 15:22, Daniel Henrique Barboza wrote:
The RISC-V target has *a lot* of CPU registers, with more registers
being added along the way when new extensions are added. In this world,
'info registers' will throw a wall of text that can be annoying to deal
with when the user wants
On Wed, 25 Jun 2025 at 11:59, William Kosasih wrote:
>
> Historically, M-profile helper functions in m_helper.c and mve_helper.c
> used the unaligned cpu_*_data_ra() routines to perform guest memory
> accesses. This meant we had no way to enforce alignment constraints
> when executing helper-based
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c9c53f796f..043568a10d 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1847,7 +1847,7 @@ static b
On 30/6/25 16:38, Peter Maydell wrote:
On Tue, 17 Jun 2025 at 10:30, Mads Ynddal wrote:
I've both publicly and private been digging around the Apple Silicon HVF code,
and use it daily as part of my job. I feel I have a solid understanding of it,
so I thought I'd step up and assist.
I've added
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 673849f07a..0b441bc611 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2675,7 +2675,7 @@ static b
Both cases are handled by fold_xor after conversion.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index a48ddd9171..62a128bc9b 100644
--- a/tcg/optimize.c
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 49ef039932..d9ccbb36e2 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1422,7 +14
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 42d5ee23c0..abcbee9111 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2097,7 +2097,7 @@ static bo
On 30/6/25 15:53, Richard Henderson wrote:
On 6/30/25 07:09, Philippe Mathieu-Daudé wrote:
It is useful to compare PSCI calls of the same guest running
under TCG or HVF.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/hvf/hvf.c | 3 ++-
target/arm/tcg/psci.c | 3 +++
target/arm/t
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 103c94b12f..42d5ee23c0 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2039,25 +2039,31 @@
On 30/6/25 15:56, Richard Henderson wrote:
On 6/30/25 07:09, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/tlb_helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
in
The following changes since commit aec6836c73403cffa56b9a4c5556451ee16071fe:
Merge tag 'pull-vfio-20250626' of https://github.com/legoater/qemu into
staging (2025-06-26 10:25:01 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 758f7b142e..29d1f29124 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -2231,16 +2231,22
This was the last use of fold_affected_mask,
now fully replaced by fold_masks_zosa.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 30 ++
1 file changed, 6 insertions(+), 24 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize
Fix the direction of the shift, introduced when converting
the codebase to TCGOutOp* and small tgen_* helpers.
Fixes: 5a4d034f3cb ("tcg: Convert extract to TCGOutOpExtract")
Reported-by: Andrea Bolognani
Signed-off-by: Richard Henderson
Tested-by: Andrea Bolognani
Tested-by: Philippe Mathieu-Da
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 49 -
1 file changed, 24 insertions(+), 25 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 572d314578..c9c53f796f 100644
--- a/tcg/optimize.c
+++ b
On Mon, 23 Jun 2025 at 13:20, Philippe Mathieu-Daudé wrote:
>
> QDev uses _post_init() during instance creation, before being
> realized. Since here both vCPUs and GIC are REALIZED, rename
> as virt_post_cpus_gic_realized() for clarity.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Ric
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 043568a10d..f5fc0cfff9 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1963,7 +1963,7 @@ s
When lowering tst comparisons, completely fold the and
opcode that we generate.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 0b441bc611..aa64f15779 100644
--- a/tc
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