On 6/23/25 17:54, Anushree Mathur wrote:
Hi Richard,
Any updates on this issue? Would really appreciate your inputs here.
Thanks in advance!
Regards,
Anushree-Mathur
Hi Richard,
Could you please share some inputs to investigate/debug this further ?
Thanks,
Chinmay
Hi Jamin,
On 30.06.25 08:37, Cédric Le Goater wrote:
Hello Tan,
On 6/29/25 15:54, Tan Siewert wrote:
This adds basic tests for the ASPEED System Control Unit (SCU) and its
protection mechanism on the AST2500 and AST2600 platforms.
The tests verify:
- That SCU protection registers can be un
On 6/19/25 15:28, Chinmay Rath wrote:
Moving floating point rounding, conversion, compare and move
instructions to decodetree specification.
Hi Richard,
Could you please share your review comments on this series ?
Thanks,
Chinmay
Also proposing myself as a reviewer for PowerPC TCG CPUs.
On 6/19/25 17:27, Cédric Le Goater wrote:
On 6/19/25 11:58, Chinmay Rath wrote:
I have been working on Power ISA for a long time now and have mostly
contributed in TCG instruction translation area (moved 300+
instructions to
decodetree as of yet) and would like to continue contributing to PPC
Hi Cédric,
Got it, I'll rename the type to "aspeed-otp" as suggested to support the global
property syntax.
Thanks for the clarification!
Best regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, June 30, 2025 2:28 PM
> To: Kane Chen ; Peter Maydell
> ; Steven L
Hello Tan,
On 6/29/25 15:54, Tan Siewert wrote:
This adds basic tests for the ASPEED System Control Unit (SCU) and its
protection mechanism on the AST2500 and AST2600 platforms.
The tests verify:
- That SCU protection registers can be unlocked and locked again
- That modifying the primary
Hello Kane,
On 6/30/25 07:17, Kane Chen wrote:
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse arr
On 6/30/25 07:17, Kane Chen wrote:
From: Kane-Chen-AS
This patch introduces a QEMU model of the ASPEED One-Time Programmable
(OTP) memory, used for secure fuse storage. The model simulates a
word-addressable OTP region with a memory-like interface via a dedicated
AddressSpace.
If no external b
Hi Cédric,
Thanks for pointing that out — sorry for missing your earlier comment.
I'll roll back the BlockBackend and drive part, and send a separate patch for
that as suggested.
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, June 30, 2025 2:18 PM
> To
On 6/30/25 07:17, Kane Chen wrote:
From: Kane-Chen-AS
This patch introduces a QEMU model of the ASPEED One-Time Programmable
(OTP) memory, used for secure fuse storage. The model simulates a
word-addressable OTP region with a memory-like interface via a dedicated
AddressSpace.
If no external b
On 6/30/25 07:17, Kane Chen wrote:
From: Kane-Chen-AS
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands a
On 6/30/25 07:17, Kane Chen wrote:
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed_ast2600.c | 2 +-
On 30/6/25 04:44, Collin Walling wrote:
Now that the deprecated_props is an optional field, the expansion method
must now set the "has_deprecated_props" flag in order for the data to be
output from the response.
Fixes: 448553bb7c (qapi: Make CpuModelExpansionInfo::deprecated-props optional
and
On 27/6/25 13:25, Alex Bennée wrote:
Seeing as I've taken a few patches to here now I might as well put
myself forward to maintain virtio-gpu. I've marked it as Odd Fixes as
it is not my core focus. If someone with more GPU experience comes
forward we can always update again.
Reviewed-by: Markus
From: Kane-Chen-AS
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32-bi
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --
From: Kane-Chen-AS
This patch introduces a QEMU model of the ASPEED One-Time Programmable
(OTP) memory, used for secure fuse storage. The model simulates a
word-addressable OTP region with a memory-like interface via a dedicated
AddressSpace.
If no external block backend is provided via the "dri
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
> > +if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
> > +*ecx = *edx = 0;
> > +break;
> > +}
>
> current code guarantees ecx and edx to be 0 for !IS_AMD_CPU(). I think the
> patch is unnecessary.
Hi, could you please tell me why?
Thanks,
Zhao
> >
Add FEAT_MEC registers to the arm max cpu.
To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are
not implemented in this commit. The bits in SCTLR2 and TCR2 control which
translation regimes use MECIDs, and determine which MECID is selected.
Signed-off-by: Gustavo Romero
The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from
EL2, so add it to the SCR mask list to use it later on.
Signed-off-by: Gustavo Romero
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 302c24e232..8ce30ca857
This series a WIP for adding full FEAT_MEC support to arm max cpu.
It adds the FEAT_MEC registers but does not touch the translation regimes to
support the MECIDs. I'm currently looking at the possibilies to support it in
QEMU for the various translation regimes we have on Arm64.
Cheers,
Gustavo
Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a
first step to fully support FEAT_MEC.
The FEAT_MEC is an extension to FEAT_RME that implements multiple
Memory Encryption Contexts (MEC) so the memory in a realm can be
encrypted and accessing it from the wrong encryption conte
Now that the deprecated_props is an optional field, the expansion method
must now set the "has_deprecated_props" flag in order for the data to be
output from the response.
Fixes: 448553bb7c (qapi: Make CpuModelExpansionInfo::deprecated-props optional
and generic)
Signed-off-by: Collin Walling
--
On Fri, Jun 27, 2025 at 11:31 PM Max Chou wrote:
>
> According to the V spec, the vector fault-only-first load instructions
> may change the VL CSR.
> So the ldff_trans TCG translation function should generate the
> lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
> make sure
On 6/26/25 4:31 PM, Zhao Liu wrote:
From: Ewan Hai
Add the cache model to YongFeng (v3) to better emulate its
environment.
Note, although YongFeng v2 was added after v10.0, it was also back
ported to v10.0.2. Therefore, the new version (v3) is needed to avoid
conflict.
The cache model is
On 6/29/25 1:50 PM, Alex Bennée wrote:
Yodel Eldar writes:
Currently, execlog searches for a space separator between the
instruction mnemonic and operands, but some disassemblers, e.g. Alpha's,
use a tab separator instead; this results in a null pointer being passed
as the haystack in g_strs
This series adds KVM support to the imx8mp-evk machine, both as a guest and as a
KVM host. Turning imx8mp-evk into a KVM host just required wiring up two
interrupts (patch 1) while implementing `-accel kvm` required more work, drawing
inspiration from the virt machine (patch 2).
Testing done:
* Ru
Allows to run KVM guests inside the imx8mp-evk machine.
Fixes: a4eefc69b237 ("hw/arm: Add i.MX 8M Plus EVK board")
CC: qemu-stable
Signed-off-by: Bernhard Beschow
---
hw/arm/fsl-imx8mp.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c
index 23e66
Allows the imx8mp-evk machine to be run with KVM acceleration as a guest.
Signed-off-by: Bernhard Beschow
---
docs/system/arm/imx8mp-evk.rst | 7 +++
hw/arm/fsl-imx8mp.c| 33 -
hw/arm/imx8mp-evk.c| 11 +++
hw/arm/Kconfig
Yodel Eldar writes:
> Currently, execlog searches for a space separator between the
> instruction mnemonic and operands, but some disassemblers, e.g. Alpha's,
> use a tab separator instead; this results in a null pointer being passed
> as the haystack in g_strstr during a subsequent register sear
This adds basic tests for the ASPEED System Control Unit (SCU) and its
protection mechanism on the AST2500 and AST2600 platforms.
The tests verify:
- That SCU protection registers can be unlocked and locked again
- That modifying the primary protection register on AST2600 also
affects the
On Thu, Jun 26, 2025 at 10:55:14PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> So tired to parse all these timestamps, when need to compare them
> with other logs.
>
> Use iso8601 format as in warn_report() (info_report(), error_report())
> already used.
>
> Also, start line with date, to be sim
On 6/25/25 4:36 AM, Alexandre Ghiti wrote:
Hi Daniel,
On Sat, Jun 7, 2025 at 7:54 PM Daniel Henrique Barboza
wrote:
On 6/5/25 11:21 AM, Alexandre Ghiti wrote:
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Signed-off-by: Alexandre Ghiti
-
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