[PATCH v2 2/3] Socket activation: get FD by label

This uses the cached copy of LISTEN_FDNAMES to find the first file descriptorlabel with a matching label. Note that if two file descriptors are given the same label this will ignore all but the first. This is another step toward addressing https://gitlab.com/qemu-project/qemu/-/issues/3011 Signe

[PATCH v2 3/3] Socket activation: enable spice listener.

Enable qemu to be socket-activated based on a spice connection. Note that this depends on un-deprecating spice_server_set_listen_socket_fd, see https://gitlab.freedesktop.org/spice/spice/-/merge_requests/240 This partially addresses https://gitlab.com/qemu-project/qemu/-/issues/3011 Signed-off-b

[PATCH v2 1/3] Socket Activation: stash $LISTEN_FDNAMES

By recording a copy of LISTEN_FDNAMES, we make it possible to learn mappings from file descriptor labels (e.g., as set by FileDescriptorName= in systemd.socket(5)). This also makes it possible to invoke check_socket_activation() more than once and have it return the same value each time. This is

Clean up (v2) of Socket Activation series

This is a clean-up of the code I offered yesterday to improve socket activation for qemu. It resolves a couple dumb bugs i had initially introduced, and reduces the line-width of some of the new code. This is addressing https://gitlab.com/qemu-project/qemu/-/issues/3011 I welcome reviews and f

Re: [PATCH] qtest/migration: Fix potential NPD through getenv

Hi, thank you for getting back to me. During my data mining, I came across the following operation: migration_get_env, which is called after find_common_machine_version. Based on this, I initially suspected there might be a bug. Here's the relevant code inside migration_get_env. env->qemu_src =

[PATCH v6 1/9] hw/intc/gicv3_its: Do not check its_class_name()

From: Philippe Mathieu-Daudé Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), the single implementation of its_class_name() no longer returns NULL (it now always returns a valid char pointer). Hence, update the prototype docstring and remove the tautological checks that use the its_c

[PATCH v6 6/9] qtest/bios-tables-test: Add test for when ITS is off on aarch64

From: Philippe Mathieu-Daudé Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of hardware introduced in GICv3 and, being optional, it can be disabled in QEMU aarch64 VMs that support it using machine option "its=off", like, for instance: "-M virt,its=off". In ACPI, the ITS is a

[PATCH v6 8/9] hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=off

Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct in the MADT table are always generated, even if GIC ITS is not available on the machine. This commit fixes it by not generating the ITS Group nodes, not mapping any other node to them, and not advertising the GIC ITS in the MA

[PATCH v6 7/9] qtest/bios-tables-test: Add blobs for its=off test on aarch64

Add blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a new variant, .its_off, that requires variations of the MADT and IORT tables. MADT (aka APIC) diff: +[000h 4]Signature : "APIC"[Multiple APIC Description Table (MADT)] +[004h 0004 4]

[PATCH v6 9/9] qtest/bios-tables-test: Update blobs for its=off test on aarch64

Update blobs for the its=off test on aarch64 after fix. Basically, all structs related to ITS are gone in MADT and IORT tables after the fix (previously ITS was not properly disabled when "its=off" option was passed to the machine). MADT diff: [000h 4]Signature : "API

[PATCH v6 4/9] hw/arm/virt-acpi-build: Improve comment in build_iort

When building the Root Complex table, the comment about the code that maps the RC node to SMMU node is misleading because it reads "RC -> SMMUv3 -> ITS", but the code is only mapping the RCs IDs to the SMMUv3 node. The step of mapping from the SMMUv3 IDs to the ITS Group node is actually defined in

[PATCH v6 2/9] hw/arm/virt: Simplify logic for setting instance's 'tcg_its' variable

Because 'tcg_its' in the machine instance is set based on the machine class’s negated variable 'no_tcg_its', 'tcg_its' is the opposite of 'no_tcg_its' and hence the code in question can be simplified as: tcg_its = !no_tcg_its. Signed-off-by: Gustavo Romero Reviewed-by: Eric Auger --- hw/arm/vir

[PATCH v6 5/9] hw/arm/virt-acpi-build: Factor out create_its_idmaps

Factor out a new function, create_its_idmaps(), from the current build_iort code. Add proper comments to it clarifying how the ID ranges that go directly to the ITS Group node are computed based on the ones that are directed to the SMMU node. Suggested-by: Eric Auger Signed-off-by: Gustavo Romero

[PATCH v6 3/9] hw/arm/virt: Simplify create_its()

From: Philippe Mathieu-Daudé No need to strstr() check the class name when we can use kvm_irqchip_in_kernel() to check if the ITS from the host can be used. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Reviewed-by: Gustavo Romero --- hw/arm/vi

[PATCH-for-10.1 v6 0/9] hw/arm: GIC 'its=off' ACPI table fixes

Since v2: - Fixed no_tcg_its inverted logic (rth) Since v3: - Fixed remappings in the IORT table when ITS is no present - Rebased on master and resoled conflics, like no more "no_its" flag in VirtMachineClass - Dropped patch 1/9 because we actually want the instance flags, not only the class f

Re: [PATCH v5 8/9] hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=off

Hi Eric, On 6/27/25 12:44, Eric Auger wrote: Hi Gustavo, On 6/23/25 3:57 PM, Gustavo Romero wrote: Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct in the MADT table are always generated, even if GIC ITS is not available on the machine. This commit fixes it by not gener

Re: [PATCH v5 5/9] hw/arm/virt-acpi-build: Factor out create_its_idmaps

Hi Eric, Thanks a lot for another round of reviews :) On 6/27/25 12:28, Eric Auger wrote: Hi Gustavo, On 6/23/25 3:57 PM, Gustavo Romero wrote: Factor out a new function, create_its_idmaps(), from the current I would call it build_rc_its_idmap() to be clearer on what relationship we build.

[PATCH 04/10] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iomm

[PATCH v5 00/10] intel_iommu: Add ATS support

This patch set belongs to a list of series that add SVM support for VT-d. Here we focus on implementing the ATS API exposed through the PCIIOMMUOps callbacks. This work is based on the VT-d specification version 4.1 (March 2023). Here is a link to our GitHub repository where you can find: - Q

[PATCH 10/10] intel_iommu: Add support for ATS

Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 63 +++ 1 file changed, 63 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1b1b0b5632..fe9a5f2872 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c

[PATCH 05/10] intel_iommu: Declare supported PASID size

the PSS field of the extended capabilities stores the supported PASID size minus 1. This commit adds support for 8bits PASIDs (limited by MemTxAttrs::pid). Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 ins

[PATCH 06/10] intel_iommu: Implement vtd_get_iotlb_info from PCIIOMMUOps

Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 71497f1936..affa7768e6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4733,10 +4733,20 @@ static A

[PATCH 08/10] intel_iommu: Return page walk level even when the translation fails

We will use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage is not present. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iom

[PATCH 02/10] memory: Add permissions in IOMMUAccessFlags

This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (defined by the PCIe 5 specification)

[PATCH 07/10] intel_iommu: Implement the PCIIOMMUOps callbacks related to invalidations of device-IOTLB

Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index affa7768e6..234c452849 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -473

[PATCH 01/10] pci: Add a memory attribute for pre-translated DMA operations

The address_type bit will be set to PCI_AT_TRANSLATED by devices that use cached addresses obtained via ATS. Signed-off-by: Clement Mathieu--Drif --- include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 + 2 files changed, 12 insertions(+) diff --git a/include/exec/memattrs.h b/

[PATCH 09/10] intel_iommu: Set address mask when a translation fails and adjust W permission

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/inte

[PATCH 03/10] memory: Allow to store the PASID in IOMMUTLBEntry

This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/memory.h b/include/system/memory.h index 1672622d70..d6d069fd50

Options to output the preprocessor code

Hi, Is there an option to generate preprocessor output while building the QEMU code? It makes it easier to understand some of the macro template function generation. -Gautam.

Re: [PATCH 2/2] target/alpha: Add GDB XML feature file

On 6/27/25 13:47, Yodel Eldar wrote: This patch adds the GDB XML feature file that describes Alpha's core registers. Resolves:https://gitlab.com/qemu-project/qemu/-/issues/2569 Signed-off-by: Yodel Eldar --- configs/targets/alpha-linux-user.mak | 1 + configs/targets/alpha-softmmu.mak|

Re: [PATCH] target/riscv: rvv: Fix missing exit TB flow for ldff_trans

On 6/27/25 06:30, Max Chou wrote: According to the V spec, the vector fault-only-first load instructions may change the VL CSR. So the ldff_trans TCG translation function should generate the lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to make sure the vl_eq_vlmax TB flag i

Re: [PATCH v2 0/2] Some trivial live update fixes

On 6/27/25 08:33, Zhenzhong Duan wrote: Hi These are trivial VFIO live update fixes in corner cases. 1) potential SIGSEGV when unmap-all-vaddr failed 2) potential vfio_container_post_load failure Thanks Zhenzhong Changelog: v2: - drop patch1,2 in v1 as they are merged - squashed "local save"