This factor is applied to time spent since we initialized clocks.
It impacts value returned by get_clock(), get_clock_realtime() and
get_cpu_host_ticks();
< 1: time goes slower.
> 1: time goes faster.
1 by default.
Signed-off-by: Pierrick Bouvier
---
include/qemu/timer.h | 60 ++
This option sets a factor on time spent for QEMU clocks since the
beginning of execution. It can be used to slow or accelerate time for a
guest, without impacting QEMU speed.
It can only be used with tcg.
Signed-off-by: Pierrick Bouvier
---
system/rtc.c| 11 +++
system/vl.c | 9
Depending on host cpu speed, and QEMU optimization level, it may sometimes be
needed to slow or accelerate time guest is perceiving. A common scenario is
hitting a timeout during a boot process, because some operations were not
finished on time.
An existing solution for that is -icount shift=X, wi
xjdeng writes:
Hi, thanks for the interest in fixing this. However, the analysis it not
quite right:
> In `find_common_machine_version`, the code previously assumed that
> `getenv(var1)` and `getenv(var2)` would always return non-NULL values.
That's not true. qtest_qemu_binary() has:
if (v
This patch adds TCG plugin register tracking support for the Alpha
target and resolves gitlab issue #2569:
https://gitlab.com/qemu-project/qemu/-/issues/2569
As mentioned in the bug report by Alex Bennée, the register list is
built using the target's corresponding GDB XML feature file, but the
This patch adds the GDB XML feature file that describes Alpha's core
registers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2569
Signed-off-by: Yodel Eldar
---
configs/targets/alpha-linux-user.mak | 1 +
configs/targets/alpha-softmmu.mak| 1 +
gdb-xml/alpha-core.xml
Currently, execlog searches for a space separator between the
instruction mnemonic and operands, but some disassemblers, e.g. Alpha's,
use a tab separator instead; this results in a null pointer being passed
as the haystack in g_strstr during a subsequent register search, i.e.
undefined behavior, b
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> Markus Armbruster writes:
>>
>>> Fabiano Rosas writes:
>>>
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> The migration parameters tls_creds, tls_authz and tls_hostname
>> currently have a non-uniform ha
On 6/27/25 1:02 PM, Pierrick Bouvier wrote:
This test allows to document and exercise device passthrough, using a
nested virtual machine setup. Two disks are generated and passed to the
VM, and their content is compared to original images.
Guest and nested guests commands are executed through tw
This test allows to document and exercise device passthrough, using a
nested virtual machine setup. Two disks are generated and passed to the
VM, and their content is compared to original images.
Guest and nested guests commands are executed through two scripts, and
init used in both system is con
On 6/27/25 11:26 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/27/25 2:17 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/26/25 9:37 AM, Alex Bennée wrote:
Alex Bennée writes:
Rowan Hart writes:
This patch series adds several new API functions focused on enabling use
cas
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
signature.asc
Description: PGP signature
Pierrick Bouvier writes:
> On 6/27/25 2:17 AM, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 6/26/25 9:37 AM, Alex Bennée wrote:
Alex Bennée writes:
> Rowan Hart writes:
>
>> This patch series adds several new API functions focused on enabling use
>> cases
This uses the cached copy of LISTEN_FDNAMES to find the first file
descriptorlabel with a matching label.
Note that if two file descriptors are given the same label this will
ignore all but the first.
This is another step toward addressing
https://gitlab.com/qemu-project/qemu/-/issues/3011
Signe
Enable qemu to be socket-activated based on a spice connection.
Note that this depends on un-deprecating
spice_server_set_listen_socket_fd, see
https://gitlab.freedesktop.org/spice/spice/-/merge_requests/240
This partially addresses
https://gitlab.com/qemu-project/qemu/-/issues/3011
Signed-off-b
By recording a copy of LISTEN_FDNAMES, we make it possible to learn
mappings from file descriptor labels (e.g., as set by
FileDescriptorName= in systemd.socket(5)).
This also makes it possible to invoke check_socket_activation() more
than once and have it return the same value each time.
This is
Hello Corey Minyard,
I hope this email finds you well.
I'm currently adding LAN-configs-retrieval support to the QEMU ipmi-bmc-sim
device. And I hope to merge the modifications upstream after it's finished.
Could you please check the attached patch file of the draft code and share your
opinion
On Fri, Jun 27, 2025, 5:52 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This change removes special parsing for freeform sections and allows
> > them to simply be unmodified rST syntax. The existing headings in the
> > QAPI schema are adjusted to reflect the new paradigm.
>
> "Allows th
On Fri, Jun 27, 2025, 5:52 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This change removes special parsing for freeform sections and allows
> > them to simply be unmodified rST syntax. The existing headings in the
> > QAPI schema are adjusted to reflect the new paradigm.
>
> "Allows th
On Fri, Jun 27, 2025, 5:54 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Oversight in the new qapidoc transmogrifier: @references in freeform
> > documentation blocks were not being transformed to literals. This fixes
> > that, and the next patch ensures that we're testing for this O:-)
On Fri, Jun 27, 2025 at 10:48:59AM +0100, Jonathan Cameron wrote:
> On Thu, 26 Jun 2025 23:41:15 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > Per the spec, FMAPI commands (0x51-0x59) must be bound with
> > MCTP_MT_CXL_FMAPI. Fix the conditions ensuring this in i2c_mctp_cxl.c
On 6/27/25 2:17 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/26/25 9:37 AM, Alex Bennée wrote:
Alex Bennée writes:
Rowan Hart writes:
This patch series adds several new API functions focused on enabling use
cases around reading and writing guest memory from QEMU plugins. To supp
Hi Gustavo,
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> Update blobs for the its=off test on aarch64 after fix.
>
> Basically, all structs related to ITS are gone in MADT and IORT
> tables after the fix (previously ITS was not properly disabled
> when "its=off" option was passed to the machine).
>
On 6/27/25 5:45 PM, Eric Auger wrote:
>
>
> On 6/23/25 3:57 PM, Gustavo Romero wrote:
>> Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct
>> in the MADT table are always generated, even if GIC ITS is not available
>> on the machine.
>>
>> This commit fixes it by not gene
Hi Gustavo,
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct
> in the MADT table are always generated, even if GIC ITS is not available
> on the machine.
>
> This commit fixes it by not generating the ITS Group nodes, not mapping
>
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct
> in the MADT table are always generated, even if GIC ITS is not available
> on the machine.
>
> This commit fixes it by not generating the ITS Group nodes, not mapping
> any other
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> Add blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a
> new variant, .its_off, that requires variations of the MADT and IORT
> tables.
>
> MADT (aka APIC) diff:
>
> +[000h 4]Signature : "APIC"[Multiple AP
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> From: Philippe Mathieu-Daudé
>
> Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
> hardware introduced in GICv3 and, being optional, it can be disabled
> in QEMU aarch64 VMs that support it using machine option "its=off",
> like,
Hi Gustavo,
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> Factor out a new function, create_its_idmaps(), from the current
I would call it build_rc_its_idmap() to be clearer on what relationship
we build.
> build_iort code. Add proper comments to it clarifying how the ID ranges
> that go directly to
On Fri, Jun 13, 2025 at 7:06 PM Roy Hopkins wrote:
>
> Here is v8 of the set of patches to add support for IGVM files to QEMU. This
> is
> based on commit d9ce74873a6a5a7c504379857461e4ae64fcf0cd of qemu.
>
> The previous version of this patch series [1] has only received a few comments
> which a
On 6/27/25 11:12 AM, Matthew Rosato wrote:
AFAICT this portion of the handler including mutex should be moved out of ap.c
into chsc_sei_nt0_get_event(). When vfio_ap is not in use, we can't call into
it. Can't you also build without VFIO_AP? I didn't try it but that sure seems
like it wou
Sure
On 6/27/25 11:12 AM, Matthew Rosato wrote:
AFAICT this portion of the handler including mutex should be moved out of ap.c
into chsc_sei_nt0_get_event(). When vfio_ap is not in use, we can't call into
it. Can't you also build without VFIO_AP? I didn't try it but that sure seems
like it
>>
>> AFAICT this portion of the handler including mutex should be moved out of
>> ap.c into chsc_sei_nt0_get_event(). When vfio_ap is not in use, we can't
>> call into it. Can't you also build without VFIO_AP? I didn't try it but
>> that sure seems like it would cause issues too.
>
> If t
On 27/6/25 15:16, Richard Henderson wrote:
On 6/26/25 09:20, Andrea Bolognani wrote:
On Mon, Jun 09, 2025 at 06:52:21AM -0700, Andrea Bolognani wrote:
On Tue, Apr 15, 2025 at 12:24:04PM -0700, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 2
On 6/27/25 3:57 PM, Eric Auger wrote:
> Hi Gustavo,
>
> On 6/23/25 3:57 PM, Gustavo Romero wrote:
>> When building the Root Complex table, the comment about the code that
> s/table/node? or do you refer to the IORT table?
Reading the IORT spec again, both terminologies are used, ie. node / tabl
Hi Gustavo,
On 6/23/25 3:57 PM, Gustavo Romero wrote:
> When building the Root Complex table, the comment about the code that
s/table/node? or do you refer to the IORT table?
> maps the RC node to SMMU node is misleading because it reads
> "RC -> SMMUv3 -> ITS", but the code is only mapping the RC
This patchset is based on the v1 provided by Anoton Blanchard with
following update:
* Add the missing input EEWs checking rule for widen vector reduction
instruction.
Reference:
* v1: 20250415043207.3512209-1-ant...@tenstorrent.com
Anton Blanchard (3):
target/riscv: rvv: Apply vext_check_in
According to the V spec, the vector fault-only-first load instructions
may change the VL CSR.
So the ldff_trans TCG translation function should generate the
lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
make sure the vl_eq_vlmax TB flag is correct.
Signed-off-by: Max Chou
According to the RISC-V instruction set manual, the minimum VLEN needs
to respect the following extensions:
Extension Minimum VLEN
* V 128
* Zve64[d|f|x] 64
* Zve32[f|x] 32
Signed-off-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 13 +++--
1 file changed, 11 inse
From: Anton Blanchard
We were marking vadc and vsbc as vm=1 instructions, which meant
vext_check_input_eew wouldn't detect mask vs source register
overlaps.
Signed-off-by: Anton Blanchard
Reviewed-by: Max Chou
Signed-off-by: Max Chou
---
target/riscv/insn32.decode | 10 +-
1 file cha
From: Anton Blanchard
Handle the overlap of source registers with different EEWs.
Signed-off-by: Anton Blanchard
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
From: Anton Blanchard
Handle the overlap of source registers with different EEWs.
Signed-off-by: Anton Blanchard
Reviewed-by: Max Chou
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --gi
On 6/26/25 12:19 PM, Matthew Rosato wrote:
On 6/9/25 12:44 PM, Rorie Reyes wrote:
Handle interception of the CHSC SEI instruction for requests
indicating the guest's AP configuration has changed.
If configuring --without-default-devices, hw/s390x/ap-stub.c
was created to handle such circumst
On 6/26/25 09:20, Andrea Bolognani wrote:
On Mon, Jun 09, 2025 at 06:52:21AM -0700, Andrea Bolognani wrote:
On Tue, Apr 15, 2025 at 12:24:04PM -0700, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 20 +
tcg/aarch64/tcg-target.c.inc
In `find_common_machine_version`, the code previously assumed that
`getenv(var1)` and `getenv(var2)` would always return non-NULL values.
However, if either environment variable is not set, `getenv` returns
NULL, which could lead to a null pointer dereference.
Tracing upstream usage: `find_common_
On 6/27/2025 2:33 AM, Zhenzhong Duan wrote:
When there are multiple VFIO containers, vioc->dma_map is restored
multiple times, this made only first container work and remaining
containers using vioc->dma_map restored by first container.
Fix it by save and restore vioc->dma_map locally. saved_dma
On 6/27/2025 2:33 AM, Zhenzhong Duan wrote:
CPR overrides then restores dma_map in both outgoing and incoming QEMU, for
different reasons. But it only sets saved_dma_map in the target.
Fix it by always setting saved_dma_map.
Fixes: eba1f657cbb1 ("vfio/container: recover from unmap-all-vaddr fai
Hi Peter,
Thanks for the comments.
Updated in v2.
Note: I have included a null check in the fail statement of
migration coroutine as well.
This is so that there are no dereferencing
issue in case local_err is not set in any of the paths.
(error_report_err call dereferences the err->msg)
On Wed,
- This is an incremental step in converting vmstate loading
code to report errors.
- Minimal changes to the signature and body of the following
functions are done,
- vmstate_load()
- vmstate_load_state()
- vmstate_subsection_load()
- qemu_load_device_state()
- qemu_loadvm_state()
-
- Introduce a new post_load_with_error() hook that will
take in the Error object as a parameter.
- This error object is set if the loading of state fails.
- The error can then be retrieved using QMP command
{"execute" : "query-migrate"}
Buglink: https://issues.redhat.com/browse/RHEL-82826
Rev
Currently, when a migration of a VM with an encrypted vTPM
fails on the destination host (e.g., due to a mismatch in secret values),
the error message displayed on the source host is generic and unhelpful.
For example, a typical error looks like this:
"operation failed: job 'migration out' failed:
Hi Shameer,
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> Hi All,
>
> Changes from v4:
> https://lore.kernel.org/qemu-devel/2025061319.60156-1-shameerali.kolothum.th...@huawei.com/
>
> Major changes from v4:
this will need a respin after merge of
f5ec751ee70d hw/arm/virt: Check bypass iommu
Hi Shameer,
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> For the legacy smmuv3 test case, IORT has a single SMMUV3 node and
> a Root Complex node with three ID mappings of which two points to
> the SMMUv3 node and the remaining one points to ITS.
You don't describe DSDT at all below, just IORT.
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
> one of which has bypass_iommu enabled. The generated IORT table contains
> a single SMMUv3 node and a Root Complex node with three ID mappings. Two
> of these ID mappings ha
John Snow writes:
> This patch changes the qapidoc parser to generate stub Return value
> documentation for any command that has a return value but does not have
> a "Returns:" doc section.
>
> The stubs include just the type name, which will be rendered with a
> cross-reference link in the HTML
Hi Shameer,
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> The tests to be added exercises both legacy(iommu=smmuv3) and new
Suggesting: exercice. legacy (
Besides:
Reviewed-by: Eric Auger
Eric
> -device arm-smmuv3,.. cases.
>
> Signed-off-by: Shameer Kolothum
> ---
> tests/data/acpi/aarch64
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> Allow cold-plugging of an SMMUv3 device on the virt machine when no
> global (legacy) SMMUv3 is present or when a virtio-iommu is specified.
>
> This user-created SMMUv3 device is tied to a specific PCI bus provided
> by the user, so ensure the IOMM
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> Now that arm,virt can have user-creatable smmuv3 devices, document it.
>
> Signed-off-by: Shameer Kolothum
Reviewed-by: Eric Auger
Eric
> ---
> qemu-options.hx | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/qemu-options.hx b/qem
Hi Shameer,
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus.
> However, when retrieving IOMMU ops for a device using
> pci_device_get_iommu_bus_devfn(), the function checks the parent_dev
> and fetches IOMMU ops from the parent dev
On Tue, 24 Jun 2025 12:45:27 +0200
Igor Mammedov wrote:
> On Tue, 24 Jun 2025 09:07:11 +0200
> Gerd Hoffmann wrote:
>
> > Hi,
> >
> > > Gerd mentioned this in the relevant bz:
> > >
> > > Note: root cause for the initrd issue noted in comment 5 is
> > > seabios
> > > runn
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> Introduce a new struct AcpiIortSMMUv3Dev to hold all the information
> required for SMMUv3 IORT node and use that for populating the node.
>
> The current machine wide SMMUv3 is named as legacy SMMUv3 as we will
> soon add support for user-creatable
Hi Shameer,
On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra
> root complexes to be associated with SMMU.
>
> Although this change does not affect functionality at present, it is
> required when we add support for user-creatable
From: Yiwei Zhang
Venus and later native contexts have their own fence context along with
multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in
the flags must be dispatched to be created on the target context. Fence
signaling also has to be handled on the specific timeline withi
On 6/27/25 12:16, Tan Siewert wrote:
On 20.06.25 03:23, Jamin Lin wrote:
Subject: Re: [PATCH v4] hw/misc/aspeed_scu: Handle AST2600 protection key
registers correctly
Jamin,
On 6/19/25 10:53, Tan Siewert wrote:
The AST2600 SCU has two protection key registers (0x00 and 0x10) that
both need
On Thu, 5 Jun 2025 10:24:34 +0100
Daniel P. Berrangé wrote:
> On Tue, Jun 03, 2025 at 05:02:38PM +0200, Igor Mammedov wrote:
> > On Wed, 28 May 2025 13:23:49 +0800
> > Zhao Liu wrote:
> >
> > > On Wed, May 28, 2025 at 10:09:56AM +0800, Xiaoyao Li wrote:
> > > > Date: Wed, 28 May 2025 10:09:
On Fri, Jun 13, 2025 at 8:52 PM Roy Hopkins wrote:
>
> The initialization sections in IGVM files contain configuration that
> should be applied to the guest platform before it is started. This
> includes guest policy and other information that can affect the security
> level and the startup measur
From: Rowan Hart
This patch adds functions to the plugins API to allow reading and
writing memory via virtual addresses. These functions only permit doing
so on the current CPU, because there is no way to ensure consistency if
plugins are allowed to read or write to other CPUs that aren't current
From: Rowan Hart
The x86_64-softmmu Makefile seems to have been copy-pasted from the i386
Makefile at some point in the past. Cleaning up a vestigial unused
variable and removing some outdated comments.
Signed-off-by: Rowan Hart
Message-ID: <20250624175351.440780-7-rowanbh...@gmail.com>
Signed-
From: Rowan Hart
This patch adds a plugin that exercises the virtual and hardware memory
read-write API functions added in a previous patch. The plugin takes a
target and patch byte sequence, and will overwrite any instruction
matching the target byte sequence with the patch.
Reviewed-by: Pierri
Seeing as I've taken a few patches to here now I might as well put
myself forward to maintain virtio-gpu. I've marked it as Odd Fixes as
it is not my core focus. If someone with more GPU experience comes
forward we can always update again.
Reviewed-by: Markus Armbruster
Signed-off-by: Alex Bennée
From: Rowan Hart
This patch exposes the gdb_write_register function from
gdbstub/gdbstub.c via the exec/gdbstub.h header file to support use in
plugins to write register contents.
Reviewed-by: Alex Bennée
Reviewed-by: Julian Ganz
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rowan Hart
Messag
From: Rowan Hart
This patch adds functionality to enforce the requested QEMU_PLUGIN_CB_
flags level passed when registering a callback function using the
plugins API. Each time a callback is about to be invoked, a thread-local
variable will be updated with the level that callback requested. Then,
From: Rowan Hart
This patch adds functions to the plugins API to allow plugins to read
and write memory via hardware addresses. The functions use the current
address space of the current CPU in order to avoid exposing address
space information to users. A later patch may want to add a function to
From: Gustavo Romero
Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and
hot-unplug on arm64.
Signed-off-by: Gustavo Romero
Reviewed-by: Daniel P. Berrangé
Acked-by: Thomas Huth
Message-ID: <20250528203137.1654964-1-gustavo.rom...@linaro.org>
[AJB: trimmed boilerplate to k
From: Philippe Mathieu-Daudé
Replace target_ulong by vaddr or size_t types to match
cpu_memory_rw_debug() prototype in "exec/cpu-common.h":
> int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
> void *ptr, size_t len,
> bool is_write);
Signe
From: Rowan Hart
This patch updates the plugin version to gate new APIs and adds notes
describing what has been added.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rowan Hart
Message-ID: <20250624175351.440780-9-rowanbh...@gmail.com>
Signed-off-by: Alex Bennée
---
include/qemu/qemu-plugin.h
From: Rowan Hart
This patch adds a function to the plugins API to allow plugins to write
register contents. It also moves the qemu_plugin_read_register function
so all the register-related functions are grouped together in the file.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rowan Hart
Messa
Thanks for volunteering to help.
Cc: Akihiko Odaki
Cc: Dmitry Osipenko
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Michael S. Tsirkin
Signed-off-by: Alex Bennée
Message-ID: <20250603110204.838117-9-alex.ben...@linaro.org>
---
MAINTAINERS | 2 ++
1 file chang
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-ID: <20250526095213.14113-3-phi...@linaro.org>
Signed-off-by: Alex Bennée
---
semihosting/meson.build | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/semihosting/m
The system tests (usually qos-test or migration-test) prove to be very
susceptible on the s390x runners. Although we have boosted memory and
virtual CPUs on the runners problems persist. For now mark test as
allow_failure so the its clear on the CI UI when checking test
results.
Signed-off-by: Ale
Hi,
Here is the rolled up set of patches from my various maintainer trees.
>From testing/next:
- new pci hotplug tests
>From semihosting/next
- compile once updates
>From plugins/next
- register write support for plugins
- memory read/write support (see caveats in APIs)
I've also be
On 20.06.25 03:23, Jamin Lin wrote:
Subject: Re: [PATCH v4] hw/misc/aspeed_scu: Handle AST2600 protection key
registers correctly
Jamin,
On 6/19/25 10:53, Tan Siewert wrote:
The AST2600 SCU has two protection key registers (0x00 and 0x10) that
both need to be unlocked. (Un-)locking 0x00 modi
This series enables ACPI PCI hotplug/hotunplug on ARM.
It is not enabled by default and ACPI PCI hotplug can
be selected by setting:
-global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
Expected benefits should be similar to those listed in [1],
ie. removal of some racy behaviors, improved la
On Fri, Jun 13, 2025 at 7:24 PM Roy Hopkins wrote:
>
> Adds an IGVM loader to QEMU which processes a given IGVM file and
> applies the directives within the file to the current guest
> configuration.
>
> The IGVM loader can be used to configure both confidential and
> non-confidential guests. For
No need to export aml_pci_device_dsm() as it is only used
in hw/i386/acpi-build.c.
Signed-off-by: Eric Auger
Reviewed-by: Gustavo Romero
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
include/hw/acpi/pci.h | 1 -
hw/i386/acpi-build.c | 2 +-
We intend to reuse build_append_pci_bus_devices and build_append_pcihp_slots
on ARM. So let's move them to hw/acpi/pcihp.c as well as all static
helpers they use.
No functional change intended.
Signed-off-by: Eric Auger
Reviewed-by: Gustavo Romero
Reviewed-by: Igor Mammedov
Reviewed-by: Jonath
hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index
Add the requested ACPI bits requested to support static acpi-index
for non hotplug ports.
Signed-off-by: Eric Auger
---
hw/arm/virt-acpi-build.c | 12
hw/arm/Kconfig | 2 ++
2 files changed, 14 inser
From: Gustavo Romero
This commit adds DSDT blobs to the whilelist in the prospect to
allow changes in the arm virt DSDT method.
Signed-off-by: Gustavo Romero
Signed-off-by: Eric Auger
---
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
1 file changed, 5 insertions(+)
diff --git a
Some sysbus devices have conditional mmio regions. This
happens for instance with the hw/acpi/ged device. In that case
it becomes difficult to predict which index a specific MMIO
region corresponds to when one needs to mmio map the region.
Introduce a new helper that takes the name of the region in
Move aml_pci_edsm to pci-bridge.c since we want to reuse that for
ARM and acpi-index support. Also rename it into build_pci_bridge_edsm.
Signed-off-by: Eric Auger
---
v3->v4:
- renamed into build_pci_bridge_edsm() (Jonathan, Igor)
v2 -> v3:
- move to pci-bridge.c instead of pcihp.c (Igor)
---
From: Gustavo Romero
This commit adds DSDT blobs to the whilelist in the prospect to
allow changes in the GPEX _OSC method.
Signed-off-by: Gustavo Romero
Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
Acked-by: Igor Mammedov
---
v3 -> v4:
- add missed tests/data/acpi/riscv64/virt/D
Add a subsection to migrate the AcpiPciHpState state.
Signed-off-by: Eric Auger
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index fc84bfb34
Modify the DSDT ACPI table to enable ACPI PCI hotplug.
Signed-off-by: Eric Auger
---
v3 -> v4:
- use property accessor
- removed ACPI_PCIHP_SIZE which is already in the header
- make addition of EDSM unconditional
v2 -> v3:
- use ACPI_PCIHP_SIZE instead of 0x1000 (Igor)
- use cihp_state->use_ac
Let pass the root bus to ich9 and piix4 through a property link
instead of through an argument passed to acpi_pcihp_init().
Also make sure the root bus is set at the entry of acpi_pcihp_init().
The rationale of that change is to be consistent with the forecoming ARM
implementation where the machi
Hi,
On 6/27/25 11:55 AM, Eric Auger wrote:
> Changes relate to the introduction of pieces related to
> acpi-index static support along with root ports with no hotplug.
>
> +
> +Scope (\_SB.PCI0)
> +{
> +Method (EDSM, 5, Serialized)
> +{
> +If ((Arg2 == Zero))
>
On Thu, 26 Jun 2025 23:41:15 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> Per the spec, FMAPI commands (0x51-0x59) must be bound with
> MCTP_MT_CXL_FMAPI. Fix the conditions ensuring this in i2c_mctp_cxl.c
> and dev-mctp.c
>
> Move the opcode enum from cxl-mailbox-utils.c to cxl_mail
From: Gustavo Romero
Add 2 new tests:
- test_acpi_aarch64_virt_acpi_pci_hotplug tests the acpi pci hotplug
using -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
- test_acpi_aarch64_virt_pcie_root_port_hpoff tests static-acpi index
on a root port with disabled hotplug
Signed-off-by:
acpi_dsdt_add_pci_osc() name is confusing as it gives the impression
it appends the _OSC method but in fact it also appends the _DSM method
for the host bridge. Let's split the function into two separate ones
and let them return the method Aml pointer instead. This matches the
way it is done on x86
HACK: waiting for the resolution of previous issue to put the
disassembled data here.
Signed-off-by: Eric Auger
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6294 bytes
tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
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