On 6/27/25 04:56, Kane Chen wrote:
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for s
On 6/27/25 04:56, Kane Chen wrote:
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP command
CPR overrides then restores dma_map in both outgoing and incoming QEMU, for
different reasons. But it only sets saved_dma_map in the target.
Fix it by always setting saved_dma_map.
Fixes: eba1f657cbb1 ("vfio/container: recover from unmap-all-vaddr failure")
Suggested-by: Steven Sistare
Signed-of
Hi
These are trivial VFIO live update fixes in corner cases.
1) potential SIGSEGV when unmap-all-vaddr failed
2) potential vfio_container_post_load failure
Thanks
Zhenzhong
Changelog:
v2:
- drop patch1,2 in v1 as they are merged
- squashed "local save" parts of patch3 into patch4 (Steve)
- s/DM
When there are multiple VFIO containers, vioc->dma_map is restored
multiple times, this made only first container work and remaining
containers using vioc->dma_map restored by first container.
Fix it by save and restore vioc->dma_map locally. saved_dma_map in
VFIOContainerCPR becomes useless and i
Hi Eric,
On 6/26/25 4:01 PM, Eric Auger wrote:
On 6/26/25 4:05 AM, Shaoqin Huang wrote:
Hi Eric,
On 6/23/25 5:20 PM, Eric Auger wrote:
On 6/17/25 5:05 AM, Shaoqin Huang wrote:
Set the "use-legacy-x86-rom" property to false by default, and only set
it to true on x86 since only x86 will ne
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 6 --
target/loongarch/cpu.c | 10 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-c
ntroduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is
Hi,
Since the previsor unified cache model series has already introduced a
new compat property "x-vendor-cpuid-only-v2", it's a chance to once
again consolidate more vendor-specific CPUIDs.
I also checked the CPUID leaves currently supported by Intel & AMD and
found that since the previous "x-ven
Sort the CPUID leaves strictly by index to facilitate checking and
changing.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 60 +++
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d5a227d4c8
Per SDM,
8007H EAX Reserved = 0.
EBX Reserved = 0.
ECX Reserved = 0.
EDX Bits 07-00: Reserved = 0.
Bit 08: Invariant TSC available if 1.
Bits 31-09: Reserved = 0.
EAX/EBX/ECX in CPUID 0x8007 leaf are reserved for Intel.
At present
Per SDM,
8000H EAX Maximum Input Value for Extended Function CPUID Information.
EBX Reserved.
ECX Reserved.
EDX Reserved.
EBX/ECX/EDX in CPUID 0x8000 leaf are reserved. Intel is using 0x0
leaf to encode vendor.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c
Per SDM,
8008H EAX Linear/Physical Address size.
Bits 07-00: #Physical Address Bits*.
Bits 15-08: #Linear Address Bits.
Bits 31-16: Reserved = 0.
EBX Bits 08-00: Reserved = 0.
Bit 09: WBNOINVD is available if 1.
Bi
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 44 ++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index c686ac9483..5959d
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.c | 7 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 25 +++--
4 files changed, 43 insertions(+), 2 del
implement the read-clear feature for CSR_MSGIR register.
Signed-off-by: Song Gao
---
target/loongarch/csr.c| 5 +
target/loongarch/tcg/csr_helper.c | 21 +++
target/loongarch/tcg/helper.h | 1 +
.../tcg/insn_trans/trans_pr
move som machine define to virt.h and define avec feature and status bit.
Use the IOCSRF_AVEC bit for avdance interrupt controller drivers
avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit
IOCSRM_AVEC_EN.
and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN.
[1]:h
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1 +
incl
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 24
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1 +
i
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 21 +
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 32 insertions(+), 3 deletions(-)
LoongArchVirtMachinState adds avecintc features, and
it use to check whether virt machine support advance interrupt controller
and default set avecintc = ON_OFF_AUTO_ON.
LoongArchVirtMachineState adds misc_feature and misc_status for
misc fetures and status. and set default avec feture bit.
Signed
In `find_common_machine_version`, the code previously assumed that
`getenv(var1)` and `getenv(var2)` would always return non-NULL values.
However, if either environment variable is not set, `getenv` returns
NULL, which could lead to a null pointer dereference.
Tracing upstream usage: `find_common_
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
> After applying these patches to QEMU mainline at commit 6e1571533fd9:
Ah, I forgot I've rebased these patches...Now you can rebase all the
patches at the latest master branch.
Or, you can try this repo - I just created it to make it easier for you:
https://gitlab.com/zhao.liu/qemu/-/tree/cache
> > +/* Encode cache info for CPUID[4] */
>
> Maybe this should be /* Encode cache info for CPUID[2] */ ?
> I'm not sure.
Yep, you're right! The following function is used to encode CPUID[2]
as its name indicates.
> > +static void encode_cache_cpuid2(X86CPU *cpu,
> > +
On 6/4/25 9:28 AM, Hanna Czenczek wrote:
FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
(via open("/dev/fuse") + ioctl(FUSE_DEV_IOC_CLONE)).
We can use this to implement multi-threading.
For configuration, we don't need any more information beyond the simple
array pr
On 6/26/25 4:31 PM, Zhao Liu wrote:
From: Manish Mishra
Add a "x-force-cpuid-0x1f" property so that CPU models can enable it and
have 0x1f CPUID leaf natually as the Host CPU.
The advantage is that when the CPU model's cache model is already
consistent with the Host CPU, for example, SRF
On 6/20/25 5:27 PM, Zhao Liu wrote:
Modern Intel CPUs use CPUID 0x4 leaf to describe cache information
and leave space in 0x2 for prefetch and TLBs (even TLB has its own leaf
CPUID 0x18).
And 0x2 leaf provides a descriptor 0xFF to instruct software to check
cache information in 0x4 leaf ins
Hi,
This patch adds support for emulation of CRC32 instructions for
the Mips target in QEMU, adds tests, and enables CRC for mips64r6.
The CRC32 instructions are available in MD00087 Revision 6.06.
The disassembly for crc32 is hidden in commit 99029be1c28.
New opcode is implemented in decodetree f
From: Aleksandar Rakic
Aleksandar Rakic (1):
Add support for emulation of CRC32 instructions
target/mips/cpu-defs.c.inc| 10 +-
target/mips/helper.h | 2 +
target/mips/meson.build | 1 +
target/mips/tcg/op_helper.c
From: Aleksandar Rakic
Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().
Enable CRC for mips64r6.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Aleksandar Rakic
Reviewed-by: Aleksandar Rikalo
---
targe
From: Anisa Su
Per the spec, FMAPI commands (0x51-0x59) must be bound with
MCTP_MT_CXL_FMAPI. Fix the conditions ensuring this in i2c_mctp_cxl.c
and dev-mctp.c
Move the opcode enum from cxl-mailbox-utils.c to cxl_mailbox.h to
allow i2c_mctp_cxl.c and dev-mctp.c to use the enum instead of
hardcod
From: Anisa Su
The FMAPI DCD Management patchset
(https://lore.kernel.org/linux-cxl/20250626222743.1766404-1-anisa.su...@gmail.com/T/#t)
is based on upstream, which does not include the i2c MCTP hack or the new MCTP
USB support carried in Jonathan's tree.
The commands are accessible upstream th
From: Anisa Su
Add a lock on the bitmap of each CXLDCRegion in preparation for the next
patch which implements FMAPI Set DC Region Configuration. This command
can modify the block size, which means the region's bitmap must be updated
accordingly.
The lock becomes necessary when commands that add
From: Anisa Su
FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4
Very similar to previously implemented command 0x4801.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
---
hw/cxl/cxl-mailbox-utils.c | 76 ++
1 file changed, 76 ins
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
---
hw/cxl/cxl-mailbox-utils.c | 86
hw/mem/cxl_type3.c | 6 +--
include/hw/cxl/cxl_device.h | 3 ++
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Signed-off-by: Anisa Su
---
hw/cxl/cxl-mailbox-utils.c | 79 ++
1 file changed, 79 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-uti
From: Anisa Su
FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section 7.6.7.6.1.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
---
hw/cxl/cxl-mailbox-utils.c | 59 +
hw/mem/cxl_type3.c | 4 +++
include/hw/cxl/cxl_device.h | 1 +
3 f
From: Anisa Su
Move definition/enum to cxl_events.h for shared use in next patch
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
---
hw/mem/cxl_type3.c | 15 ---
include/hw/cxl/cxl_events.h | 15 +++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a
From: Anisa Su
Prepatory patch for following FMAPI Add/Release Patches. Refactors part
of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
function to create DC Event Records and insert in the event log.
Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
accessed b
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Signed-off-by: Anisa Su
---
hw/cxl/cxl-mailbox-utils.c | 106
hw/mem/cxl_type3.c | 8 +--
include/hw/cxl/cxl_device.h | 4 ++
3 files changed, 114
From: Anisa Su
This patchset adds support for 6 FM API DCD Management commands (0x5600-0x5605)
according to the CXL r3.2 Spec.
The code was tested with libcxlmi, which runs in the QEMU VM and sends 56xxh
commands to the device (QEMU-emulated) through MCTP messages over USB.
Test Configuration:
From: Anisa Su
Add booleans to DC Region struct to represent dsmas flags (defined in CDAT) in
preparation for the next command, which returns the flags in the next mailbox
command 0x5601.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
---
hw/mem/cxl_type3.c | 8 +++-
include/hw/cxl
From: Anisa Su
FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
---
hw/cxl/cxl-mailbox-utils.c | 103 +
1 file changed, 103 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/
The new qapidoc.py can generate "Returns" statements with type
information just fine, so we can remove it from the source where it
doesn't add anything particularly novel or helpful and just repeats the
type info.
This patch is fairly "gentle" and doesn't aggressively touch other
"Returns" lines t
This form is used to annotate a return type without an accompanying
description, for when there is no "Returns:" information in the source
doc, but we have a return type we want to generate a cross-reference to.
The syntax is:
:return-nodesc: TypeName
It's primarily necessary because Sphinx alwa
Well, I tried. Maybe not very hard. Sorry!
Signed-off-by: John Snow
---
qapi/block-core.json | 6 +++---
qapi/block-export.json | 2 +-
qapi/block.json| 2 +-
qapi/control.json | 5 ++---
qapi/dump.json | 5 ++---
qapi/introspect.json | 6 +++---
qapi/job.json |
So tired to parse all these timestamps, when need to compare them
with other logs.
Use iso8601 format as in warn_report() (info_report(), error_report())
already used.
Also, start line with date, to be similar with warn_report() as well.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
scripts/
This patch changes the qapidoc parser to generate stub Return value
documentation for any command that has a return value but does not have
a "Returns:" doc section.
The stubs include just the type name, which will be rendered with a
cross-reference link in the HTML output.
Signed-off-by: John Sn
This series adds the ability for the new QAPIDoc system to generate
"Returns:" documentation based on the return type declared in the Schema
even when no explicit documentation is found in the QAPI source. As a
result and as an immediate cleanup, trivial return statements are
removed and remaining
Sparc QEMU segfaults directly if a TCG plugin is used but no logging is
specified via `-d plugin`.
If logging is enabled it segfaults also. But a little later.
I tested it also with PPC32 and Hexagon. They seem to work fine.
Host: Fedora 41 - Linux 6.12.25-1.qubes.fc37.x86_64
Anyone had this p
>
>
> > This patch does not apply to qemu.git/master. When posting new revisions
> > of patches, please resend the entire patch series that this belongs to
> > or send it as a separate patch with the Based-on: trailer
> > to let people (and tools) know which unmerged patch series it depends
> > on
On Wed, Jun 25, 2025 at 12:30:23PM +, Tanish Desai wrote:
> Adds generate_conditional, allowing backends to wrap generate()
> output in a trace_event_get_state(...) check if needed.
>
> Removes no_check by inlining its logic into trace_foo(...).
> Also ensures the generated code is formatted p
On Tue, 17 Jun 2025 08:56:41 +0800
Tomita Moeko wrote:
> On 2025/5/29 18:41, Tomita Moeko wrote:
> > On 2025/5/29 2:30, Alex Williamson wrote:
> >> On Wed, 28 May 2025 23:55:48 +0800
> >> Tomita Moeko wrote:
> >>
> >>> Introduce x-pci-class-code option to allow users to override PCI class
>
On 6/26/25 9:37 AM, Alex Bennée wrote:
Alex Bennée writes:
Rowan Hart writes:
This patch series adds several new API functions focused on enabling use
cases around reading and writing guest memory from QEMU plugins. To support
these new APIs, some utility functionality around retrieving inf
Hi Michael,
On 6/17/2025 8:34 PM, Alejandro Jimenez wrote:
> Added two new changes based on observations from Ethan. Like the rest of
> the fixes in this series, these do not trigger problems today given the
> limited feature set supported. Re-tested the series with emulated devices,
> VFIO passt
On 6/17/2025 8:34 PM, Alejandro Jimenez wrote:
> The definitions encoding the maximum Virtual, Physical, and Guest Virtual
> Address sizes supported by the IOMMU are using incorrect offsets i.e. the
> VASize and GVASize offsets are switched. The value in the GVAsize field is
> also modified, sin
On Wed, Jun 25, 2025 at 03:22:34PM +0100, Alireza Sanaee wrote:
> On Thu, 23 May 2024 10:44:40 -0700
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > A git tree of this series can be found here (with one extra commit on
> > top for printing out accepted/pending extent list for testing):
Alex Bennée writes:
> Rowan Hart writes:
>
>> This patch series adds several new API functions focused on enabling use
>> cases around reading and writing guest memory from QEMU plugins. To support
>> these new APIs, some utility functionality around retrieving information
>> about
>> address s
On Mon, Jun 09, 2025 at 06:52:21AM -0700, Andrea Bolognani wrote:
> On Tue, Apr 15, 2025 at 12:24:04PM -0700, Richard Henderson wrote:
> > Signed-off-by: Richard Henderson
> > ---
> > tcg/tcg.c| 20 +
> > tcg/aarch64/tcg-target.c.inc | 28 +++-
> > tcg/
On 6/9/25 12:44 PM, Rorie Reyes wrote:
> Handle interception of the CHSC SEI instruction for requests
> indicating the guest's AP configuration has changed.
>
> If configuring --without-default-devices, hw/s390x/ap-stub.c
> was created to handle such circumstance. Also added the
> following to hw/
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> Markus Armbruster writes:
>>
>>> Fabiano Rosas writes:
>>>
The migration parameters tls_creds, tls_authz and tls_hostname
currently have a non-uniform handling. When used as arguments to
migrate-set-parameters, their type is
On Thu, Jun 26, 2025 at 10:52:32AM +0200, Juraj Marcin wrote:
> From: Juraj Marcin
>
> Recent patch [1] renames the save_live_complete_precopy handler to
> save_complete, as the machine is not live in most cases when this
> handler is executed. The same is true also for
> save_live_complete_preco
On 6/23/2025 6:22 AM, Zhenzhong Duan wrote:
When there are multiple VFIO containers, vioc->dma_map is restored
multiple times, this made only first container work and remaining
containers using vioc->dma_map restored by first container.
Fix it by save and restore vioc->dma_map locally. saved_dma
On 6/26/2025 8:53 AM, Steven Sistare wrote:
On 6/24/2025 12:54 PM, Cédric Le Goater wrote:
On 6/23/25 12:22, Zhenzhong Duan wrote:
cpr.saved_dma_map isn't initialized in source qemu which lead to vioc->dma_map
assigned a NULL value, this will trigger SIGSEGV.
I don't understand the scenario.
On 6/17/2025 8:34 PM, Alejandro Jimenez wrote:
> From: Ethan Milon
>
> The variable `oldval` was incorrectly declared as a 32-bit `uint32_t`.
> This could lead to truncation and incorrect behavior where the upper
> read-only 32 bits are significant.
>
> Fix the type of `oldval` to match the r
On 6/24/2025 12:54 PM, Cédric Le Goater wrote:
On 6/23/25 12:22, Zhenzhong Duan wrote:
cpr.saved_dma_map isn't initialized in source qemu which lead to vioc->dma_map
assigned a NULL value, this will trigger SIGSEGV.
I don't understand the scenario. Could you please explain more ?
Thank you Z
This patch enables and advertises asym capabilties
for backend user application.
Signed-off-by: Rajesh Mudimadugula
---
backends/cryptodev-vhost-user.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-user.c
index cb04e68b02..f9dec
Jonah Palmer writes:
> On 6/2/25 4:29 AM, Markus Armbruster wrote:
>> Butterfingers... let's try this again.
>>
>> Markus Armbruster writes:
>>
>>> Si-Wei Liu writes:
>>>
On 5/26/2025 2:16 AM, Markus Armbruster wrote:
> Si-Wei Liu writes:
>
>> On 5/15/2025 11:40 PM, Markus Armbr
"Michael S. Tsirkin" writes:
> On Wed, Jun 25, 2025 at 08:46:54PM +0100, Daniel P. Berrangé wrote:
>> On Wed, Jun 25, 2025 at 03:16:52PM -0400, Michael S. Tsirkin wrote:
>> > On Mon, Jun 16, 2025 at 11:22:41AM +0200, Markus Armbruster wrote:
>> > > From: Daniel P. Berrangé
>> > >
>> > > There h
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 17/19] intel_iommu: Refresh pasid bind when either
>SRTP or TE bit is changed
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> From: Yi Liu
>>
>> When either 'Set Root Table Pointer' or 'Translation En
On 6/20/25 3:22 PM, Igor Mammedov wrote:
> On Fri, 20 Jun 2025 11:40:29 +0100
> Jonathan Cameron wrote:
>
>> On Mon, 16 Jun 2025 11:46:57 +0200
>> Eric Auger wrote:
>>
>>> From: Gustavo Romero
>>>
>>> The test uses -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>>> to force the usag
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 16/19] intel_iommu: Propagate PASID-based iotlb
>invalidation to host
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> From: Yi Liu
>>
>> This traps the guest PASID-based iotlb invalidation request and
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Now that the TLS options have been made the same between
>>> migrate-set-parameters and query-migrate-parameters, a single type can
>>> be used. Remove MigrateSetParameters.
>>>
>>> The TLS options documentation
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> The migration parameters tls_creds, tls_authz and tls_hostname
>>> currently have a non-uniform handling. When used as arguments to
>>> migrate-set-parameters, their type is StrOrNull and when used as
>>> return
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 15/19] intel_iommu: Replay pasid binds after context
>cache invalidation
>
>
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> From: Yi Liu
>>
>> This replays guest pasid attachments after context cache invalidation.
>> This is
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 14/19] intel_iommu: Bind/unbind guest page table to
>host
>
>
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> This captures the guest PASID table entry modifications and
>> propagates the changes to host to attach a hwpt with
From: Juraj Marcin
Recent patch [1] renames the save_live_complete_precopy handler to
save_complete, as the machine is not live in most cases when this
handler is executed. The same is true also for
save_live_complete_precopy_thread, therefore this patch removes the
"live" keyword from the handle
Hi Cédric,
Thanks for your feedback. I will move the OTP implementation to `hw/nvram/` as
suggested, and adjust the related code accordingly.
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, June 26, 2025 4:23 PM
> To: Kane Chen ; Peter Maydell
> ; Ste
Hi Igor,
On 6/25/25 5:23 PM, Eric Auger wrote:
> Hi Igor, Jonathan,
>
> On 6/20/25 6:13 PM, Jonathan Cameron wrote:
>> On Fri, 20 Jun 2025 14:38:22 +0200
>> Igor Mammedov wrote:
>>
>>> On Fri, 20 Jun 2025 10:35:38 +0100
>>> Jonathan Cameron wrote:
>>>
On Mon, 16 Jun 2025 11:46:46 +0200
>>>
On Thu, Jun 26, 2025 at 09:18:22AM +0100, Daniel P. Berrangé wrote:
> On Wed, Jun 25, 2025 at 04:49:17PM -0400, Michael S. Tsirkin wrote:
> > On Wed, Jun 25, 2025 at 04:47:06PM -0400, Stefan Hajnoczi wrote:
> > > On Wed, Jun 25, 2025 at 4:39 PM Kevin Wolf wrote:
> > > >
> > > > Am 25.06.2025 um 21
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 13/19] intel_iommu: Stick to system MR for
>IOMMUFD backed host device when x-fls=on
>
>
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> When guest in scalable mode and x-flts=on, we stick to system MR for
>IOMMUFD
>when guest
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 12/19] intel_iommu: Introduce a new pasid cache
>invalidation type FORCE_RESET
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> FORCE_RESET is different from GLOBAL_INV which updates pasid cache if
>> u
On 2025-06-24 12:25, Thomas Huth wrote:
On 16/06/2025 16.01, Shalini Chellathurai Saroja wrote:
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU.
Changed since v5:
- Add identifiers as class properties instead of object properties
- Add
On 6/26/25 09:57, Kane Chen wrote:
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP command
On 6/26/25 09:57, Kane Chen wrote:
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provid
On Wed, Jun 25, 2025 at 04:49:17PM -0400, Michael S. Tsirkin wrote:
> On Wed, Jun 25, 2025 at 04:47:06PM -0400, Stefan Hajnoczi wrote:
> > On Wed, Jun 25, 2025 at 4:39 PM Kevin Wolf wrote:
> > >
> > > Am 25.06.2025 um 21:16 hat Michael S. Tsirkin geschrieben:
> > > > On Mon, Jun 16, 2025 at 11:22:
Hi Igor,
On 6/20/25 3:10 PM, Igor Mammedov wrote:
> On Mon, 16 Jun 2025 11:46:55 +0200
> Eric Auger wrote:
>
>> Signed-off-by: Eric Auger
> why do we still need this?
>
> pcihp code should override native pcie bus handlers, and then
> when device_add calls bus hotplug handlers it will be pcihp o
From: Thanos Makatos
This patch introduces the vfio-user protocol specification (formerly
known as VFIO-over-socket), which is designed to allow devices to be
emulated outside QEMU, in a separate process. vfio-user reuses the
existing VFIO defines, structs and concepts.
It has been earlier discu
Add the cache model to GraniteRapids (v3) to better emulate its
environment.
The cache model is based on GraniteRapids-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level= 0x1 (1)
self-initializ
Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 5 -
1 file changed, 4 insertions(+
Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 5 -
1 file changed, 4 insertions(+)
Add the cache model to SapphireRapids (v4) to better emulate its
environment.
The cache model is based on SapphireRapids-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level= 0x1 (1)
self-initial
Hi,
Since the last RFC, this is now my official patch, trying to add cache
models for Intel CPUs (and Ewai's YongFeng).
This series is based on another series dedicated to cleaning up the
legacy cache models:
https://lore.kernel.org/qemu-devel/20250620092734.1576677-1-zhao1@intel.com/
And t
From: Ewan Hai
Add the cache model to YongFeng (v3) to better emulate its
environment.
Note, although YongFeng v2 was added after v10.0, it was also back
ported to v10.0.2. Therefore, the new version (v3) is needed to avoid
conflict.
The cache model is as follows:
--- cache 0 ---
c
Host SierraForest CPU has 0x1f leaf by default, so that enable it for
Guest CPU by default as well.
Suggested-by: Igor Mammedov
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Rename the property to "x-force-cpuid-0x1f". (Igor)
---
target/i386/cpu.c | 5 -
1 file changed, 4 insertions(+),
Add the cache model to SierraForest (v3) to better emulate its
environment.
The cache model is based on SierraForest-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level= 0x1 (1)
self-initializin
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