Hello,
On 6/20/25 18:40, Paolo Bonzini wrote:
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On request of GetQuote, it connects to the QGS socket, read request
data from shared gues
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 02/19] hw/pci: Introduce pci_device_get_viommu_cap()
>
>Hi Zhenzhong,
>
>On 6/20/25 9:17 AM, Zhenzhong Duan wrote:
>> pci_device_get_viommu_cap() call pci_device_get_iommu_bus_devfn()
>> to get iommu_bus->iommu_ops and
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 18/19] Workaround for ERRATA_772415_SPR17
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> On a system influenced by ERRATA_772415,
>IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17
>> is repored by IOMMU_DEVICE_GET_HW_IN
Hi Cédric,
Sure, I will submit a follow-up patch that includes the following changes:
1. Introduce a new OTP memory device model, which provides in-memory storage
and implements basic MMIO read/write via address space.
2. Initialize the OTP memory device as a child of the SBC controller.
3. Add
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 07/19] intel_iommu: Check for compatibility with
>IOMMUFD backed device when x-flts=on
>
>Hi Zhenzhong,
>
>On 6/20/25 9:18 AM, Zhenzhong Duan wrote:
>> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
>
Hi guys,
Kindly ping for this series.
Thanks,
Shaoqin
On 6/17/25 11:05 AM, Shaoqin Huang wrote:
Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
release package on arm64 it can't find the vgabios-ramfb.
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 05/19] hw/pci: Export pci_device_get_iommu_bus_devfn()
>and return bool
>
>Hi Zhenzhong,
>
>On 6/20/25 9:17 AM, Zhenzhong Duan wrote:
>> Returns true if PCI device is aliased or false otherwise. This will be
>> used in followi
在 2025/6/21 上午2:12, Stefan Hajnoczi 写道:
On Thu, Jun 19, 2025 at 11:11 PM gaosong wrote:
在 2025/6/20 上午4:39, Stefan Hajnoczi 写道:
gpg:using RSA key CA473C44D6A09C189A193FCD452B96852B268216
gpg: Can't check signature: No public key
Why has the GPG key changed? Your previous pull
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v2 04/19] vfio/iommufd: Force creating nested parent
>domain
>
>
>
>On 6/20/25 9:17 AM, Zhenzhong Duan wrote:
>> Call pci_device_get_viommu_cap() to get if vIOMMU supports
>VIOMMU_CAP_STAGE1,
>> if yes, create nested pare
When PIIX3 IDE is used, these two interrupts are
active-low level-triggered but are not set as MADT overrides.
Since the default for legacy interrupts is on rising edge,
these two extra MADT isa irq overrides are needed.
Signed-off-by: Damien Zammit
---
hw/i386/pc_piix.c | 5 +
1 file change
On 6/20/25 10:13, Philippe Mathieu-Daudé wrote:
By converting toAccelOpsClass::cpu_thread_routine we can
let the common accel_create_vcpu_thread() create the thread.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-accel-ops.c | 12 +---
1 file changed, 1 insertion(+), 11 delet
On 6/21/25 16:49, Richard Henderson wrote:
Pipe the value through from SMCR_ELx through hflags
and into the disassembly context.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/arm/tcg/translate.h | 1 +
target/arm/cpu.c | 3 +++
targ
We failed to raise an exception when
sme_excp_el == 0 and fp_excp_el == 1.
Cc: qemu-sta...@nongnu.org
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --g
of it will be cache miss latency anyway.
btw this started as a sketch in a gist in June 20th of last year:
https://gist.github.com/michaeljclark/8f9b81e5e40488035dc252c9da3ecc2e
# the glyph architecture
current: https://metaparadigm.com/~mclark/glyph.pdf
latest: https://metaparadigm.com/~
Supercedes: 20250622175052.180728-1-richard.hender...@linaro.org
("target/arm: Fix SME vs AdvSIMD exception priority")
A couple of fixes for EC_SMETRAP, plus some insns that missed
being updated for non-streaming.
r~
Richard Henderson (3):
target/arm: Fix SME vs AdvSIMD exception priority
On 6/21/25 16:50, Richard Henderson wrote:
+uint64_t HELPER(sve2p1_cntp_c)(uint32_t png, uint32_t desc)
+{
+int pl = FIELD_EX32(desc, PREDDESC, OPRSZ);
+int vl = pl * 8;
+unsigned v_esz = FIELD_EX32(desc, PREDDESC, ESZ);
+int lg2_width = FIELD_EX32(desc, PREDDESC, DATA) + 1;
+
Do not assume SME implies SVE. Ensure that the
non-streaming check is present along the SME path,
since it is not implied by sme_*_enabled_check.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 27 +++
1 file changed, 19 i
of it will be cache miss latency anyway.
btw this started as a sketch in a gist in June 20th of last year:
https://gist.github.com/michaeljclark/8f9b81e5e40488035dc252c9da3ecc2e
# the glyph architecture
current: https://metaparadigm.com/~mclark/glyph.pdf
latest: https://metaparadigm.com/~
On 6/22/25 10:50, Richard Henderson wrote:
We failed to raise an exception when
sme_excp_el == 0 and fp_excp_el == 1.
Cc: qemu-sta...@nongnu.org
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 3 ++-
1 file ch
We failed to raise an exception when
sme_excp_el == 0 and fp_excp_el == 1.
Cc: qemu-sta...@nongnu.org
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --g
On 6/21/25 16:50, Richard Henderson wrote:
This is the single vector version within SVE decode space.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sve.c | 22 ++
target/arm/tcg/sve.decode | 2 ++
2 files changed, 24 insertions(+)
diff --git a/targ
On 6/20/25 10:13, Philippe Mathieu-Daudé wrote:
Currently nvmm_enabled() is restricted to target-specific code.
By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/nvmm.h | 23 ---
accel/stubs/nvmm-s
Hello,
On 6/21/25 14:22, John Levon wrote:
On Fri, Jun 20, 2025 at 10:32:10AM +0200, Cédric Le Goater wrote:
Before merging, I would like to be able to experiment a minimum.
Does a dummy device (server side) implementation exist ? and a
GH repo I could pull the code from.
John,
How do you t
On 6/20/25 10:13, Philippe Mathieu-Daudé wrote:
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_cpu_synchronize_state() stub is not
necessary.
Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes")
Signed-off-by: Philippe Mathieu-Daud
On 6/20/25 10:27, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
accel/split/split-accel-ops.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c
index 0f3d48fc68d..40cd39aea5
Hi Peter,
Sorry for the long delay..
On 2025/3/21 00:55, Zenghui Yu wrote:
> On 2025/3/19 00:56, Peter Maydell wrote:
> >
> > ICC_RPR_EL1 is a read-only register.
>
> Yup! Writes to it should result in an UNDEFINED exception. I completely
> missed that point..
>
> > But hvf_sysreg_read_cp()
> >
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