Re: [PATCH RFC 00/16] virtio: introduce support for GSO over UDP tunnel

On 2025/05/23 18:43, Paolo Abeni wrote: On 5/23/25 9:19 AM, Akihiko Odaki wrote: On 2025/05/21 20:33, Paolo Abeni wrote: Some virtualized deployments use UDP tunnel pervasively and are impacted negatively by the lack of GSO support for such kind of traffic in the virtual NIC driver. The virtio

Re: [PATCH v2] vdpa: Allow VDPA to work on big-endian machine

On 2025/06/16 22:36, Konstantin Shkolnyy wrote: After commit 0caed25cd171 vhost_vdpa_net_load_vlan() started seeing VIRTIO_NET_F_CTRL_VLAN flag and making 4096 calls to the kernel with VIRTIO_NET_CTRL_VLAN_ADD command. However, it forgot to convert the 16-bit VLAN IDs to LE format. On BE machine,

Re: [PULL 12/17] virtio-gpu: support context init multiple timeline

On 2025/06/21 4:47, Yiwei Zhang wrote: On Thu, Jun 19, 2025 at 11:45 PM Alex Bennée wrote: Yiwei Zhang writes: On Sun, Jun 8, 2025 at 1:24 AM Akihiko Odaki wrote: On 2025/06/06 1:26, Alex Bennée wrote: From: Yiwei Zhang Venus and later native contexts have their own fence context alon

[PATCH v3] hw/riscv/virt: Add acpi ged and powerdown support

From: Xuemei Liu This adds powerdown support by implementing the ACPI GED. Signed-off-by: Xuemei Liu Co-authored-by: Björn Töpel --- Changes in v3: - Added missing param to virt_is_acpi_enabled - Fixed failure of bios-tables-test hw/riscv/Kconfig | 1 + hw/riscv/virt-acpi

[RFC PATCH RESEND 37/42] accel/hvf: Emulate HVC at EL2

Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 3907ea8791e..a4f823f834d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -17,6 +17,7 @@ #include "system/hvf.

[RFC PATCH RESEND 35/42] target/arm: Emulate EL2 under TCG

When using hardware acceleration and TCG is available, expose EL2 and EL3 features as available (they will be emulated). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu64.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

[RFC PATCH RESEND 05/42] accel/split: Expose 'hw' and 'sw' properties

In preparation of other accelerator (or potential emulator), expose the "hw" and "sw" keys. Only HVF and TCG allowed so far. Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-all.c | 46 + 1 file changed, 46 insertions(+) diff --git a/accel/spli

[RFC PATCH RESEND 19/42] accel/split: Implement kick_vcpu_thread()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 746a6a2782d..63b6217f3fa 100644 --- a/accel/split/split-accel-ops.c +++ b/accel/sp

[RFC PATCH v2 38/48] accel/whpx: Expose whpx_enabled() to common code

Currently whpx_enabled() is restricted to target-specific code. By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere. Signed-off-by: Philippe Mathieu-Daudé --- include/system/whpx.h | 27 ++- accel/stubs/whpx-stub.c | 12 target/i386/whpx/w

[RFC PATCH RESEND 39/42] target/arm: Implement TCGCPUOps::rebuild_tb_hflags()

Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 2 ++ target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/arm/tcg/hflags.c | 5 + 4 files changed, 9 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c31f69912b8..b703ec7edc9 100644 -

[RFC PATCH RESEND 24/42] accel/split: Implement handle_interrupt()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 399bf71a9ec..5a36e22f205 100644 --- a/accel/split/split-accel-ops.c +++ b/accel

[RFC PATCH RESEND 17/42] accel/split: Implement synchronize_post_reset()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 80efbd82091..91ed0af2746 100644 --- a/accel/split/split-accel-ops.c +++ b/acc

[RFC PATCH RESEND 25/42] accel/split: Empty ops_init()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 5a36e22f205..375821f1064 100644 --- a/accel/split/split-accel-ops.c +++ b/accel/split/split-accel-op

[RFC PATCH RESEND 26/42] accel/split: Empty set/get_virtual_clock()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 12 1 file changed, 12 deletions(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 375821f1064..d19b4641a2e 100644 --- a/accel/split/split-accel-ops.c +++ b/accel/split/split-

[RFC PATCH RESEND 40/42] accel/split: Call TCGCPUOps::rebuild_tb_hflags()

Call TCG rebuild_tb_hflags() when transitioning from hardware accelerator to TCG. Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 615faf1d96b..4b0580

[RFC PATCH RESEND 15/42] accel/split: Implement synchronize_pre_resume()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 6b3ddf21a17..65feb929404 100644 --- a/accel/split/split-accel-ops.c +++ b/ac

[RFC PATCH RESEND 07/42] accel/split: Implement supports_guest_debug()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-all.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/accel/split/split-all.c b/accel/split/split-all.c index 8b9f8ff77a4..cb910300931 100644 --- a/accel/split/split-all.c +++ b/accel/split/split-all.c @

[RFC PATCH RESEND 16/42] accel/split: Implement synchronize_state()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 65feb929404..80efbd82091 100644 --- a/accel/split/split-accel-ops.c +++ b/acc

[RFC PATCH RESEND 41/42] tests/functional: Add split_available() helper

Signed-off-by: Philippe Mathieu-Daudé --- python/qemu/utils/__init__.py | 3 ++- python/qemu/utils/accel.py | 10 ++ tests/functional/qemu_test/testcase.py | 4 +++- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/python/qemu/utils/__init__.py b/pyth

[RFC PATCH RESEND 13/42] accel/split: Implement cpu_reset_hold()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 39495fdff14..d4fa07c2dec 100644 --- a/accel/split/split-accel-ops.c +++ b/ac

[RFC PATCH 00/42] accel/split/arm: Run EL2 using TCG and EL1/EL0 in hardware with HVF

Hi, This RFC is a proof-of-concept we can have QEMU run both software emulator (TCG) and hardware accelerator (here HVF). Unfortunately I'm exhausted so I'll let Alex explain what this is about, otherwise I'll post the real cover letter next Monday after getting some rest. Full work available in

[RFC PATCH RESEND 28/42] accel/split: Empty cpu_thread_is_idle()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 034b5ebc96c..e1d91ace2fa 100644 --- a/accel/split/split-accel-ops.c +++ b/accel/split/split-accel-op

[RFC PATCH RESEND 23/42] target/arm: Implement SysemuCPUOps::can_accelerate() handler

ARM hardware can only accelerate EL0 and EL1. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ab5fbd9b40b..1a19e5cfb45 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -149,6 +

[RFC PATCH RESEND 36/42] target/arm: Have ERET switch to hw accel for EL0/EL1

When hardware accelerator available, use it to directly run EL0 and EL1. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/helper-a64.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 4f618ae390e..5962cff4e7a 100

Re: [PULL 12/17] virtio-gpu: support context init multiple timeline

On Thu, Jun 19, 2025 at 11:45 PM Alex Bennée wrote: > > Yiwei Zhang writes: > > > On Sun, Jun 8, 2025 at 1:24 AM Akihiko Odaki > > wrote: > >> > >> On 2025/06/06 1:26, Alex Bennée wrote: > >> > From: Yiwei Zhang > >> > > >> > Venus and later native contexts have their own fence context along wi

[RFC PATCH RESEND 21/42] accel/split: Set use_hw in cpu_thread_routine() and switch over

Introduce the EXCP_HWACCEL definition to switch to hardware accelerator. Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel.h | 1 + include/exec/cpu-common.h | 1 + accel/split/split-accel-ops.c | 11 +++ 3 files changed, 13 insertions(+) diff --git a/accel/spl

[RFC PATCH RESEND 34/42] accel/split: Implement get_[vcpu]_stats()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel.h | 5 + accel/split/split-accel-ops.c | 24 +++- accel/split/split-all.c | 16 +++- 3 files changed, 43 insertions(+), 2 deletions(-) diff --git a/accel/split/split-accel.h b/accel/s

[RFC PATCH RESEND 01/42] accel/split: Minimal stubs for split accelerator

From: Julian Armistead Signed-off-by: Julian Armistead Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 161 ++ accel/split/split-all.c | 77 system/vl.c | 4 + accel/Kconfig |

[RFC PATCH v2 13/48] accel: Move cpu_common_[un]realize() declarations to AccelOpsClass

AccelClass is for methods dealing with AccelState. When dealing with vCPUs, we want AccelOpsClass. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/accel.h | 2 -- include/system/accel-ops.h | 2 ++ accel/accel-common.c | 10 ++ accel/tcg/tcg-accel-ops.c | 3 +++ ac

[RFC PATCH RESEND 27/42] accel/split: Empty get_elapsed_ticks()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index d19b4641a2e..034b5ebc96c 100644 --- a/accel/split/split-accel-ops.c +++ b/accel/split/split-accel-o

[RFC PATCH RESEND 04/42] accel/split: Implement accel_init_machine()

Force to TCG + HVF for now. Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel.h | 3 +++ accel/split/split-all.c | 30 +- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel.h b/accel/split/split-accel.h index cc82

[RFC PATCH RESEND 11/42] accel/split: Register MTTCG

FIXME: Use sw-hooks? Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 5 + 1 file changed, 5 insertions(+) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index efef0d60fde..2c7945b6331 100644 --- a/accel/split/split-accel-ops.c +++ b/acce

[RFC PATCH RESEND 42/42] tests/functional: Test Aarch64 virt machine with split-accelerator

Signed-off-by: Philippe Mathieu-Daudé --- tests/functional/meson.build| 1 + tests/functional/test_aarch64_virt_split.py | 69 + 2 files changed, 70 insertions(+) create mode 100644 tests/functional/test_aarch64_virt_split.py diff --git a/tests/functional/me

[RFC PATCH RESEND 12/42] accel/split: Have thread routine ready to dispatch over HW/SW

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 22 -- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 2c7945b6331..39495fdff14 100644 --- a/accel/split/split-accel-ops

[RFC PATCH v2 41/48] accel/tcg: Factor tcg_vcpu_init() out for re-use

Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops.h | 2 ++ accel/tcg/tcg-accel-ops-mttcg.c | 4 +++- accel/tcg/tcg-accel-ops-rr.c| 4 +++- accel/tcg/tcg-accel-ops.c | 7 +++ 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-op

Re: [PULL 00/14] loongarch-to-apply queue

On Thu, Jun 19, 2025 at 11:11 PM gaosong wrote: > > 在 2025/6/20 上午4:39, Stefan Hajnoczi 写道: > > gpg:using RSA key CA473C44D6A09C189A193FCD452B96852B268216 > > gpg: Can't check signature: No public key > > > > Why has the GPG key changed? Your previous pull request was signed > > wi

[RFC PATCH RESEND 10/42] accel/split: Define and allocate AccelCPUState

AccelCPUState is where we store per-vCPU accelerator related information. FIXME: structures might clash so add padding (ok with TCG+HVF) Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel.h | 7 +++ accel/split/split-accel-ops.c | 9 - 2 files changed, 15 insertio

[RFC PATCH RESEND 14/42] accel/split: Implement synchronize_post_init()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index d4fa07c2dec..6b3ddf21a17 100644 --- a/accel/split/split-accel-ops.c +++ b/acc

[RFC PATCH RESEND 08/42] accel/split: Implement gdbstub_supported_sstep_flags()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-all.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/accel/split/split-all.c b/accel/split/split-all.c index cb910300931..413954af96c 100644 --- a/accel/split/split-all.c +++ b/accel/split/split-all.c

[RFC PATCH RESEND 09/42] accel/split: Add cpu_thread_routine() stub

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 70 ++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index e5c1d51d426..294ea79420e 100644 --- a/accel/split/spl

[RFC PATCH RESEND 38/42] accel/tcg: Introduce TCGCPUOps::rebuild_tb_hflags handler

In order to allow rebuilding target specific TB flags, introduce tcg_rebuild_tb_flags() which dispatches to a TCGCPUOps handler. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/internal-common.h | 1 + include/accel/tcg/cpu-ops.h | 2 ++ include/system/accel-ops.h | 8 accel/tcg/cp

[RFC PATCH RESEND 31/42] accel/split: Implement remove_breakpoint()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 0f3d48fc68d..40cd39aea5c 100644 --- a/accel/split/split-accel-ops.c +++ b/a

[RFC PATCH RESEND 18/42] accel/split: Implement synchronize_pre_loadvm()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 91ed0af2746..746a6a2782d 100644 --- a/accel/split/split-accel-ops.c +++ b/acc

[RFC PATCH RESEND 33/42] accel/split: Implement update_guest_debug()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index eb52d690c7c..d59e70e0d9b 100644 --- a/accel/split/split-accel-ops.c +++ b/acc

[RFC PATCH RESEND 02/42] accel/split: Define SplitAccelState

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel.h | 38 ++ accel/split/split-all.c | 5 - 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 accel/split/split-accel.h diff --git a/accel/split/split-accel.h b/accel/spl

[RFC PATCH RESEND 22/42] accel/split: Add few trace events in cpu_thread_routine handler

Signed-off-by: Philippe Mathieu-Daudé --- meson.build | 1 + accel/split/trace.h | 2 ++ accel/split/split-accel-ops.c | 7 +++ accel/split/trace-events | 9 + 4 files changed, 19 insertions(+) create mode 100644 accel/split/trace.h create mode 10064

[RFC PATCH RESEND 32/42] accel/split: Implement insert_breakpoint()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 40cd39aea5c..eb52d690c7c 100644 --- a/accel/split/split-accel-ops.c +++ b/a

[RFC PATCH v2 34/48] accel/kvm: Convert to AccelOpsClass::cpu_thread_routine

By converting to AccelOpsClass::cpu_thread_routine we can let the common accel_create_vcpu_thread() create the thread. Signed-off-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-accel-ops.c | 12 +--- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/accel/kvm/kvm-accel-ops.c b/

[RFC PATCH RESEND 29/42] accel/split: Kludge qemu_tcg_mttcg_enabled()

../../accel/tcg/tcg-all.c:59:TCG_STATE: Object 0x60c42740 is not an instance of type tcg-accel Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-all.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index f5920b5796e..96104915eef 100644 --

[RFC PATCH RESEND 06/42] accel/split: Empty setup_post()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-all.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/accel/split/split-all.c b/accel/split/split-all.c index 28f626d0ff4..8b9f8ff77a4 100644 --- a/accel/split/split-all.c +++ b/accel/split/split-all.c @@ -37,11 +37,6 @@ static

[RFC PATCH RESEND 00/42] accel/split/arm: Run EL2 using TCG and EL1/EL0 in hardware with HVF

Hi, This RFC is a proof-of-concept we can have QEMU run both software emulator (TCG) and hardware accelerator (here HVF). Unfortunately I'm exhausted so I'll let Alex explain what this is about, otherwise I'll post the real cover letter next Monday after getting some rest. Full work available in

[RFC PATCH RESEND 20/42] accel/split: Implement cpu_common_realize()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index 63b6217f3fa..3278e01f18a 100644 --- a/accel/split/split-accel-ops.c +++ b/accel

[RFC PATCH v2 29/48] accel: Factor accel_create_vcpu_thread() out

Factor accel_create_vcpu_thread() out of system/cpus.c to be able to access accel/ internal definitions. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/accel.h | 2 ++ accel/accel-common.c | 19 +++ system/cpus.c| 4 +--- 3 files changed, 22 insertions(+), 3 del

[RFC PATCH RESEND 30/42] accel/split: Implement remove_all_breakpoints()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-accel-ops.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/split/split-accel-ops.c b/accel/split/split-accel-ops.c index e1d91ace2fa..0f3d48fc68d 100644 --- a/accel/split/split-accel-ops.c +++ b/acc

[RFC PATCH RESEND 03/42] accel/split: Implement cpus_are_resettable()

Signed-off-by: Philippe Mathieu-Daudé --- accel/split/split-all.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/accel/split/split-all.c b/accel/split/split-all.c index 6bc95c7a7c8..c86d0e8583a 100644 --- a/accel/split/split-all.c +++ b/accel/split/split-all.c @

[PATCH 07/16] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel

Per SDM, 0x8005 leaf is reserved for Intel CPU, and its current "assert" check blocks adding new cache model for non-AMD CPUs. And please note, although Zhaoxin mostly follows Intel behavior, this leaf is an exception [1]. So, add a compat property "x-vendor-cpuid-only-v2" (for PC machine v10

[PULL 19/24] i386/cpu: Rename enable_cpuid_0x1f to force_cpuid_0x1f

From: Xiaoyao Li The name of "enable_cpuid_0x1f" isn't right to its behavior because the leaf 0x1f can be enabled even when "enable_cpuid_0x1f" is false. Rename it to "force_cpuid_0x1f" to better reflect its behavior. Suggested-by: Igor Mammedov Signed-off-by: Xiaoyao Li Reviewed-by: Daniel P

[PULL 15/24] rust: hpet: fix new warning

Nightly rustc complains that HPETAddrDecode has a lifetime but it is not clearly noted that it comes from &self. Apply the compiler's suggestion to shut it up. Reviewed-by: Zhao Liu Reviewed-by: Stefan Hajnoczi Signed-off-by: Paolo Bonzini --- rust/hw/timer/hpet/src/device.rs | 2 +- 1 file c

[PATCH v2 18/26] target/arm/hvf: Trace host processor features

Tracing an Apple M1 (Icestorm core, ARMv8.4-A): hvf_processor_feature_register EL0: 1 hvf_processor_feature_register EL1: 1 hvf_processor_feature_register EL2: 0 hvf_processor_feature_register FP: 1 hvf_processor_feature_register AdvSIMD: 1 hvf_processor_feature_register GIC: 0 hvf_p

[PATCH v2 20/26] hw/arm/virt: Only require TCG || QTest to use virtualization extension

We can not start in EL2 / EL3 with anything but TCG (or QTest); whether KVM or HVF are used is not relevant. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ar

Re: [PATCH v2] target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction

On 6/18/25 6:35 PM, Vasilis Liaskovitis wrote: Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1 and rd arguments are x0. In this case, if the new property is true, only the vill bit will be set. See https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ex

[PATCH v2 26/26] tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator

Signed-off-by: Philippe Mathieu-Daudé --- tests/functional/test_aarch64_smmu.py | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tests/functional/test_aarch64_smmu.py b/tests/functional/test_aarch64_smmu.py index c65d0f28178..59b62a55a9e 100755 --- a/tests/functional/

[PULL 18/24] i386/tdx: Error and exit when named cpu model is requested

From: Xiaoyao Li Currently, it gets below error when requesting any named cpu model with "-cpu" to boot a TDX VM: qemu-system-x86_64: KVM_TDX_INIT_VM failed: Invalid argument It misleads people to think it's the bug of KVM or QEMU. It is just that current QEMU doesn't support named cpu model

[PULL 07/24] rust: qom: introduce ParentInit

This is a smart pointer for MaybeUninit; it can be upcasted to the already-initialized parent classes, or dereferenced to a MaybeUninit for the class that is being initialized. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/qom.rs | 96 +

[PATCH 0/3] Reinvent BQL-free PIO/MMIO

When booting WS2025 with following CLI 1) -M q35,hpet=off -cpu host -enable-kvm -smp 240,sockets=4 the guest boots very slow and is sluggish after boot or it's stuck on boot at spinning circle. pref shows that VM is experiencing heavy BQL contention on IO path which happens to be ACPI PM timer

[PATCH v2 04/26] target/arm/hvf: Simplify GIC hvf_arch_init_vcpu()

Only update the ID_AA64PFR0_EL1 register when a GIC is provided. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 42258cc2d88..c1ed8b510db 100644 ---

Re: [PATCH 0/2] virtio-9p: move G_GNUC_PRINTF to header

Hi Christian, On 2025/6/20 10:17 AM, Christian Schoenebeck wrote: On Saturday, June 14, 2025 4:07:40 AM CEST Sean Wei wrote: v9fs_string_sprintf() and v9fs_path_sprintf() already have G_GNUC_PRINTF annotations in their own *.c files, but the prototypes in the corresponding headers lack them. W

[PATCH v2 10/26] accel/hvf: Model PhysTimer register

Emulate PhysTimer dispatching to TCG, like we do with GIC registers. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index bf59b17dcb9..5169bf6e23c

[RFC PATCH v2 09/48] accel/tcg: Prefer local AccelState over global current_accel()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/tcg-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 6c5979861cf..4b1238ed345 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@

[RFC PATCH v2 20/48] cpus: Rename 'vcpu_dirty' field as negated 'hwaccel_synchronized'

Try to better describe which side is dirty (QEMU process or hardware accelerator) by renaming as @hwaccel_synchronized. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 4 ++-- accel/kvm/kvm-all.c | 20 ++-- target/mips/kvm.c | 4 ++-- 3 files changed, 14

[RFC PATCH v2 30/48] accel: Introduce AccelOpsClass::cpu_thread_routine handler

In order to have a generic function creating threads, introduce the thread_precreate() and cpu_thread_routine() handlers. Signed-off-by: Philippe Mathieu-Daudé --- include/system/accel-ops.h | 5 - accel/accel-common.c | 16 +++- system/cpus.c | 2 +- 3 files

[PATCH v2 23/26] tests/functional: Restrict nexted Aarch64 Xen test to TCG

On macOS this test fails: qemu-system-aarch64: mach-virt: HVF does not support providing Virtualization extensions to the guest CPU Signed-off-by: Philippe Mathieu-Daudé --- tests/functional/test_aarch64_xen.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/functional/test_aarch64

[RFC PATCH v2 14/48] hw/core/machine: Display CPU model name in 'info cpus' command

Display the CPU model in 'info cpus'. Example before: $ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio QEMU 10.0.0 monitor - type 'help' for more information (qemu) info cpus * CPU #0: thread_id=42924 CPU #1: thread_id=42924 CPU #2: thread_id=42924 CPU #3: thread_id=42924

[RFC PATCH v2 19/48] cpus: Document CPUState::vcpu_dirty field

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 33296a1c080..69ea425c458 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -441,6 +441,7 @@ struct qemu_work_item

[RFC PATCH v2 25/48] accel/system: Document cpu_synchronize_state()

Signed-off-by: Philippe Mathieu-Daudé --- include/system/accel-ops.h | 8 include/system/hw_accel.h | 13 +++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h index 5c5171ea5b5..f40098c1c92 100644 --- a/in

[RFC PATCH v2 02/48] system/cpus: Defer memory layout changes until vCPUs are realized

vCPUs are not really usable until fully realized. Do not attempt to commit memory changes in the middle of vCPU realization. Defer until realization is completed and vCPU fully operational. Signed-off-by: Philippe Mathieu-Daudé --- system/physmem.c | 8 1 file changed, 8 insertions(+)

[RFC PATCH v2 21/48] accel/hvf: Replace @dirty field by generic @hwaccel_synchronized

No need for accel-specific @dirty field when we have a generic one in CPUState. Signed-off-by: Philippe Mathieu-Daudé --- include/system/hvf_int.h | 1 - accel/hvf/hvf-accel-ops.c | 10 +- target/arm/hvf/hvf.c | 4 ++-- target/i386/hvf/hvf.c | 4 ++-- target/i386/hvf/x86hvf.

[RFC PATCH v2 33/48] accel/hvf: Convert to AccelOpsClass::cpu_thread_routine

By converting to AccelOpsClass::cpu_thread_routine we can let the common accel_create_vcpu_thread() create the thread. Signed-off-by: Philippe Mathieu-Daudé --- accel/hvf/hvf-accel-ops.c | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/accel/hvf/hvf-accel-op

Re: [PATCH v3 09/29] hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_method

On Mon, 16 Jun 2025 11:46:38 +0200 Eric Auger wrote: > gpex build_host_bridge_osc() and x86 originated > build_pci_host_bridge_osc_method() are mostly identical. > > In GPEX, SUPP is set to CDW2 but is not further used. CTRL > is same as Local0. > > So let gpex code reuse build_pci_host_bridge_

[PULL 10/24] rust: prepare variable definitions for multiple bindgen invocations

When splitting the QEMU Rust bindings into multiple crates, the bindgen-generated structs also have to be split so that it's possible to add "impl" blocks (e.g. for Sync/Send or Default, or even for utility methods in cases such as VMStateFlags). Tweak various variable definitions in meson.build,

[PULL 14/24] rust: pl011: Add missing logging to match C version

From: Bernhard Beschow Co-developed-by: Paolo Bonzini Signed-off-by: Bernhard Beschow Link: https://lore.kernel.org/r/20250615112037.11992-4-shen...@gmail.com Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 6 ++ 1 file changed, 6 insertions(+) diff --git a/rust/hw/ch

Re: [PATCH v3 06/29] hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation

On Mon, 16 Jun 2025 11:46:35 +0200 Eric Auger wrote: > acpi_dsdt_add_pci_osc() name is confusing as it gives the impression > it appends the _OSC method but in fact it also appends the _DSM method > for the host bridge. Let's split the function into two separate ones > and let them return the met

Re: [PATCH v4 1/7] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association

On Thu, 19 Jun 2025 10:38:02 +0100 Jonathan Cameron wrote: > On Thu, 19 Jun 2025 10:30:28 +0100 > Jonathan Cameron wrote: > > > On Thu, 19 Jun 2025 09:05:07 +0100 > > Shameerali Kolothum Thodi wrote: > > > > > > -Original Message- > > > > From: Eric Auger > > > > Sent: Thursday, Ju

Re: [PATCH] qga-vss: Exit with non-zero code when register fail

On Fri, Jun 20, 2025 at 12:33 PM Kostiantyn Kostiuk wrote: > > QGA installer uses rundll32 to run the DLLCOMRegister function > from qga-vss.dll and perform VSS provider registration. > rundll32 ignores the return value of the function and always > exits with a zero exit code. This causes a situat

[RFC PATCH v2 39/48] accel/system: Introduce hwaccel_enabled() helper

hwaccel_enabled() return whether any hardware accelerator is available. Signed-off-by: Philippe Mathieu-Daudé --- include/system/hw_accel.h | 21 + 1 file changed, 21 insertions(+) diff --git a/include/system/hw_accel.h b/include/system/hw_accel.h index 574c9738408..49556b02

Re: [PATCH v2 10/19] intel_iommu: Handle PASID entry removing and updating

Hi Zhenzhong, On 6/20/25 9:18 AM, Zhenzhong Duan wrote: I would suggest: Handle PASID entry removal and update instead of verbing. > This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the > pasid entry and track PASID usage and future PASID tagged DMA address > translation suppo

Re: [PATCH v3 01/28] Add boot-certificates to s390-ccw-virtio machine type option

On 6/6/25 10:00 AM, Daniel P. Berrangé wrote: > On Wed, Jun 04, 2025 at 05:56:29PM -0400, Zhuoying Cai wrote: >> Add boot-certificates as a parameter of s390-ccw-virtio machine type option. >> >> The `boot-certificates=/path/dir:/path/file` parameter is implemented >> to provide path to either a di

[RFC PATCH v2 28/48] accel/dummy: Factor tcg_vcpu_thread_precreate() out

Factor tcg_vcpu_thread_precreate() out for re-use. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops.h | 1 + accel/tcg/tcg-accel-ops-mttcg.c | 3 +-- accel/tcg/tcg-accel-ops-rr.c| 3 +-- accel/tcg/tcg-accel-ops.c | 7 +++ 4 files changed, 10 insertions(+), 4

Re: [PATCH v2 03/19] intel_iommu: Implement get_viommu_cap() callback

Hi Zhenzhong, On 6/20/25 9:17 AM, Zhenzhong Duan wrote: > Implement get_viommu_cap() callback and expose stage-1 capability for now. > > VFIO uses it to create nested parent domain which is further used to create > nested domain in vIOMMU. All these will be implemented in following patches. > > Su

[RFC PATCH v2 16/48] accel/tcg: Factor tcg_dump_flush_info() out

Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/internal-common.h | 2 ++ accel/tcg/monitor.c | 27 +-- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 1dbc45dd955..fb265d0cefa 10

[PATCH 06/16] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState

With the pre-defined cache model legacy_intel_cpuid2_cache_info, for X86CPUState there's no need to cache special cache information for CPUID 0x2 leaf. Drop the cache_info_cpuid2 field of X86CPUState and use the legacy_intel_cpuid2_cache_info directly. Signed-off-by: Zhao Liu --- target/i386/cp

[PATCH 04/16] i386/cpu: Present same cache model in CPUID 0x2 & 0x4

For a long time, the default cache models used in CPUID 0x2 and 0x4 were inconsistent and had a FIXME note from Eduardo at commit 5e891bf8fd50 ("target-i386: Use #defines instead of magic numbers for CPUID cache info"): "/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */". This

[PATCH 03/16] i386/cpu: Add default cache model for Intel CPUs with level < 4

Old Intel CPUs with CPUID level < 4, use CPUID 0x2 leaf (if available) to encode cache information. Introduce a cache model "legacy_intel_cpuid2_cache_info" for the CPUs with CPUID level < 4, based on legacy_l1d_cache, legacy_l1i_cache, legacy_l2_cache_cpuid2 and legacy_l3_cache. But for L2 cache,

Re: [RFC PATCH] target/arm: clamp value to account for RES0 fields

Peter Maydell writes: > On Mon, 16 Jun 2025 at 21:10, Alex Bennée wrote: >> >> If the user writes a large value to the register but with the bottom >> bits unset we could end up with something illegal. By clamping ahead >> of the check we at least assure we won't assert(bpr > 0) later in the >>

Re: [PATCH v3 15/29] hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info

On Mon, 16 Jun 2025 11:46:44 +0200 Eric Auger wrote: > pcihp acpi_set_pci_info() generic code currently uses > acpi_get_i386_pci_host() to retrieve the pci host bridge. > > To make it work also on ARM we get rid of that call and > directly use AcpiPciHpState::root. > > Signed-off-by: Eric Auger

Re: [PATCH v3 05/29] tests/qtest/bios-tables-test: Prepare for changes in the DSDT table

On 6/20/25 10:49 AM, Jonathan Cameron wrote: > On Mon, 16 Jun 2025 11:46:34 +0200 > Eric Auger wrote: > >> From: Gustavo Romero >> >> This commit adds DSDT blobs to the whilelist in the prospect to >> allow changes in the GPEX _OSC method. >> >> Signed-off-by: Gustavo Romero >> Signed-off-by:

[PULL 03/24] hw: Fix type constant for DTB files

From: Bernhard Beschow Commit fcb1ad456c58 ("system/datadir: Add new type constant for DTB files") introduced a new type constant for DTB files and converted the boards with bundled device trees to use it. Convert the other boards for consistency. Fixes: fcb1ad456c58 ("system/datadir: Add new ty

[PULL 00/24] i386 (TCG, TDX), Rust changes for 2025-06-20

The following changes since commit a6f02277595136832c9e9bcaf447ab574f7b1128: Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2025-06-12 14:16:11 -0400) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to

[RFC PATCH v2 26/48] accel/system: Document cpu_synchronize_state_post_init/reset()

Signed-off-by: Philippe Mathieu-Daudé --- include/system/accel-ops.h | 8 1 file changed, 8 insertions(+) diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h index f40098c1c92..b1b9dce27d0 100644 --- a/include/system/accel-ops.h +++ b/include/system/accel-ops.h @@ -43,6

[RFC PATCH v2 23/48] accel/whpx: Replace @dirty field by generic @hwaccel_synchronized

No need for accel-specific @dirty field when we have a generic one in CPUState. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/whpx/whpx-all.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-

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