On 6/20/2025 4:33 AM, Paolo Bonzini wrote:
This is my update of Binbin's patches from
https://github.com/intel-staging/qemu-tdx/commits/binbinwu/GetTdVmCallInfo_fixup/,
updated for the proposed userspace API at
https://lore.kernel.org/kvm/20250619180159.187358-1-pbonz...@redhat.com/T/
and with a
Hi Gustavo,
On 6/19/25 7:07 PM, Gustavo Romero wrote:
> Hi Eric,
>
> On 6/17/25 10:22, Eric Auger wrote:
>> Hi Gustavo,
>>
>> On 6/16/25 3:18 PM, Gustavo Romero wrote:
>>> The comment about the mapping from SMMU to ITS is incorrect and it
>>> reads
>>> "RC -> ITS". The code in question actually ma
On 6/20/2025 4:33 AM, Paolo Bonzini wrote:
...
+static void tdx_generate_quote_cleanup(TdxGenerateQuoteTask *task)
+{
+timer_del(&task->timer);
+
+g_source_remove(task->watch);
It needs to be
if (task->watch) {
g_source_remove(task->watch);
}
for the
Yiwei Zhang writes:
> On Sun, Jun 8, 2025 at 1:24 AM Akihiko Odaki
> wrote:
>>
>> On 2025/06/06 1:26, Alex Bennée wrote:
>> > From: Yiwei Zhang
>> >
>> > Venus and later native contexts have their own fence context along with
>> > multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING
This short series adds the 'address type' bit (concept from PCIe) to the
memory attributes and extends the IOMMUAccessFlags enum. This
will be required to implement ATS support for the virtual IOMMUs.
Address type: Field present in the PCIe R/W requests, it allows devices to
tell the IOMMU if the
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added (defined by the PCIe 5 specification)
The address_type bit will be set to PCI_AT_TRANSLATED by devices that
use cached addresses obtained via ATS.
Signed-off-by: Clement Mathieu--Drif
---
include/exec/memattrs.h | 3 +++
include/hw/pci/pci.h| 9 +
2 files changed, 12 insertions(+)
diff --git a/include/exec/memattrs.h b/
Hi Cédric,
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH V5 00/38] Live update: vfio and iommufd
>
>Zhenzhong, Eric,
>
>On 6/12/25 09:23, Cédric Le Goater wrote:
>> On 6/11/25 16:39, Steven Sistare wrote:
>>> On 6/11/2025 10:25 AM, Cédric Le Goater wrote:
On 6/10/2
Hello Kane,
On 6/19/25 08:41, Kane Chen wrote:
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoCs (AST2600, AST1030).
The OTP model emulates a simpl
On 6/19/2025 10:29 PM, Peter Xu wrote:
> On Thu, Jun 19, 2025 at 11:06:46AM +0800, Chenyi Qiang wrote:
>> To fix the build error with --enable-docs configuration, Add the below fixup
>
> Thanks, this works for me.
>
> Though I just noticed it has more than the doc issue.. please see:
>
> http
From: Xuemei Liu
This adds powerdown support by implementing the ACPI GED.
Signed-off-by: Xuemei Liu
Co-authored-by: Björn Töpel
---
Changes in v2:
- Unwrappered acpi_dsdt_add_ged function
- Modified base address of VIRT_ACPI_GED
- Added conditions for function calls
- Adjusted code formattin
在 2025/6/20 上午4:39, Stefan Hajnoczi 写道:
gpg:using RSA key CA473C44D6A09C189A193FCD452B96852B268216
gpg: Can't check signature: No public key
Why has the GPG key changed? Your previous pull request was signed
with key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF.
If you would like to
On 6/12/2025 4:27 PM, Chenyi Qiang wrote:
> Commit 852f0048f3 ("RAMBlock: make guest_memfd require uncoordinated
> discard") highlighted that subsystems like VFIO may disable RAM block
> discard. However, guest_memfd relies on discard operations for page
> conversion between private and shared m
On Sun, Jun 8, 2025 at 1:24 AM Akihiko Odaki
wrote:
>
> On 2025/06/06 1:26, Alex Bennée wrote:
> > From: Yiwei Zhang
> >
> > Venus and later native contexts have their own fence context along with
> > multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in
> > the flags must be di
available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-20250619
From https://github.com/gaosong715/qemu
* tag pull-loongarch-20250619 -> FETCH_HEAD
gpg: Signature made Thu 19 Jun 2025 04:49:38 EDT
gpg:
> Subject: Re: [PATCH v4] hw/misc/aspeed_scu: Handle AST2600 protection key
> registers correctly
>
> Jamin,
>
> On 6/19/25 10:53, Tan Siewert wrote:
> > The AST2600 SCU has two protection key registers (0x00 and 0x10) that
> > both need to be unlocked. (Un-)locking 0x00 modifies both protection
Commit 816a430c517e ("util/aio: Defer disabling poll mode as long as
possible") kept polling enabled when the event loop timeout is 0. Since
there is no timeout the event loop will continue immediately and the
overhead of disabling and re-enabling polling can be avoided.
fdmon-io_uring.c is unable
test-nested-aio-poll relies on internal details of how fdmon-poll.c
handles AioContext polling. Skip it when other fdmon implementations are
in use.
Note that this test is only built on POSIX systems so it is safe to
include "util/aio-posix.h".
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Bl
Introduce the aio_add_sqe() API for submitting io_uring requests in the
current AioContext. This allows other components in QEMU, like the block
layer, to take advantage of io_uring features without creating their own
io_uring context.
This API supports nested event loops just like file descriptor
io_uring may not be available at runtime due to system policies (e.g.
the io_uring_disabled sysctl) or creation could fail due to file
descriptor resource limits.
Handle failure scenarios as follows:
If another AioContext already has io_uring, then fail AioContext
creation so that the aio_add_sqe
When an AioHandler is enqueued on ctx->submit_list for removal, the
fill_sq_ring() function will submit an io_uring POLL_REMOVE operation to
cancel the in-flight POLL_ADD operation.
There is a race when another thread enqueues an AioHandler for deletion
on ctx->submit_list when the POLL_ADD CQE ha
AioContext has its own io_uring instance for file descriptor monitoring.
The disk I/O io_uring code was developed separately. Originally I
thought the characteristics of file descriptor monitoring and disk I/O
were too different, requiring separate io_uring instances.
Now it has become clear to me
When aio_context_new() -> aio_context_setup() fails at startup it
doesn't really matter whether errors are returned to the caller or the
process terminates immediately.
However, it is not acceptable to terminate when hotplugging --object
iothread at runtime. Refactor aio_context_setup() so that er
The io_uring_prep_readv2/writev2() man pages recommend using the
non-vectored read/write operations when possible for performance
reasons.
I didn't measure a significant difference but it doesn't hurt to have
this optimization in place.
Suggested-by: Eric Blake
Signed-off-by: Stefan Hajnoczi
--
v2:
- Performance improvements
- Fix pre_sqe -> prep_sqe typo [Eric]
- Add #endif terminator comment [Eric]
- Fix spacing in aio_ctx_finalize() argument list [Eric]
- Add new "block/io_uring: use non-vectored read/write when possible" patch
[Eric]
- Drop Patch 1 because multi-shot POLL_ADD has edg
There is no need for aio_context_use_g_source() now that epoll(7) and
io_uring(7) file descriptor monitoring works with the glib event loop.
AioContext doesn't need to be notified that GSource is being used.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
---
include/block/aio.h
AioContext's glib integration only supports ppoll(2) file descriptor
monitoring. epoll(7) and io_uring(7) disable themselves and switch back
to ppoll(2) when the glib event loop is used. The main loop thread
cannot use epoll(7) or io_uring(7) because it always uses the glib event
loop.
Future QEMU
fdmon_ops->wait() is called with notify_me enabled. This makes it an
expensive place to call qemu_bh_schedule() because aio_notify() invokes
write(2) on the EventNotifier.
Moving qemu_bh_schedule() after notify_me is reset improves IOPS from
270k to 300k IOPS with --blockdev file,aio=io_uring.
I
g_source_destroy() only removes the GSource from the GMainContext it's
attached to, if any. It does not free it.
Use g_source_unref() instead so that the AioContext (which embeds a
GSource) is freed. There is no need to call g_source_destroy() in
aio_context_new() because the GSource isn't attache
On 19/6/25 15:13, Philippe Mathieu-Daudé wrote:
Trace memory mapped / unmapped in the guest.
Signed-off-by: Philippe Mathieu-Daudé
---
meson.build | 1 +
accel/hvf/trace.h | 2 ++
accel/hvf/hvf-accel-ops.c | 6 ++
accel/hvf/trace-events| 7 +++
4 files ch
On 19/6/25 23:28, Richard Henderson wrote:
On 6/19/25 14:20, Philippe Mathieu-Daudé wrote:
@@ -756,7 +756,9 @@ static void sbsa_ref_init(MachineState *machine)
sms->smp_cpus = smp_cpus;
if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
- error_report("sbsa-ref: cannot
On 6/19/25 14:20, Philippe Mathieu-Daudé wrote:
@@ -756,7 +756,9 @@ static void sbsa_ref_init(MachineState *machine)
sms->smp_cpus = smp_cpus;
if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
- error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
+
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Allow distinguishing HV_ILLEGAL_GUEST_STATE in trace events.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/hvf/hvf.c| 10 +-
target/arm/hvf/trace-events | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
Reviewed-
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
We only need TCG (or QTest) to use TrustZone, whether
KVM or HVF are used is not relevant.
Reported-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Rich
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Setting ARMCPU::gt_cntfrq_hz in hvf_arch_init_vcpu() is
not correct because the timers have already be initialized
with the default frequency.
Set it earlier in the AccelOpsClass::cpu_target_realize()
handler instead, and assert the value is correc
On Thu, Jun 19, 2025 at 8:38 PM Ilya Dryomov wrote:
>
> On Mon, Jun 16, 2025 at 2:38 PM Fiona Ebner wrote:
> >
> > Am 16.06.25 um 12:28 schrieb Ilya Dryomov:
> > > On Mon, Jun 16, 2025 at 11:52 AM Daniel P. Berrangé
> > > wrote:
> > >> On Mon, Jun 16, 2025 at 11:25:54AM +0200, Ilya Dryomov wrot
On 19/6/25 23:09, Richard Henderson wrote:
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Define RAMLIMIT_BYTES using the TiB definition and display
the error parsed with size_to_str():
$ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T
qemu-system-aarch64-unsigned: sbsa-ref: cannot model
On 19/6/25 15:13, Philippe Mathieu-Daudé wrote:
Do not expose system-specific properties on user-mode binaries.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index eb0639de
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8".
Fixes: 585df85efea ("hvf: arm: Implement -cpu host")
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/hvf/hvf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Tracing $PC for unknown HVC instructions to not have to
look at the disassembled flow of instructions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/hvf/hvf.c| 4 ++--
target/arm/hvf/trace-events | 2 +-
2 files changed, 3 insert
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Same code, use the generic variant.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/translate.h | 1 +
target/arm/tcg/translate-a64.c | 6 --
target/arm/tcg/translate.c | 2 +-
3 files changed, 2 insertions(+), 7 deletions
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Since commit 0c1aaa66c24 ("target/arm: wrap psci call with
tcg_enabled") the arm_handle_psci_call() call is elided
when TCG is disabled.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 6 +-
1 file changed, 1 insertion(+)
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
arm_cpu_post_init() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 2 --
target/arm/cpu.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 6/19/25 06:13, Philippe Mathieu-Daudé wrote:
Define RAMLIMIT_BYTES using the TiB definition and display
the error parsed with size_to_str():
$ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T
qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of RAM
Signed-off-by: Phili
On 18/6/25 13:27, Mark Cave-Ayland wrote:
This is to prepare for splitting the isapc machine into its own separate file.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 260 +-
1 file changed, 259 insertions(+), 1 deletion(-)
Reviewed-by:
On 18/6/25 13:27, Mark Cave-Ayland wrote:
This code will never be used for an isapc machine.
s/This/PCI/
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 105 --
1 file changed, 8 insertions(+), 97 d
On 18/6/25 13:27, Mark Cave-Ayland wrote:
These are based upon the PIIX4 PCI chipset and so can never be used on an isapc
machine.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 19 ---
1 file changed, 19 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 18/6/25 13:27, Mark Cave-Ayland wrote:
NVDIMMs cannot be used by PCs from a pre-PCI era.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 6 --
1 file changed, 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 18/6/25 13:27, Mark Cave-Ayland wrote:
All isapc machines must have 32-bit CPUs and so the RAM split logic can be
hardcoded
accordingly.
s/32-bit CPUs/32-bit address space/?
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 58 ---
1
On 18/6/25 13:27, Mark Cave-Ayland wrote:
Now that pc_init_isa() is independent of any PCI initialisation, move it into a
separate isapc.c file. This enables us to finally fix the dependency of ISAPC on
I440FX in hw/i386/Kconfig.
Note that as part of the move to a separate file we can see that t
On 18/6/25 13:27, Mark Cave-Ayland wrote:
All isapc machines must have 32-bit CPUs and have no PCI 64-bit hole so it can
be
hardcoded to 0.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 18/6/25 13:27, Mark Cave-Ayland wrote:
By definition an isapc machine must always use ISA IDE drives
ISA: yes, IDE: not necessarily. Anyhow,
Reviewed-by: Philippe Mathieu-Daudé
so ensure that they
are always enabled. At the same time also remove the surrounding CONFIG_IDE_ISA
define sinc
On 18/6/25 13:27, Mark Cave-Ayland wrote:
By definition PCI can never be enabled on an isapc machine so hardcode the
relevant values
set via pcmc->pci_enabled.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Phil
On 18/6/25 13:27, Mark Cave-Ayland wrote:
By definition PCI can never be enabled on an isapc machine so hardcode the
PCIBus argument
of pc_nic_init() to NULL.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe
ilable in the Git repository at:
>
> https://github.com/gaosong715/qemu.git tags/pull-loongarch-20250619
>From https://github.com/gaosong715/qemu
* tag pull-loongarch-20250619 -> FETCH_HEAD
gpg: Signature made Thu 19 Jun 2025 04:49:38 EDT
gpg:using RSA k
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On request of GetQuote, it connects to the QGS socket, read request
data from shared guest memory, send the request data to the QGS,
and s
This is my update of Binbin's patches from
https://github.com/intel-staging/qemu-tdx/commits/binbinwu/GetTdVmCallInfo_fixup/,
updated for the proposed userspace API at
https://lore.kernel.org/kvm/20250619180159.187358-1-pbonz...@redhat.com/T/
and with a few tweaks to drop the remains of the
quote g
Signed-off-by: Paolo Bonzini
---
include/standard-headers/asm-x86/setup_data.h | 13 +-
include/standard-headers/drm/drm_fourcc.h | 45 +++
include/standard-headers/linux/ethtool.h | 124 +-
include/standard-headers/linux/fuse.h | 6 +-
.../linux/input-eve
From: Binbin Wu
Signed-off-by: Binbin Wu
Signed-off-by: Paolo Bonzini
---
target/i386/kvm/tdx.h | 9 +
target/i386/kvm/kvm.c | 12
target/i386/kvm/tdx-stub.c | 4
target/i386/kvm/tdx.c | 12
4 files changed, 37 insertions(+)
diff --git a
KVM has a weird behaviour when a guest executes VMCALL on an AMD system
or VMMCALL on an Intel CPU. Both naturally generate an invalid opcode
exception (#UD) as they are just the wrong instruction for the CPU
given. But instead of forwarding the exception to the guest, KVM tries
to patch the guest
On Mon, Jun 16, 2025 at 2:51 PM Fiona Ebner wrote:
>
> Am 16.06.25 um 11:34 schrieb Ilya Dryomov:
> > On Thu, May 15, 2025 at 1:29 PM Fiona Ebner wrote:
> >>
> >> In Proxmox VE, it is not always required to have a dedicated Ceph
> >> configuration file, and using the 'key-secret' QAPI option woul
On Mon, Jun 16, 2025 at 2:38 PM Fiona Ebner wrote:
>
> Am 16.06.25 um 12:28 schrieb Ilya Dryomov:
> > On Mon, Jun 16, 2025 at 11:52 AM Daniel P. Berrangé
> > wrote:
> >> On Mon, Jun 16, 2025 at 11:25:54AM +0200, Ilya Dryomov wrote:
> >>> On Thu, May 15, 2025 at 1:29 PM Fiona Ebner wrote:
>
Hi Eric,
On 6/17/25 10:22, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
The comment about the mapping from SMMU to ITS is incorrect and it reads
"RC -> ITS". The code in question actually maps SMMU -> ITS, so the
mapping in question is not direct. The direct mapping,
I've updated this patch to address some notes about the build/test
configuration for the patch plugin. Please check
https://lore.kernel.org/qemu-devel/20250619161547.1401448-1-rowanbh...@gmail.com/T/#t
instead.
On 6/11/25 4:24 PM, Rowan Hart wrote:
This patch series adds several new API funct
This patch series adds several new API functions focused on enabling use
cases around reading and writing guest memory from QEMU plugins. To support
these new APIs, some utility functionality around retrieving information about
address spaces is added as well.
The new qemu_plugin_write_register ut
From: novafacing
This patch updates the plugin version to gate new APIs and adds notes
describing what has been added.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rowan Hart
---
include/qemu/qemu-plugin.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/qem
This patch adds functionality to enforce the requested QEMU_PLUGIN_CB_
flags level passed when registering a callback function using the
plugins API. Each time a callback is about to be invoked, a thread-local
variable will be updated with the level that callback requested. Then,
called API functio
From: novafacing
This patch adds functions to the plugins API to allow plugins to read
and write memory via hardware addresses. The functions use the current
address space of the current CPU in order to avoid exposing address
space information to users. A later patch may want to add a function to
From: novafacing
This patch exposes the gdb_write_register function from
gdbstub/gdbstub.c via the exec/gdbstub.h header file to support use in
plugins to write register contents.
Reviewed-by: Alex Bennée
Reviewed-by: Julian Ganz
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rowan Hart
---
g
From: novafacing
This patch adds a plugin that exercises the virtual and hardware memory
read-write API functions added in a previous patch. The plugin takes a
target and patch byte sequence, and will overwrite any instruction
matching the target byte sequence with the patch.
Signed-off-by: Rowa
From: novafacing
This patch adds functions to the plugins API to allow reading and
writing memory via virtual addresses. These functions only permit doing
so on the current CPU, because there is no way to ensure consistency if
plugins are allowed to read or write to other CPUs that aren't current
From: novafacing
This patch adds a function to the plugins API to allow plugins to write
register contents. It also moves the qemu_plugin_read_register function
so all the register-related functions are grouped together in the file.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rowan Hart
---
Eric Auger writes:
> Hi,
>
> On 6/17/25 5:50 PM, Miguel Luis wrote:
>> Hi Eric,
>>
>>> On 17 Jun 2025, at 15:41, Eric Auger wrote:
>>>
>>>
>>>
>>> On 6/17/25 5:23 PM, Miguel Luis wrote:
Hi Alyssa,
> On 17 Jun 2025, at 14:17, Alyssa Ross wrote:
>
> Eric Auger writes:
>
On 13/06/2025 16:32, Roy Hopkins wrote:
IGVM files can contain an initial VMSA that should be applied to each
vcpu as part of the initial guest state. The sev_features flags are
provided as part of the VMSA structure. However, KVM only allows
sev_features to be set during initialization and no
On 6/19/25 17:14, Patrick Williams wrote:
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some cases I substituted devices that are close enough
for present functionality. Strap registers are
Hi Xuemei Liu,
Thank you for the patch!
On Thu, Jun 19, 2025 at 03:56:26PM +0800, liu.xuem...@zte.com.cn wrote:
> From: Xuemei Liu
>
> This adds powerdown support by implementing the ACPI GED.
>
> Signed-off-by: Xuemei Liu
> Co-authored-by: Björn Töpel
> ---
> hw/riscv/Kconfig |
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command t
From: Shiju Jose
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The subclasses
for this operation vary in terms of the scope of the sparing being
performed. The Cacheline sparing subclass refers to a sparing a
From: Shiju Jose
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with Maintenance Operation Subclass, LD ID and
ID of the device head information.
Add updates for the above spec changes in the related CXL events
reporting and QMP command to inject CXL events.
S
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error C
From: Davidlohr Bueso
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the reque
From: Shiju Jose
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature()
to the local scope where they are used.
Signed-off-by: Shiju Jose
---
hw/cxl/cxl-mailbox-utils.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/cxl/cxl
From: Shiju Jose
Add updates for the CXL spec rev3.2 changes, in the CXL events reporting
and QMP command to inject CXL events.
Add maintenance support and emulation support for memory Post Package
Repair(PPR) and memory sparing control features.
Davidlohr Bueso (1):
hw/cxl: Add Maintenance s
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
Add updates for the above spe
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some cases I substituted devices that are close enough
for present functionality. Strap registers are were verified with
hardware.
This has been
Hi,
On Thu, Jun 19, 2025 at 5:24 PM Cédric Le Goater wrote:
>
> Hi,
>
> This is a follow up of a private discussion with Patrick.
>
> Aspeed modeling started nearly 10y ago with the palmetto-bmc machine.
> We now have 5 SoCs and 25 machines which are mostly defined in
> in a single aspeed.c file.
This is a linux header update against v6.16-rc2 (e04c78d86a96),
especially targeted to get nested virt enablement.
Signed-off-by: Eric Auger
---
include/standard-headers/asm-x86/setup_data.h | 13 +-
include/standard-headers/drm/drm_fourcc.h | 45 +++
include/standard-headers/linux/eth
From: Haibo Xu
Introduce query support for KVM_CAP_ARM_EL2.
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
Signed-off-by: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/kvm_arm.h | 7 +++
target/arm/kvm-stub.c | 5 +
target/arm/kvm
From: Haibo Xu
Allow virt arm machine to set the interrupt ID for the KVM
GIC maintenance interrupt.
This setting must be done before the KVM_DEV_ARM_VGIC_CTRL_INIT
hence the choice to perform the setting in the GICv3 realize
instead of proceeding the same way as kvm_arm_pmu_set_irq().
Signed-o
From: Haibo Xu
KVM_CAP_ARM_EL2 must be supported by the cpu to enable ARM_FEATURE_EL2.
In case the host does support NV, expose the feature.
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
Signed-off-by: Eric Auger
Reviewed-by: Richard Henderson
---
v2 -> v3:
- check pmu->has_el2 on kvm_
The only change compared to v5 is the linux header update against
kvm main branch. As discussed on the mailing list, KVM_ARM_VCPU_EL2_E2H0
(non VHE version of the NV support) will be dealt with in a separate
add-on series. Also the fallback to TCG does not apply if the host
does not support nested
From: Haibo Xu
Up to now virt support on guest has been only supported with TCG.
Now it becomes feasible to use it with KVM acceleration.
Also check only in-kernel GICv3 is used along with KVM EL2.
Signed-off-by: Haibo Xu
Signed-off-by: Miguel Luis
Signed-off-by: Eric Auger
Reviewed-by: Rich
On Thu, 19 Jun 2025 at 14:23, Philippe Mathieu-Daudé wrote:
>
> On Thu, 19 Jun 2025 at 15:15, Philippe Mathieu-Daudé
> wrote:
> >
> > fetch_firmware() is only about fetching firmware.
> > Set the machine type in test_sbsaref_edk2_firmware().
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
On Thu, Jun 19, 2025 at 11:06:46AM +0800, Chenyi Qiang wrote:
> To fix the build error with --enable-docs configuration, Add the below fixup
Thanks, this works for me.
Though I just noticed it has more than the doc issue.. please see:
https://gitlab.com/peterx/qemu/-/jobs/10403528070
So 6 failu
This is based on version v0.8.3 of the ZALASR specification [1].
The specification is listed as in Frozen state [2].
[1]: https://github.com/riscv/riscv-zalasr/tree/v0.8.3
[2]:
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
Signe
Add new message to send multiple writes to server in a single message.
Prevents the outgoing queue from overflowing when a long latency
operation is followed by a series of posted writes.
Originally-by: John Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by:
IRQ setup uses the same semantics as the traditional vfio path, but we
need to share the corresponding file descriptors with the server as
necessary.
Originally-by: John Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by: John Levon
---
hw/vfio-user/protocol
Hook this call up to the legacy reset handler for vfio-user-pci.
Originally-by: John Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by: John Levon
---
hw/vfio-user/device.h | 2 ++
hw/vfio-user/device.c | 12
hw/vfio-user/pci.c| 15 +++
On Thu, 19 Jun 2025 at 14:15, Philippe Mathieu-Daudé wrote:
>
> Define RAMLIMIT_BYTES using the TiB definition and display
> the error parsed with size_to_str():
>
> $ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T
> qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of RAM
>
By default, the vfio-user subsystem will wait 5 seconds for a message
reply from the server. Add an option to allow this to be configurable.
Originally-by: John Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by: John Levon
---
hw/vfio-user/proxy.h | 1 +
hw
1 - 100 of 181 matches
Mail list logo
