On 6/19/25 05:58, Patrick Williams wrote:
Update the Bletchley hardware strap register values
per actual hardware:
```
root@bmc:~# devmem 0x1e6e2500
0x2000
root@bmc:~# devmem 0x1e6e2510
0x0801
```
Signed-off-by: Patrick Williams
---
hw/arm/aspeed.c | 5 ++---
1 file changed, 2 insert
From: Kane-Chen-AS
This patch exposes a new "otpmem" machine parameter to allow users to
attach an OTP memory device to AST1030 and AST2600-based platforms.
The value of this parameter is passed as a QOM alias to the Secure Boot
Controller (SBC), enabling binding to an aspeed.otpmem device creat
From: Kane-Chen-AS
Introduce a functional test suite to validate the ASPEED OTP memory
device integration under different machine configurations.
The following cases are covered:
- AST2600 with blockdev + device + machine parameter (full binding)
- AST2600 fallback with no machine parameter
- AS
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage or boot-time configuration. The OTP memory can operate
with either:
- a file-backed backend via the 'drive' property,
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoCs (AST2600, AST1030).
The OTP model emulates a simple fuse array used for secure boot or
device config
v2 changes: Addresses comments by Peter. For each device: - Switched soc
to use sysbus_realize - Standardized switch case bracing, indentation, and
error case - Added valid min and max access size - Changed endianness to
DEVICE_LITTLE_ENDIAN - Added reset method, if not already implemented -
Added
Hello Patrick,
On 6/19/25 05:43, Patrick Williams wrote:
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some cases I substituted devices that are close enough
for present functionality. Stra
This patch adds support for the MAX78000FTHR machine.
The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch
implements only the MAX78000, which is Cortex-M4 based.
Details can be found at:
https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf
Sig
This commit implements the Global Control Register
for the MAX78000
Signed-off-by: Jackson Donaldson
---
hw/arm/Kconfig | 1 +
hw/misc/Kconfig| 3 +
hw/misc/max78000_gcr.c | 339 +
hw/misc/meson.build| 1 +
This commit adds TRNG to max78000_soc
Signed-off-by: Jackson Donaldson
---
hw/arm/max78000_soc.c | 10 +-
include/hw/arm/max78000_soc.h | 2 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c
index 1a36bba2fc..09667b578
This commit implements the True Random Number
Generator for the MAX78000
Signed-off-by: Jackson Donaldson
---
hw/arm/Kconfig | 1 +
hw/misc/Kconfig | 3 +
hw/misc/max78000_gcr.c | 6 ++
hw/misc/max78000_trng.c | 127
This commit implements AES for the MAX78000
Signed-off-by: Jackson Donaldson
---
hw/arm/Kconfig | 1 +
hw/misc/Kconfig| 3 +
hw/misc/max78000_aes.c | 232 +
hw/misc/max78000_gcr.c | 6 +
hw/misc/meson.build
This commit adds UART to max78000_soc
Signed-off-by: Jackson Donaldson
---
hw/arm/max78000_soc.c | 28
include/hw/arm/max78000_soc.h | 3 +++
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c
index
This commit implements the Instruction Cache Controller
for the MAX78000
Signed-off-by: Jackson Donaldson
---
hw/arm/Kconfig | 1 +
hw/misc/Kconfig| 3 +
hw/misc/max78000_icc.c | 120 +
hw/misc/meson.build|
This commit adds the instruction cache controller
to max78000_soc
Signed-off-by: Jackson Donaldson
---
hw/arm/max78000_soc.c | 19 +++
include/hw/arm/max78000_soc.h | 6 ++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/hw/arm/max78000_soc.c b/hw/arm
This commit adds AES to max78000_soc
Signed-off-by: Jackson Donaldson
---
hw/arm/max78000_soc.c | 12 +---
include/hw/arm/max78000_soc.h | 2 ++
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c
index 09667b578c..f6d599
This commit adds the Global Control Register to
max78000_soc
Signed-off-by: Jackson Donaldson
---
hw/arm/max78000_soc.c | 21 +++--
include/hw/arm/max78000_soc.h | 2 ++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/arm/max78000_soc.c b/hw/arm/max780
> A minor note on email patchseries formatting: something odd
> seems to have happened with your cover letter. Patches in a
> series are supposed to be followups to the cover letter, but
> in this case each patch email has a header
> In-reply-to: 20250510042043.2056265-1-jc...@duck.com
> but tha
This commit implements UART support for the MAX78000
Signed-off-by: Jackson Donaldson
---
hw/arm/Kconfig | 1 +
hw/char/Kconfig | 3 +
hw/char/max78000_uart.c | 285
hw/char/meson.build | 1 +
include/hw/
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some cases I substituted devices that are close enough
for present functionality. Strap registers are were verified with
hardware.
This has been
Update the Bletchley hardware strap register values
per actual hardware:
```
root@bmc:~# devmem 0x1e6e2500
0x2000
root@bmc:~# devmem 0x1e6e2510
0x0801
```
Signed-off-by: Patrick Williams
---
hw/arm/aspeed.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/arm/a
when loongarch cpu set irq is INT_AVEC, we need set CSR_ECFG MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 5 +++--
target/loongarch/cpu.c | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
inde
On 6/19/2025 6:22 AM, Peter Xu wrote:
> On Thu, Jun 12, 2025 at 04:27:41PM +0800, Chenyi Qiang wrote:
>> This is the v7 series of the shared device assignment support.
>
> Building doc fails, see:
>
> https://gitlab.com/peterx/qemu/-/jobs/10396029551
>
> You should be able to reproduce with
On 6/12/2025 4:27 PM, Chenyi Qiang wrote:
> Update ReplayRamDiscard() function to return the result and unify the
> ReplayRamPopulate() and ReplayRamDiscard() to ReplayRamDiscardState() at
> the same time due to their identical definitions. This unification
> simplifies related structures, such
LoongArchVirtMachinState add avecintc features, and
it use to check whether virt machine support advance interrupt controller
and default set avecintc = ON_OFF_AUTO_ON.
LoongArchVirtMachineState add misc_feature and misc_status for
misc fetures and status. and set default avec feture bit.
Signed-
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 1 +
target/loongarch/cpu.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 0834e91f
the AVEC controller supports 256*256 irqs input, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 21 +
hw/loongarch/virt.c | 11 +--
target/loongarch/cpu.h | 3 ++-
3 files changed, 32 insertions(+), 3 deletions(-)
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 7 +++
target/loongarch/cpu.h | 10 ++
target/loongarch/machine.c | 5 +
3 files changed, 22 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
i
move som machine define to virt.h and define avec feature and status bit.
Use the IOCSRF_AVEC bit for avdance interrupt controller drivers
avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit
IOCSRM_AVEC_EN.
and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN.
[1]:h
the AVEC controller use [2fe0-2ff00) Memory.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 25
hw/loongarch/virt.c | 39 +++-
include/hw/intc/loongarch_avec.h | 1 +
include/hw/loongarch/virt.h | 1 +
i
Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index 7dd8bac696..bbd1b48c7d 100
ntroduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is
Add Loongarch advance interrupt controller device base Definition.
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 ++
hw/intc/loongarch_avec.c | 68
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1 +
incl
It will be better if check_vldi_mode() is renamed as
check_valid_vldi_mode().
Reviewed-by: Bibo Mao
On 2025/6/18 下午3:49, gaosong wrote:
Ping ! :-)
在 2025/6/5 上午9:53, Song Gao 写道:
on qemu we got an aborted error
**
ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value:
Hi Gandalf,
On 5/7/25 8:39 AM, GanDalf LeBron wrote:
Hi there!
I am writing to inquire about the current implementation status of
Secure SMMU features in QEMU.
I understand that non-secure SMMU emulation for general peripheral DMA
(IOVA to PA translation and protection managed by the Norma
On Thu, Jun 12, 2025 at 04:27:41PM +0800, Chenyi Qiang wrote:
> This is the v7 series of the shared device assignment support.
Building doc fails, see:
https://gitlab.com/peterx/qemu/-/jobs/10396029551
You should be able to reproduce with --enable-docs. I think you need to
follow the rest wit
Hi, Chenyi,
On Thu, Jun 12, 2025 at 04:27:41PM +0800, Chenyi Qiang wrote:
> Relationship with in-place conversion
> -
> In-place page conversion is the ongoing work to allow mmap() of
> guest_memfd to userspace so that both private and shared memory can use
> th
Hi,
On Wed, Jun 18, 2025 at 4:22 PM Daniel Henrique Barboza
wrote:
> > +if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0) ||
> > +(cpu->cfg.rvv_vsetvl_x0_vill && x0 && (env->vl != vl))) {
>
> In this particular case I don't mind replicating code. The first existing
Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
and rd arguments are x0.
In this case, if the new property is true, only the vill bit will be set.
See
https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding
According to the spec, the above
Clang 20.1.6 (Fedora 20.1.6-1.fc42)'s UBSAN complains:
qemu/include/tcg/tcg.h:715:19: runtime error: applying non-zero offset 64
to null pointer
The code uses NULL as pool's initial start and end, with the intention
that `pool_cur + size > pool_end` should trigger the allocation.
Unfortunate
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z. Ex: Use 4 cores and 2 threads with e
(CCing Michael and Marcel)
For better visibility I suggest copying the maintainers of hw/pci/pci.c when
submitting this patch in the next version:
$ ./scripts/get_maintainer.pl -f hw/pci/pci.c
"Michael S. Tsirkin" (supporter:PCI)
Marcel Apfelbaum (supporter:PCI)
qemu-devel@nongnu.org (open lis
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 +++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 219
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
Il mer 18 giu 2025, 16:25 Markus Armbruster ha scritto:
> I don't know enough about Rust/serde to give advice. I do know how to
> make a fool of myself by asking dumb questions.
>
No dumb questions, only dumb answers.
> For commands this is not a problem because the real underlying
> > transfo
Hi Shameer, Jonathan,
On 6/18/25 10:35 AM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Jonathan Cameron
>> Sent: Tuesday, June 17, 2025 5:53 PM
>> To: Eric Auger
>> Cc: Shameerali Kolothum Thodi
>> ; Linuxarm
>> ; qemu-...@nongnu.org; qemu-
>> de...@nongnu.org; pete
On 13/06/2025 16:22, Roy Hopkins wrote:
Adds a handler for the guest policy initialization IGVM section and
builds an SEV policy based on this information and the ID block
directive if present. The policy is applied using by calling
'set_guest_policy()' on the ConfidentialGuestSupport object.
Thanks for your service!
Remove the old qapidoc and the option to enable the transmogrifier,
leaving the "transmogrifier" as the ONLY qapi doc generator. This in
effect also converts the QAPI test to use the new documentation
generator, too.
Update doc-good.txt output to match the new doc generat
Oversight in the new qapidoc transmogrifier: @references in freeform
documentation blocks were not being transformed to literals. This fixes
that, and the next patch ensures that we're testing for this O:-)
Signed-off-by: John Snow
---
docs/sphinx/qapidoc.py | 10 +++---
1 file changed, 7 in
Signed-off-by: John Snow
---
docs/sphinx/qapidoc.py | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc.py
index 8011ac9efaf..5374dee8fad 100644
--- a/docs/sphinx/qapidoc.py
+++ b/docs/sphinx/qapidoc.py
@@ -267,10 +267,14 @
This change removes special parsing for freeform sections and allows
them to simply be unmodified rST syntax. The existing headings in the
QAPI schema are adjusted to reflect the new paradigm.
Tests and documentation are updated to match.
Signed-off-by: John Snow
---
docs/devel/qapi-code-gen.rs
Remove docs/sphinx/qapidoc_legacy.py, and remove special parsing of
freeform QAPI documentation block sections in favor of using standard
rST syntax that is included in the final document with no special
parsing or post-processing.
v3:
- Fixed indentation for :error: in qapidoc
- Removed parser
Signed-off-by: John Snow
---
scripts/qapi/parser.py | 4
tests/qapi-schema/doc-bad-section.err | 1 -
tests/qapi-schema/doc-bad-section.json | 10 --
tests/qapi-schema/doc-bad-section.out | 0
tests/qapi-schema/meson.build | 1 -
5 files changed, 16 del
> Please fix the word wrap on the commit at 78 chars.
I will send v2 with this fix
> stray newline
In tracetool/backend, every function is followed by two newline characters.
On Wed, Jun 18, 2025 at 4:12 AM Alex Bennée wrote:
> Tanish Desai writes:
>
> > This patch separates the generation logi
This patch continues the effort to decouple the generic vhost layer
from specific network backend implementations.
Previously, the vhost_net initialization code contained a hardcoded
check for the vhost-user client type to retrieve its acked features
by calling vhost_user_get_acked_features(). Thi
Previously, the vhost_net_get_feature_bits() function in
hw/net/vhost_net.c used a large switch statement to determine
the appropriate feature bits based on the NetClientDriver type.
This created unnecessary coupling between the generic vhost layer
and specific network backends (like TAP, vhost-us
The code to set the link status is currently located in
qmp_set_link(). This function identifies the device by name,
searches for the corresponding NetClientState, and then updates
the link status.
In some parts of the code, such as vhost-user.c, the
NetClientState are already available. Calling q
This patch completes the series of refactorings aimed at decoupling the
generic vhost layer from specific network backends.
The final remaining dependency was in vhost_net_save_acked_features,
which contained a hardcoded check for the vhost-user client type.
This commit applies the now-establishe
This commit introduces support for passt as a new network backend.
passt is an unprivileged, user-mode networking solution that provides
connectivity for virtual machines by launching an external helper process.
The implementation reuses the generic stream data handling logic. It
launches the pass
This series introduces support for passt as a new network backend for
QEMU.
passt is a modern, unprivileged, user-mode networking solution that
provides guest connectivity by launching an external helper process. This
series adds the core backend and integrates it with vhost-user for
high-performa
To prepare for the implementation of '-net passt', this patch moves
the generic stream handling functions from net/stream.c into new
net/stream_data.c and net/stream_data.h files.
This refactoring introduces a NetStreamData struct that encapsulates
the generic fields and logic previously in NetStr
Currently, several parts of the codebase check if a network client is a
vhost-user backend by directly comparing its type against the
NET_CLIENT_DRIVER_VHOST_USER enum. This creates a tight coupling
between virtio/vhost-net drivers and the internal implementation
details of the vhost-user net clien
This commit adds support for the vhost-user interface to the passt
network backend, enabling high-performance, accelerated networking for
guests using passt.
The passt backend can now operate in a vhost-user mode, where it
communicates with the guest's virtio-net device over a socket pair
using th
The get_vhost_net() function previously contained a large switch
statement to find the VHostNetState pointer based on the net
client's type. This created a tight coupling, requiring the generic
vhost layer to be aware of every specific backend that supported
vhost, such as tap, vhost-user, and vhos
This commit refactors how the maximum transmit queue size for
virtio-net devices is determined, making the mechanism more generic
and extensible.
Previously, virtio_net_max_tx_queue_size() contained hardcoded
checks for specific network backend types (vhost-user and
vhost-vdpa) to determine their
On 6/18/25 1:57 AM, Markus Armbruster wrote:
> Zhuoying Cai writes:
>
>> On 6/17/25 6:58 AM, Markus Armbruster wrote:
>>> Zhuoying Cai writes:
>>>
Add helper functions for x509 certificate which will be used in the next
patch for the certificate store.
Signed-off-by: Zhuoying
On 6/18/25 10:00, Jamin Lin wrote:
According to the datasheet:
BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter.
BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished.
Firmware polls BIT[6] to determine when measurement is complete.
The flag can be cleared by w
On 6/18/25 10:00, Jamin Lin wrote:
On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate
that DDR training has completed, thus skipping the dram_init().
To align with the recent U-Boot changes, where the Main Control Register's
BIT16 is checked to skip the dram_init() process,
I don't know enough about Rust/serde to give advice. I do know how to
make a fool of myself by asking dumb questions.
Paolo Bonzini writes:
> On Wed, Jun 11, 2025 at 10:57 AM Paolo Bonzini wrote:
>> Yes. If using serde the implementation of the traits is very small,
>> and basically the same f
Hi,
Thanks for putting this into a patch. A comment below:
On 6/18/25 4:25 AM, Vasilis Liaskovitis wrote:
Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
and rd arguments are x0.
In this case, if the new property is true, only the vill bit will be set.
See
https
Hi,
This lacks a MAINTAINER.
Ah, right. I can add that in v2. I can add myself to it, is there
anyone else who should be on it?
Would any of your colleagues be interested too ?
Could you please provide functional tests ? some with a standard I2C
device attached to an I3C legacy bus too.
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 14 ++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..1e62b96094 1
Several things implemented in v3:
- Addressing review comments
- Added documentation
- Referenced MIPS Specification
- Split e1000e and pci changes into separate patches
- Rebase on top of master branch
Djordje Todorovic (10):
hw/intc: Allow gaps in hartids for aclint and aplic
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 +++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 219 +++
4 files changed,
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.h | 4
target/riscv/translate.c | 8
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.h b/target
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z. Ex: Use 4 cores and 2 threads with each core to
have 8 smp cpus as follows.
qemu-sys
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/risc
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans/trans_xmips.c.in
Since there is no pch_gbe emulation, we could be using func other
than 0 when adding new devices to specific boards.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pci.c b/h
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 27 +
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 3 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans/trans_x
On 6/18/25 03:35, Ilya Leoshkevich wrote:
Clang 20.1.6 (Fedora 20.1.6-1.fc42)'s UBSAN complains:
qemu/include/tcg/tcg.h:715:19: runtime error: applying non-zero offset 64
to null pointer
The code uses NULL as pool's initial start and end, with the intention
that `pool_cur + size > pool_en
On Wed, 2025-06-18 at 12:35 +0200, Ilya Leoshkevich wrote:
> Clang 20.1.6 (Fedora 20.1.6-1.fc42)'s UBSAN complains:
>
> qemu/include/tcg/tcg.h:715:19: runtime error: applying non-zero
> offset 64 to null pointer
>
> The code uses NULL as pool's initial start and end, with the
> intention
> th
On Wed, Jun 18, 2025 at 11:40:38AM +0800, Yi Liu wrote:
> Actually, as I explained in the first hunk of [1], there is no issue with
> the legacy mode support. :)
>
> [1]
> https://lore.kernel.org/qemu-devel/2025052452.3316354-1-zhenzhong.d...@intel.com/T/#m4c8fa70742001d4c22b3c297e240a2151d2
> >> +/* Assert PERST involves physical port to be in
> >wrap at 80 chars.
> okay
> >> + * hold reset phase for minimum 100ms. No other calls
> >> + * are entertained until Deassert PERST command.
> >> + *
> >> https://patchwork.ozlabs.org/project/linux-pci/patc
By definition an isapc machine must always use ISA IDE drives so ensure that
they
are always enabled. At the same time also remove the surrounding CONFIG_IDE_ISA
define since it will be enabled via the ISAPC Kconfig.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 35 +++
These are based upon the PIIX4 PCI chipset and so can never be used on an isapc
machine.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 102e785d27..2ce3a3463f 100644
--- a/
> >> +#define LINK_STATE_FLAG_PERST_ASSERTED (1 << 1)
> >> +#define LINK_STATE_FLAG_PRSNT(1 << 2)
> >> +#define LINK_STATE_FLAG_POWER_OFF(1 << 3)
> >> +
> >> +/* physical port control info - CXL r3.2 table 7-19 */
> >> +typedef enum {
> >> +PORT_DISABLED = 0,
> >> +B
This is to prepare for splitting the isapc machine into its own separate file.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 260 +-
1 file changed, 259 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ea
For various historical reasons the initialisation of the isapc machine is
closely
intertwined with the initialisation of the pc machine, which is preventing some
future improvements to the pc machine initialisation logic.
Since the consensus [1] was that the isapc is still useful for testing and
By definition PCI can never be enabled on an isapc machine so hardcode the
relevant values
set via pcmc->pci_enabled.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 03bd09f
This code will never be used for an isapc machine.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 105 --
1 file changed, 8 insertions(+), 97 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 9842d2152b..102e785d27 100644
Now that pc_init_isa() is independent of any PCI initialisation, move it into a
separate isapc.c file. This enables us to finally fix the dependency of ISAPC on
I440FX in hw/i386/Kconfig.
Note that as part of the move to a separate file we can see that the licence
text
is a verbatim copy of the M
All isapc machines must have 32-bit CPUs and have no PCI 64-bit hole so it can
be
hardcoded to 0.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 168469457e..cd9a89f7ff 100644
By definition PCI can never be enabled on an isapc machine so hardcode the
PCIBus argument
of pc_nic_init() to NULL.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 279eab10ce..
All isapc machines must have 32-bit CPUs and so the RAM split logic can be
hardcoded
accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 58 ---
1 file changed, 4 insertions(+), 54 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i38
This function contains 'assert(PC_MACHINE_GET_CLASS(pcms)->pci_enabled)' and so
we can
safely assume that it should never be used for the isapc machine.
Signed-off-by: Mark Cave-Ayland
---
hw/i386/pc_piix.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
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