On 2025-06-17 19:09, Nina Schoetterl-Glausch wrote:
On Mon, 2025-06-16 at 16:01 +0200, Shalini Chellathurai Saroja wrote:
Add Control-Program Identification (CPI) data to the QEMU Object
Model (QOM), along with the timestamp in which the data was received
as shown below.
virsh # qemu-monitor-co
This patchset is small code cleanup with LoongArch TLB emulation.
LoongArch does not support hardware page table walker, TLB handling
is complicated compared with common architectures.
Bibo Mao (3):
target/loongarch: Correct spelling in helper_csrwr_pwcl()
target/loongarch: Fix CSR STLBPS regi
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register
write operation. However there is only parameter checking action, and
no register updating action. Here update value of CSR_STLBPS when
parameter passes to check.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/csr_helper.c |
Page size of TLB entry comes from CSR STLBPS and pwcl register. With
huge page, it is dir_base + dir_width from pwcl register. With normal
page, it is field of PTBASE from pwcl register.
So it is ok to check validity in function helper_ldpte() and function
helper_csrwr_stlbps(). And it is unnecess
There is small typo issue in function helper_csrwr_pwcl(), this patch
corrects this issue.
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/csr_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/csr_helper.c
b/target/loongarch/tcg/csr_helper.c
John Snow writes:
> On Mon, Jun 16, 2025 at 8:20 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Thanks for your service!
>> >
>> > Remove the old qapidoc and the option to enable the transmogrifier,
>> > leaving the "transmogrifier" as the ONLY qapi doc generator. This in
>> > effec
In the cases where mixed DMA/non-DMA transfers are used or no data is
available, it is possible to for the calculated transfer length to be
zero. Only call the dma_memory_read function where the transfer length
is non-zero to avoid invoking the DMA engine for a zero length transfer
which can have s
If an ESP command is issued in an incorrect mode then an illegal command
interrupt should be generated. Add a new esp_cmd_is_valid() function to
indicate whether the ESP command is valid for the current mode, and if not
then raise the illegal command interrupt.
This fixes WinNT MIPS which issues I
In the cases where mixed DMA/non-DMA transfers are used or no data is
available, it is possible to for the calculated transfer length to be
zero. Only call the dma_memory_write function where the transfer length
is non-zero to avoid invoking the DMA engine for a zero length transfer
which can have
Add a new asc_mode property to ESPState which indicates the current mode of
the ESP and update the ESP state machine accordingly.
Bump the vmstate version and include migration logic to ensure that asc_mode
is set to initiator mode such that any commands in progress will always
continue.
Signed-o
Clarify the logic in esp_transfer_data() to ensure that the deferred interrupt
code
can only be triggered for CMD_SEL, CMD_SELATN and CMD_TI commands. This should
already
be the case, but make it explicit to ensure the logic isn't triggered
unexpectedly.
Signed-off-by: Mark Cave-Ayland
---
hw
This series contains a few minor tidy-ups along with an implementation of the
logic to only allow ESP commands permitted in the current mode. The motivation
is to fix GitLab issue #2464 which causes Windows NT MIPS to bluescreen on
boot.
Patches 1 to 5 are simple tidy-ups from investigating the is
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v1 06/15] intel_iommu: Handle PASID entry removing and
>updating
>
>On 2025/6/6 18:04, Zhenzhong Duan wrote:
>> This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the
>> pasid entry and track PASID usage and fut
Zhuoying Cai writes:
> On 6/17/25 6:58 AM, Markus Armbruster wrote:
>> Zhuoying Cai writes:
>>
>>> Add helper functions for x509 certificate which will be used in the next
>>> patch for the certificate store.
>>>
>>> Signed-off-by: Zhuoying Cai
[...]
>> Ignorant question: why are these QAPI
Hi Takashi,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.16-rc2 next-20250617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
在 2025/6/17 下午3:34, Bibo Mao 写道:
hi,
here is pch_msi [start-256] gpio_out connect to avec gpio_in
[start, 256], not the avec connect to cpu.
pch_msi is always connected to eiointc, and it is not connected to
avec gpio_in. There is two MSI controllers coexisting together:
pch_msi and avec,
On 2025/6/17 21:11, Jason Gunthorpe wrote:
On Tue, Jun 17, 2025 at 09:03:32PM +0800, Yi Liu wrote:
I suggest fixing the Linux driver to refuse to run in sm_on mode if
the HW supports scalable mode and ecap_slts = false. That may not be
100% spec compliant but it seems like a reasonable approach.
>-Original Message-
>From: Jason Gunthorpe
>Subject: Re: [PATCH rfcv3 15/21] intel_iommu: Bind/unbind guest page table to
>host
>
>On Tue, Jun 17, 2025 at 09:03:32PM +0800, Yi Liu wrote:
>> > I suggest fixing the Linux driver to refuse to run in sm_on mode if
>> > the HW supports scalab
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v1 03/15] intel_iommu: Check for compatibility with
>IOMMUFD backed device when x-flts=on
>
>Hi Zhenzhong,
>
>On 6/6/25 12:04 PM, Zhenzhong Duan wrote:
>> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
>
On 6/16/25 13:10, Alex Bennée wrote:
If the user writes a large value to the register but with the bottom
bits unset we could end up with something illegal. By clamping ahead
of the check we at least assure we won't assert(bpr > 0) later in the
GIC interface code.
Signed-off-by: Alex Bennée
---
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH v1 02/15] intel_iommu: Optimize context entry cache
>utilization
>
>Hi Zhenzhong,
>
>On 6/6/25 12:04 PM, Zhenzhong Duan wrote:
>> There are many call sites referencing context entry by calling
>> vtd_dev_to_context_entry(
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v1 02/15] intel_iommu: Optimize context entry cache
>utilization
>
>On 2025/6/11 18:06, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Liu, Yi L
>>> Subject: Re: [PATCH v1 02/15] intel_iommu: Optimize conte
On 6/16/25 10:15, Solomon Tan wrote:
According to the Arm A-profile A64 Instruction Set Architecture,
RETA[AB] should be decoded as UNDEF if the pauth feature is not
implemented.
Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to
decodetree")
Signed-off-by: Solomon Tan
-
On 6/15/25 22:09, Philippe Mathieu-Daudé wrote:
Hi Solomon,
Cc'ing the qemu-arm@ list.
On 14/6/25 06:51, r...@wjsota.com wrote:
Hi!
Is `qemu-aarch64 -cpu neoverse-n1` supposed to emulate the `retaa` instruction?
I have a binary called `main_pac` compiled from https://learn.arm.com/learning-p
Hi,
On Sun, Jun 15, 2025 at 11:49 PM Cédric Le Goater wrote:
>
> Hi
>
> + Jeremy
>
> On 6/13/25 02:03, Joe Komlodi wrote:
> > Hi all,
> >
> > This series adds I3C bus support to QEMU and adds more functionality to the
> > Aspeed I3C controller.
> >
> > This implementation is a basic implementatio
On Sun, Jun 15, 2025 at 11:42 PM Cédric Le Goater wrote:
>
> On 6/13/25 02:03, Joe Komlodi wrote:
> > Moves the Aspeed I3C model and traces into hw/i3c and creates I3C build
> > files.
> >
> > Signed-off-by: Joe Komlodi
>
>
> Reviewed-by: Cédric Le Goater
>
> > Reviewed-by: Patrick Venture
> >
Tanish Desai writes:
> This patch separates the generation logic of trace_foo() for the UST and
> DTrace backends from other backends.
> The motivation is to remove the unnecessary if (true) in the _no_check
> function, as UST and DTrace do not require a trace_event_get_state check
> without i
The current check incorrectly misses the 0% case, which semantically
can either be not running or one that just started. The runtime
is a better way to check for 0%, 100% or aborted. This is currently
benign in the kernel equivalent without cancel support.
Signed-off-by: Davidlohr Bueso
---
Appl
On 6/17/25 3:03 PM, Daniel Borkmann wrote:
> On 6/17/25 1:59 PM, Ilya Maximets wrote:
>> On 6/4/25 1:29 PM, Daniel Borkmann wrote:
>>> While testing, it turned out that upon error in the queue creation loop,
>>> we never trigger the af_xdp_cleanup() handler. This is because we pass
>>> errp instead
On 6/4/25 5:56 PM, Zhuoying Cai wrote:
> Add documentation for secure IPL
>
> Signed-off-by: Collin Walling
> Signed-off-by: Zhuoying Cai
> ---
> docs/specs/s390x-secure-ipl.rst | 145 +++
> docs/system/s390x/secure-ipl.rst | 129 +++
> 2 fi
When compiling QEMU against fuse3-3.17.1 with --enable-werror the build fails
with:
In file included from ../src/block/export/fuse.c:33:
/usr/include/fuse3/fuse.h:959:5: error: redundant redeclaration of
‘fuse_main_real_versioned’ [-Werror=redundant-decls]
959 | int fuse_main_real_version
On Mon, Jun 16, 2025 at 8:20 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Thanks for your service!
> >
> > Remove the old qapidoc and the option to enable the transmogrifier,
> > leaving the "transmogrifier" as the ONLY qapi doc generator. This in
> > effect also converts the QAPI test
Tanish Desai writes:
> The vcpu property is no longer used in these backends. Removing it avoids
> unnecessary checks and simplifies the code generation for these trace
> backends.
>
> Signed-off-by: Tanish Desai
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
This commit improves the QGA VSS provider installation flow
by attempting to unregister the VSS provider if it's already
found during installation. This allows for a retry of installation
even if a previous unregistration failed or was not performed.
Signed-off-by: Elizabeth Ashurov
---
qga/vss-
On 6/17/25 12:52 PM, Jonathan Cameron wrote:
On Tue, 17 Jun 2025 09:49:54 +0200
Eric Auger wrote:
On 6/16/25 12:20 PM, Jonathan Cameron wrote:
On Fri, 13 Jun 2025 15:44:43 +0100
Shameer Kolothum wrote:
Although this change does not affect functionality at present, it is
Patch title s
On Wed, Jun 04, 2025 at 02:07:14PM +0200, Fiona Ebner wrote:
> Signed-off-by: Fiona Ebner
> ---
> include/block/graph-lock.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Eric Blake
>
> diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h
> index 2c26c72
The vcpu property is no longer used in these backends. Removing it avoids
unnecessary checks and simplifies the code generation for these trace backends.
Signed-off-by: Tanish Desai
---
scripts/tracetool/__init__.py | 6 +++---
scripts/tracetool/backend/log.py| 6 +-
scripts/tracet
Queued, thanks.
Paolo
Queued, thanks.
Paolo
Queued, thanks; sorry about the delay.
Paolo
Hi Zhenzhong,
On 6/6/25 12:04 PM, Zhenzhong Duan wrote:
> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
> is passed to host to construct nested page table. We need to check
> compatibility of some critical IOMMU capabilities between vIOMMU and
> host IOMMU to ensure gues
On 6/17/25 3:24 AM, Alex Bennée wrote:
Rowan Hart writes:
From: novafacing
This patch adds functions to the plugins API to allow plugins to read
and write memory via hardware addresses. The functions use the current
address space of the current CPU in order to avoid exposing address
space in
Hi Zhenzhong,
On 6/6/25 12:04 PM, Zhenzhong Duan wrote:
> There are many call sites referencing context entry by calling
> vtd_dev_to_context_entry() which will traverse the DMAR table.
>
> In most cases we can use cached context entry in vtd_as->context_cache_entry
> except when its entry is stal
Hi Zhenzhong,
On 6/6/25 12:04 PM, Zhenzhong Duan wrote:
> In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry
> of rid2pasid, then it was extended to get any pasid entry. So a new name
> vtd_ce_get_pasid_entry is better to match what it actually does.
>
> No functional change in
On Mon, 2025-06-16 at 16:01 +0200, Shalini Chellathurai Saroja wrote:
> Add Control-Program Identification (CPI) data to the QEMU Object
> Model (QOM), along with the timestamp in which the data was received
> as shown below.
>
> virsh # qemu-monitor-command vm --pretty '{"execute":"qom-list",
> "
On 6/17/25 6:01 PM, Gustavo Romero wrote:
> Hi Eric,
>
> On 6/17/25 12:51, Eric Auger wrote:
>>
>>
>> On 6/17/25 5:12 PM, Gustavo Romero wrote:
>>> Hi Eric,
>>>
>>> On 6/17/25 10:34, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
> From: Philippe Mathi
On Tue, 17 Jun 2025 09:49:54 +0200
Eric Auger wrote:
> On 6/16/25 12:20 PM, Jonathan Cameron wrote:
> > On Fri, 13 Jun 2025 15:44:43 +0100
> > Shameer Kolothum wrote:
> >
> >> Although this change does not affect functionality at present, it is
> > Patch title says PCIe. This check is vs PC
Although we are using structure initialisation the order of the
op[012]/cr[nm] fields don't match the rest of the code base.
Re-organise to be consistent and help the poor engineer who is
grepping for system registers.
Signed-off-by: Alex Bennée
---
target/arm/debug_helper.c | 12 +++-
1
For now just deal with the basic version probe we see during startup.
Signed-off-by: Alex Bennée
---
target/arm/kvm.c| 44 +
target/arm/trace-events | 1 +
2 files changed, 45 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 0
If the user writes a large value to the register but with the bottom
bits unset we could end up with something illegal. By clamping ahead
of the check we at least assure we won't assert(bpr > 0) later in the
GIC interface code.
Signed-off-by: Alex Bennée
---
hw/intc/arm_gicv3_cpuif.c | 5 -
Fortunately all the information about which sysreg is being accessed
should be in the ISS field of the ESR. Once we process that we can
figure out what we need to do.
[AJB: the read/write stuff should probably go into a shared helper].
Signed-off-by: Alex Bennée
---
target/arm/kvm.c| 95
Previously we suppressed this option as KVM would get confused if it
started trapping GIC system registers without a GIC configured.
However if we know we are trapping harder we can allow it much like we
do for HVF.
Signed-off-by: Alex Bennée
---
target/arm/kvm_arm.h | 8
hw/arm/
This allows the vCPU guest core to go to sleep on a WFx instruction.
Signed-off-by: Alex Bennée
---
target/arm/kvm.c| 28
target/arm/trace-events | 1 +
2 files changed, 29 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 1280e2c1e8..63b
Currently we do nothing but report we don't handle anything and let
KVM come to a halt.
Signed-off-by: Alex Bennée
---
target/arm/syndrome.h | 4
target/arm/kvm-stub.c | 5 +
target/arm/kvm.c | 44 +++
3 files changed, 53 insertions(+)
dif
Import headers for trap-me-harder, based on 6.15.1.
Signed-off-by: Alex Bennée
---
include/standard-headers/linux/virtio_pci.h | 1 +
linux-headers/linux/kvm.h | 8
linux-headers/linux/vhost.h | 4 ++--
3 files changed, 11 insertions(+), 2 deletions(-)
Before this we suppress all ARM_CP_NORAW registers being listed under
GDB. This includes useful registers like CurrentEL which gets tagged
as ARM_CP_NO_RAW because it is one of the ARM_CP_SPECIAL_MASK
registers. These are registers TCG can directly compute because we
have the information at compile
It would be nice to only have the variable for this is a KVM_ARM_STATE
but currently everything is just held together in the common KVMState.
Only KVM ARM can set the flag though.
Signed-off-by: Alex Bennée
---
include/system/kvm_int.h | 4
target/arm/kvm.c | 19 +++
Signed-off-by: Alex Bennée
---
target/arm/kvm_arm.h | 9 +
hw/arm/virt.c| 7 +--
target/arm/kvm.c | 7 +++
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 7dc83caed5..a4f68e14cb 100644
--- a/target/arm/k
The following is an RFC to explore how KVM would look if we forwarded
almost all traps back to QEMU to deal with.
Why - won't it be horribly slow?
Maybe, that's why its an RFC.
Traditionally KVM tries to avoid full vmexit's to QEMU because the
additional context
On Tue, Jun 17, 2025, 7:44 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Update the python tests to also check QAPI and the QAPI Sphinx
> > extensions. The docs/sphinx/qapidoc_legacy.py file is not included in
> > these checks, as it is destined for removal soon. mypy is also not
> > cal
From: Eric Auger
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named
Hi Eric,
On 6/17/25 12:51, Eric Auger wrote:
On 6/17/25 5:12 PM, Gustavo Romero wrote:
Hi Eric,
On 6/17/25 10:34, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
From: Philippe Mathieu-Daudé
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
ha
Hi Eric,
> On 17 Jun 2025, at 15:41, Eric Auger wrote:
>
>
>
> On 6/17/25 5:23 PM, Miguel Luis wrote:
>> Hi Alyssa,
>>
>>> On 17 Jun 2025, at 14:17, Alyssa Ross wrote:
>>>
>>> Eric Auger writes:
>>>
From: Haibo Xu
Up to now virt support on guest has been only supported wi
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +-
target/arm/cpu.c | 24 +++
target/arm/cpu.h | 7 --
Hi Eric,
On 6/17/25 12:51, Eric Auger wrote:
On 6/17/25 5:12 PM, Gustavo Romero wrote:
Hi Eric,
On 6/17/25 10:34, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
From: Philippe Mathieu-Daudé
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
ha
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Description: PGP signature
On 6/4/25 1:29 PM, Daniel Borkmann wrote:
> While testing, it turned out that upon error in the queue creation loop,
> we never trigger the af_xdp_cleanup() handler. This is because we pass
> errp instead of a local err pointer into the various AF_XDP setup functions
> instead of a scheme like:
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Description: PGP signature
We have fd, so might as well neaten things up.
Suggested-by: Eric Auger
Reviewed-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/kvm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 3df046b2b911..70919aedd0a4 100
Generated against Linux 6.15.
Reviewed-by: Sebastian Ott
Reviewed-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h.inc | 43 +---
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cp
On 6/4/25 1:29 PM, Daniel Borkmann wrote:
> Extend 'inhibit=on' setting with the option to specify a pinned XSK map
> path along with a starting index (default 0) to push the created XSK
> sockets into. Example usage:
>
> # ./build/qemu-system-x86_64 [...] \
>-netdev
> af-xdp,ifname=enp2s0f
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 74 +++
target/arm/cpu.h | 4 ---
target/arm/cpu64.c| 8 ++---
target/arm/h
On Tue, Jun 17 2025, Cornelia Huck wrote:
> diff --git a/scripts/arm-gen-cpu-sysregs-header.awk
> b/scripts/arm-gen-cpu-sysregs-header.awk
> new file mode 100755
> index ..f92bbbafa727
> --- /dev/null
> +++ b/scripts/arm-gen-cpu-sysregs-header.awk
> @@ -0,0 +1,37 @@
> +#!/bin/awk -f
On Tue, Jun 17, 2025, 5:16 AM Mads Ynddal wrote:
>
> > diff --git a/scripts/simpletrace.py b/scripts/simpletrace.py
> > index cef81b0707f..a013e4402de 100755
> > --- a/scripts/simpletrace.py
> > +++ b/scripts/simpletrace.py
> > @@ -9,13 +9,15 @@
> > #
> > # For help see docs/devel/tracing.rst
> >
On 6/17/25 1:59 PM, Ilya Maximets wrote:
On 6/4/25 1:29 PM, Daniel Borkmann wrote:
Extend 'inhibit=on' setting with the option to specify a pinned XSK map
path along with a starting index (default 0) to push the created XSK
sockets into. Example usage:
# ./build/qemu-system-x86_64 [...] \
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16
target/arm/cpu.c | 13 +
target/arm/cpu.h |
From: Eric Auger
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory generates target/arm/cpu-sysregs.h.inc
containing d
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 44 +++
target/arm/cpu.c | 13
target/arm/cpu.h | 2 --
target
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c| 7 ++-
target/arm/helper.c | 2 +-
target/arm/kvm
On 6/17/25 5:12 PM, Gustavo Romero wrote:
> Hi Eric,
>
> On 6/17/25 10:34, Eric Auger wrote:
>> Hi Gustavo,
>>
>> On 6/16/25 3:18 PM, Gustavo Romero wrote:
>>> From: Philippe Mathieu-Daudé
>>>
>>> Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
>>> hardware introduced in G
Hi Eric,
Thanks a lot for doing a first pass on this series!
On 6/17/25 06:35, Eric Auger wrote:
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
Since v2:
- Fixed no_tcg_its inverted logic (rth)
Since v3:
- Fixed remappings in the IORT table when ITS is no present
- Rebased on master a
On 6/17/25 1:59 PM, Ilya Maximets wrote:
On 6/4/25 1:29 PM, Daniel Borkmann wrote:
While testing, it turned out that upon error in the queue creation loop,
we never trigger the af_xdp_cleanup() handler. This is because we pass
errp instead of a local err pointer into the various AF_XDP setup fun
Hi Gustavo,
On 6/16/25 3:18 PM, Gustavo Romero wrote:
> From: Philippe Mathieu-Daudé
>
> Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
> hardware introduced in GICv3 and, being optional, it can be disabled
> in QEMU aarch64 VMs that support it using machine option "its=off
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c |
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18
target/arm/cpu.h | 6 ---
target/arm/cpu64.c| 16 +++
targ
John Snow writes:
> Hi, I've long been a little confused about the specifics of our build
> platform guarantee and how it applies to documentation and testing.
"Guarantee" feels too strong. See below.
> My *current* understanding is that our build platform guarantee applies to
> both unit test
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 40 -
target/arm/cpu.c | 29
target/arm/cpu.h | 2 --
My main concern about the long list of caveats for writing memory is the
user will almost certainly cause weird things to happen which will then
be hard to debug. I can see the patcher example however it would be
useful to know what other practical uses this interface provides.
Of course! My main
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 16
target/arm/cpu.c | 15 +--
target/arm/cpu.h | 2 --
target/arm/cpu64.c
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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Mostly addressed Peter's feedback:
- make sure every inbetween stage compiles (also fixed some bonus issues)
- try to make the scripts more robust, add a note the generated file,
and make sure to grab only registers we actually want
- I did a half-hearted attempt to use python instead of awk, b
John Snow writes:
> Update the python tests to also check QAPI and the QAPI Sphinx
> extensions. The docs/sphinx/qapidoc_legacy.py file is not included in
> these checks, as it is destined for removal soon. mypy is also not
> called on the QAPI Sphinx extensions, owing to difficulties supporting
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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On 2025/6/17 20:37, Jason Gunthorpe wrote:
On Mon, Jun 16, 2025 at 08:14:27PM -0700, Nicolin Chen wrote:
On Mon, Jun 16, 2025 at 08:15:11AM +, Duan, Zhenzhong wrote:
IIUIC, the guest kernel cmdline can switch the mode between the
stage1 (nesting) and stage2 (legacy/emulated VT-d), right?
From: Eric Auger
Also add kvm accessors for storing host features into idregs.
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 57 ---
target/arm/cpu.c
Hi Alex,
On 6/17/25 06:49, Alex Bennée wrote:
Gustavo Romero writes:
Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and
hot-unplug on arm64.
Queued to testing/next, thanks.
Thanks a lot!
Cheers,
Gustavo
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 5 ++--
target/arm/cpu-features.h | 10
target/arm/cpu.c | 8 +++---
target/arm/cpu.h | 3 ---
targe
On 6/17/25 5:23 PM, Miguel Luis wrote:
> Hi Alyssa,
>
>> On 17 Jun 2025, at 14:17, Alyssa Ross wrote:
>>
>> Eric Auger writes:
>>
>>> From: Haibo Xu
>>>
>>> Up to now virt support on guest has been only supported with TCG.
>>> Now it becomes feasible to use it with KVM acceleration.
>>>
>>> A
On Mon, Jun 16, 2025 at 08:14:27PM -0700, Nicolin Chen wrote:
> On Mon, Jun 16, 2025 at 08:15:11AM +, Duan, Zhenzhong wrote:
> > >IIUIC, the guest kernel cmdline can switch the mode between the
> > >stage1 (nesting) and stage2 (legacy/emulated VT-d), right?
> >
> > Right. E.g., kexec from "int
On Tue, Jun 17, 2025 at 09:03:32PM +0800, Yi Liu wrote:
> > I suggest fixing the Linux driver to refuse to run in sm_on mode if
> > the HW supports scalable mode and ecap_slts = false. That may not be
> > 100% spec compliant but it seems like a reasonable approach.
>
> running sm_on with only ecap
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