Hello there, would you be so kind to give some feedback on this patch?
> On 23 May 2025, at 18:44, Kirill Martynov wrote:
>
> Certain error conditions can trigger x86_cpu_dump_state() to output CPU state
> debug information e.g. KVM emulation failure due to misbehaving guest.
> However, if the C
On 2025/6/17 11:22, Nicolin Chen wrote:
On Mon, Jun 16, 2025 at 03:38:26PM +0800, Yi Liu wrote:
On 2025/6/16 13:59, Nicolin Chen wrote:
On Thu, Jun 12, 2025 at 08:53:40PM +0800, Yi Liu wrote:
That being said, IOMMU_NOTIFIER_IOTLB_EVENTS should not be needed
for passthrough devices, right?
No
Hi Peter,
> Finally there's
>
> DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
>
> which is exposed to the users via cache mode setting of cpu:
>
> https://www.libvirt.org/formatdomain.html#cpu-model-and-topology
>
> look for 'cache'.
I found this link doesn't mention "l3-cache
From: lxx <1733205...@qq.com>
This patch adds support for the Zilsd and Zclsd extension,
which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0
Signed-off-by: LIU Xu
Co-developed-by: SUN Dongya
Co-developed-by: ZHAO Fujin
Reviewed-by: Alistair Francis
---
target/riscv/
Thanks for Alistair's correction on the V8 version.
Now Zclsd has been disabled for the "max" CPU as C and F are already
enabled.
lxx (1):
target/riscv: Add Zilsd and Zclsd extension support
target/riscv/cpu.c| 4 +
target/riscv/cpu_cfg_fields.h.inc | 2 +
On 6/16/25 12:13, John Levon wrote:
Signed-off-by: John Levon
---
include/hw/vfio/vfio-device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/vfio/vfio-device.h b/include/hw/vfio/vfio-device.h
index d45e5a68a2..abea652be2 100644
--- a/include/hw/vfio/vfio-device.h
+++ b/inclu
There are cases where we do not want the memory layout of a texture to
be tiled as the component processing the texture would not know how to
de-tile either via software or hardware. Therefore, ensuring that the
memory backing the texture has a linear layout is absolutely necessary
in these situati
In cases where the scanout buffer is provided as a texture (e.g. Virgl)
we need to check to see if it has a linear memory layout or not. If
it doesn't have a linear layout, then blitting it onto the texture
associated with the display surface (which already has a linear layout)
seems to ensure that
Newer versions of Spice server should be able to accept dmabuf
fds from Qemu for clients that are connected via the network.
In other words, when this option is enabled, Qemu would share
a dmabuf fd with Spice which would encode and send the data
associated with the fd to a client that could be loc
While trying to export and obtain fds associated with a texture, it
is possible that the fds returned after eglExportDMABUFImageMESA()
call have error values. Therefore, we need to evaluate the value of
all fds and return false if any of them are negative.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
To address the limitation that this option is incompatible with
remote clients, this patch series adds an option to select a
preferred codec and also enable gl=on option for clients that
are connected via the network. In other words, with this option
enabled (and the below linked Spice series merge
Giving users an option to choose a particular codec will enable
them to make an appropriate decision based on their hardware and
use-case. Note that, the Spice server would use this codec with
Gstreamer encoder and only when gl=on is specified.
If no codec is provided, then the codec gstreamer:h26
Since most encoders/decoders (invoked by Spice) may not work properly
with tiled memory associated with a texture, we need to create another
texture that has linear memory layout and use that instead.
Note that, there does not seem to be a direct way to indicate to the
GL implementation that a tex
In the specific case where the display layer (virtio-gpu) is using
dmabuf, and if remote clients are enabled (-spice gl=on,port=),
it makes sense to limit the maximum (streaming) rate (refresh rate)
to a fixed value using the GUI refresh timer. Otherwise, the updates
or gl_draw requests would b
From: Yuquan Wang
This creates a specific CXL host bridge (0001:00) with two cxl
root ports on sbsa-ref. And the memory layout provides separate
space windows for the cxl host bridge in the sbsa-ref memmap:
- 64K CXL Host Bridge Component Registers (CHBCR)
- 64K CXL_PIO
- 128M CXL_MMIO
- 256M
From: Yuquan Wang
Define a new CXL host bridge type (TYPE_CXL_HOST). This is an
independent CXL host bridge which combined GPEX features (ECAM, MMIO
windows and irq) and CXL Host Bridge Component Registers (CHBCR).
The root bus path of CXL_HOST is "0001:00", that would not affect the
original PC
v2 -> v3:
- Update the commit message
- Fix some alignment and space problems
- Add a SPDX header for the new file
- Remove unnecessary comments
- Add CXL_HOST_BRIDGE config
v1 -> v2:
- Move the code of new bridge to hw/pci-host/cxl.c
- Fix and simplify some logic on handling the different bridge t
This renames some descriptions and definitions of pxb cxl host
bridge, since the original names can be confusing.
Signed-off-by: Yuquan Wang
---
hw/pci-bridge/pci_expander_bridge.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/
On Fri, Apr 25, 2025 at 10:18 PM Ran Wang wrote:
>
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
>
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Patches based on alistair/riscv-
On Thu, Jun 12, 2025 at 6:16 PM ~liuxu wrote:
>
> From: lxx <1733205...@qq.com>
>
> This patch adds support for the Zilsd and Zclsd extension,
> which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0
>
> Signed-off-by: LIU Xu
> Co-developed-by: SUN Dongya
> Co-developed-by
On Mon, Jun 16, 2025 at 08:15:11AM +, Duan, Zhenzhong wrote:
> >IIUIC, the guest kernel cmdline can switch the mode between the
> >stage1 (nesting) and stage2 (legacy/emulated VT-d), right?
>
> Right. E.g., kexec from "intel_iommu=on,sm_on" to "intel_iommu=on,sm_off",
> Then first kernel will
On Mon, Jun 16, 2025 at 03:38:26PM +0800, Yi Liu wrote:
> On 2025/6/16 13:59, Nicolin Chen wrote:
> > On Thu, Jun 12, 2025 at 08:53:40PM +0800, Yi Liu wrote:
> > > > > That being said, IOMMU_NOTIFIER_IOTLB_EVENTS should not be needed
> > > > > for passthrough devices, right?
> > > >
> > > > No, ev
Hi Alistair,
On 2025/6/17 10:59, Alistair Francis wrote:
On Fri, Apr 25, 2025 at 10:22 PM Ran Wang wrote:
From: Huang Borong <3543977...@qq.com>
This implementation provides emulation for the Xiangshan Kunminghu
FPGA prototype platform, including support for UART, CLINT, IMSIC,
and APLIC dev
在 2025/6/6 下午2:30, Bibo Mao 写道:
If kernel irqchip is set such as kvm_irqchip_in_kernel() return true, there
is special operations with irqchips in such fields:
1. During irqchip object realization, kvm_create_device() is used here
to create irqchip in KVM kernel.
2. Add pre_save and p
Set the "use-legacy-x86-rom" property to false by default, and only set
it to true on x86 since only x86 will need it.
Signed-off-by: Shaoqin Huang
---
hw/display/ramfb-standalone.c | 2 +-
hw/i386/pc_q35.c | 3 +++
hw/vfio/pci.c | 2 +-
3 files changed, 5 insertions
Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specific. For ot
Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specific. For ot
On Fri, Apr 25, 2025 at 10:22 PM Ran Wang wrote:
>
> From: Huang Borong <3543977...@qq.com>
>
> This implementation provides emulation for the Xiangshan Kunminghu
> FPGA prototype platform, including support for UART, CLINT, IMSIC,
> and APLIC devices. More details can be found at
> https://github
On Thu, Jun 12, 2025 at 6:16 PM ~liuxu wrote:
>
> From: lxx <1733205...@qq.com>
>
> This patch adds support for the Zilsd and Zclsd extension,
> which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0
>
> Signed-off-by: LIU Xu
> Co-developed-by: SUN Dongya
> Co-developed-by
在 2025/6/11 下午2:36, Bibo Mao 写道:
On 2025/6/9 下午6:48, Song Gao wrote:
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 718b5b4f92..6b670e7936 100644
--- a/h
在 2025/6/11 下午2:26, Bibo Mao 写道:
On 2025/6/9 下午6:48, Song Gao wrote:
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 37 ++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
index c69
在 2025/6/11 下午2:40, Bibo Mao 写道:
On 2025/6/9 下午6:48, Song Gao wrote:
the AVEC controller supports 256*256 irqs, all the irqs connect CPU
INT_AVEC irq
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 28
hw/loongarch/virt.c | 11 +--
target
On 2025/5/29 18:41, Tomita Moeko wrote:
> On 2025/5/29 2:30, Alex Williamson wrote:
>> On Wed, 28 May 2025 23:55:48 +0800
>> Tomita Moeko wrote:
>>
>>> Introduce x-pci-class-code option to allow users to override PCI class
>>> code of a device, similar to the existing x-pci-vendor-id option. Only
* Moger, Babu (babu.mo...@amd.com) wrote:
> Hi Dave,
>
> On 6/6/25 07:29, Dr. David Alan Gilbert wrote:
> > * Babu Moger (babu.mo...@amd.com) wrote:
> >> Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
> >> MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
Hi Phil,
On 6/16/25 2:59 AM, Philippe Mathieu-Daudé wrote:
Hi Alejandro,
On 12/6/25 22:59, Alejandro Jimenez wrote:
Hi Ethan,
On 6/12/25 4:36 AM, Ethan MILON wrote:
Hi,
Is this series the right place to include the following minor fix?
I would defer this change for two reasons:
1) This
On Mon, Jun 16, 2025 at 7:36 AM Markus Armbruster wrote:
> John Snow writes:
>
> > If we remove the legacy parser, the doc-good.json formatting begins to
>
> "parser"? You mean docs/sphinx/qapidoc_legacy.py, don't you?
>
Mmm... yes, I'm conflating the purpose of the series (removing the legacy
On Mon, Jun 16, 2025 at 08:56:50PM +, Chaney, Ben wrote:
> Not all pmem regions are backed by non-volatile memory. Syncing volatile
> memory provides no benefit, but can cause performance issues is some
> cases. Only sync memory that is marked as non-volatile.
>
> Signed-off-by: Ben Chaney
>
Not all pmem regions are backed by non-volatile memory. Syncing volatile
memory provides no benefit, but can cause performance issues is some
cases. Only sync memory that is marked as non-volatile.
Signed-off-by: Ben Chaney
Fixes: bd108a44bc29 (migration: ram: Switch to ram block writeback)
---
m
On 6/16/25, 4:35 PM, "Peter Xu" mailto:pet...@redhat.com>>
wrote:
> On Mon, Jun 16, 2025 at 07:43:02PM +, Chaney, Ben wrote:
>> Not all pmem regions are backed by non-volatile memory. Syncing volatile
>> memory provides no benefit, but can cause performance issues is some
>> cases. Only sy
On Mon, Jun 16, 2025 at 07:43:02PM +, Chaney, Ben wrote:
> Not all pmem regions are backed by non-volatile memory. Syncing volatile
> memory provides no benefit, but can cause performance issues is some
> cases. Only sync memory that is marked as non-volatile.
>
> Fixes: bd108a44bc29 (migratio
If the user writes a large value to the register but with the bottom
bits unset we could end up with something illegal. By clamping ahead
of the check we at least assure we won't assert(bpr > 0) later in the
GIC interface code.
Signed-off-by: Alex Bennée
---
hw/intc/arm_gicv3_cpuif.c | 5 -
This patch separates the generation logic of trace_foo() for the UST and DTrace
backends from other backends.
The motivation is to remove the unnecessary if (true) in the _no_check
function, as UST and DTrace do not require a trace_event_get_state check
without introducing a seperate function it
The vcpu property is no longer used in these backends. Removing it avoids
unnecessary checks and simplifies the code generation for these trace backends.
Signed-off-by: Tanish Desai
---
scripts/tracetool/backend/log.py| 6 +-
scripts/tracetool/backend/simple.py | 6 +-
scripts/tracet
Moved trace_event_get_state check from _no_check_trace_foo to trace_foo, and
removed
if (true) checks. The _no_check_trace_foo now only emits backend-specific core
logic, avoiding trace event conditionals entirely.
This brings conditional logic in format/h.py, reducing duplication across
backends
This series of patch aims to removes the leftover if (true) condition from
trace_foo, a remnant from the TCG tracing feature removal.
It replaces it with a proper trace_event_get_state(...) check where
necessary(for log/simple/syslog and ftrace backend).
Additionally, this change centralizes the
Not all pmem regions are backed by non-volatile memory. Syncing volatile
memory provides no benefit, but can cause performance issues is some
cases. Only sync memory that is marked as non-volatile.
Fixes: bd108a44bc29 (migration: ram: Switch to ram block writeback)
---
migration/ram.c | 4 +++-
1
Solomon Tan writes:
> According to the Arm A-profile A64 Instruction Set Architecture,
> RETA[AB] should be decoded as UNDEF if the pauth feature is not
> implemented.
>
> Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to
> decodetree")
> Signed-off-by: Solomon Tan
Rev
Hi Dave,
On 6/6/25 07:29, Dr. David Alan Gilbert wrote:
> * Babu Moger (babu.mo...@amd.com) wrote:
>> Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
>> MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
>> support for IC prefetch.
>>
>> CPUID_Fn8021_EA
-- Forwarded message -
From: Stefan Hajnoczi
Date: Tue, Jun 17, 2025 at 12:00 AM
Subject: Re: Some doubts regarding scripts/tracetool/backend/*.py
To: Tanish Desai
On Mon, Jun 16, 2025 at 12:48 AM Tanish Desai
wrote:
Please CC qemu-devel and Paolo Bonzini so that others can pa
On Fri, Jun 13, 2025 at 12:54:20PM -0400, Sean Wei wrote:
> Some of the LGPLv2.1 boiler-plate still contained the
> obsolete "51 Franklin Street" postal address.
>
> Replace it with the canonical GNU licenses URL recommended by the FSF:
> https://www.gnu.org/licenses/
>
> Signed-off-by: Sean Wei
According to the Arm A-profile A64 Instruction Set Architecture,
RETA[AB] should be decoded as UNDEF if the pauth feature is not
implemented.
Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to
decodetree")
Signed-off-by: Solomon Tan
---
target/arm/tcg/translate-a64.c | 4
On Thu, Jun 12, 2025 at 11:05 AM Thomas Huth wrote:
>
> On 12/06/2025 15.08, Stefan Hajnoczi wrote:
> > On Thu, Jun 12, 2025 at 12:36 AM Thomas Huth wrote:
> >>
> >> On 11/06/2025 21.09, Stefan Hajnoczi wrote:
> >>> On Wed, Jun 11, 2025 at 2:36 PM Thomas Huth wrote:
>
> On 11/06/2025 0
On 6/16/25 7:12 AM, Jonathan Cameron wrote:
On Fri, 13 Jun 2025 15:44:49 +0100
Shameer Kolothum wrote:
Now that arm,virt can have user-creatable smmuv3 devices, document it.
Signed-off-by: Shameer Kolothum
---
qemu-options.hx | 6 ++
1 file changed, 6 insertions(+)
diff --git a/qe
On Thu, 12 Jun 2025 at 16:17, Jonathan Cameron
wrote:
> On Fri, 30 May 2025 18:54:30 +0800
> wangyuquan wrote:
> > Dynamic cxl topology problem
> >
> > Actually the ideal expectation is sbsa-ref could also have a dynamic cxl
> > topology by user
> > parameters. Accor
The following changes since commit a6f02277595136832c9e9bcaf447ab574f7b1128:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2025-06-12 14:16:11 -0400)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/tracing-pull-request
fo
From: oltolm
The build fails on Windows. Replace calls to Unix programs like ´cat´,
´sed´ and ´true´ with calls to ´python´ and wrap calls to
´os.path.relpath´ in try-except because it can fail when the two paths
are on different drives. Make sure to convert the Windows paths to Unix
paths to pre
On Mon, Jun 16, 2025 at 1:00 PM Paolo Bonzini wrote:
>
> On 6/16/25 18:46, Stefan Hajnoczi wrote:
> > Hi Paolo,
> > The CI is hitting the following new issue in rust/hw/hpet/device.rs:
>
> Thanks! I just saw it as well.
>
> As you've noticed, this job is allowed to fail, because it's just making
On Fri, Jun 13, 2025 at 04:36:20PM -0400, John Snow wrote:
> These modules don't have specific maintainers, so they're lumped in
> together here as miscellaneous.
>
> Signed-off-by: John Snow
> ---
> qapi/control.json| 2 +-
> qapi/ebpf.json | 2 +-
> qapi/introspect.json | 22 ++
On Fri, Jun 13, 2025 at 04:36:16PM -0400, John Snow wrote:
> Signed-off-by: John Snow
> ---
> qapi/sockets.json | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Eric Blake
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
Virtualization: qemu.org | libguestfs
On 6/16/25 18:46, Stefan Hajnoczi wrote:
Hi Paolo,
The CI is hitting the following new issue in rust/hw/hpet/device.rs:
Thanks! I just saw it as well.
As you've noticed, this job is allowed to fail, because it's just making
sure that we find these issues before they hit the "real" CI targets
Hi Paolo,
The CI is hitting the following new issue in rust/hw/hpet/device.rs:
error: lifetime flowing from input to output with different syntax can
be confusing
--> ../rust/hw/timer/hpet/src/device.rs:770:15
|
770 | fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode {
| ^ --
On Mon, Jun 16, 2025, 12:31 PM Eric Blake wrote:
> On Fri, Jun 13, 2025 at 04:36:05PM -0400, John Snow wrote:
> > Signed-off-by: John Snow
> > ---
> > qapi/block-core.json | 186 -
> > qapi/block-export.json | 36
> > qapi/block.json|
On Fri, Jun 13, 2025 at 04:36:05PM -0400, John Snow wrote:
> Signed-off-by: John Snow
> ---
> qapi/block-core.json | 186 -
> qapi/block-export.json | 36
> qapi/block.json| 14 ++--
> qapi/transaction.json | 20 ++---
> 4 files chang
From: Fabian Vogt
Some platforms require CONFIG_NO_IOPORT_MAP=y but would also support
qemu_fw_cfg over MMIO. Currently the qemu_fw_cfg module can't be built for
those as it needs HAS_IOPORT_MAP=y for ioport remapping.
This patch allows to build the qemu_fw_cfg in those cases. If
CONFIG_HAS_IOPO
On Mon, 16 Jun 2025, Markus Armbruster wrote:
Chao Liu writes:
On 2025/6/16 13:55, Markus Armbruster wrote:
Chao Liu writes:
From: Chao Liu
Hi, all:
After several rounds of discussion, I think that adding a -t option to the
`info mtree` command, which enables the display of tree-like no
On 6/16/25 12:13, John Levon wrote:
This keeps the existence of ->region_fds private to hw/vfio/device.c.
Signed-off-by: John Levon
Reviewed-by: Cédric Le Goater
Applied to vfio-next.
Thanks,
C.
"VMware" is the vendor's official spelling.
Adjust the spelling in MAINTAINERS for consistency.
Signed-off-by: Sean Wei
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0477e124d1..7428217361 100644
--- a/MAINTAINERS
+++ b/MAINTA
After the docs directory restructuring, several comments
refer to paths that no longer exist.
Replace these references to the current file locations
so readers can find the correct files.
Related commits
---
189c099f75f (Jul 2021)
docs: collect the disparate device emulation do
Several source comments still refer to docs with the old .txt
extension that were previously converted to reStructuredText.
Update these references to use the correct .rst extensions to
maintain accurate in-tree documentation pointers.
No functional changes.
Related commits:
50f8174c5c1 (Jul 2
The entry for the VMware PVSCSI spec uses "vwm" instead of "vmw",
which does not match any file in the tree.
Correct the path so scripts/get_maintainer.pl can match the file.
Signed-off-by: Sean Wei
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS
On Fri, 13 Jun 2025 16:36:19 -0400
John Snow wrote:
> Signed-off-by: John Snow
> ---
> qapi/yank.json | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/qapi/yank.json b/qapi/yank.json
> index 9bd8ecce27f..931d4b22d4b 100644
> --- a/qapi/yank.json
>
Several files were renamed in previous commits, causing their entries
in MAINTAINERS to reference outdated paths.
This prevents scripts/get_maintainer.pl from correctly matching
these files to their maintainers.
Update the filenames to reflect their current locations so that
maintainer lookup work
The documentation tree has been converted to reStructuredText, but
two entries in MAINTAINERS still point to the removed *.txt files.
This prevents scripts/get_maintainer.pl from matching the documents.
Update those entries to *.rst so the maintainer script works again.
Related commits:
8472cc
Several files were renamed in previous commits, causing their entries
in MAINTAINERS and source comments to reference outdated paths.
Update the filenames to reflect their current locations so that
maintainer lookup works properly, and readers can find the correct files.
The rename history can b
Sorry I did not reply-all.
Albert Esteve
Principal Software Engineer
Red Hat
aest...@redhat.com
On Mon, Jun 16, 2025 at 5:28 PM Albert Esteve wrote:
>
>
>
> On Thu, Jun 12, 2025 at 6:19 PM Stefan Hajnoczi wrote:
> >
> > On Mon, Jun 09, 2025 at 04:47:23PM +0200, Albert Esteve wrote:
> > > A
Hi Phil,
On 6/16/25 10:33, Philippe Mathieu-Daudé wrote:
Hi Gustavo, why reset authorship?
It was not intentional. hmm maybe it changed because I tweaked
the commit message and the code due to rebasing as well? Do you
know how to restore it?
Cheers,
Gustavo
On 16/6/25 15:18, Gustavo Romero
Hi Philippe,
I update this to use the proper API call.
Regards,
Jared Rossi
On 6/16/25 6:04 AM, Philippe Mathieu-Daudé wrote:
Hi,
On 23/10/24 15:17, Thomas Huth wrote:
From: Jared Rossi
Build an IPLB for any device with a bootindex (up to a maximum of 8
devices).
The IPLB chain is place
On 2025/6/16 22:44, Markus Armbruster wrote:
Chao Liu writes:
On 2025/6/16 13:55, Markus Armbruster wrote:
Chao Liu writes:
From: Chao Liu
Hi, all:
After several rounds of discussion, I think that adding a -t option to the
`info mtree` command, which enables the display of tree-like
Chao Liu writes:
> On 2025/6/16 13:55, Markus Armbruster wrote:
>> Chao Liu writes:
>>
>>> From: Chao Liu
>>>
>>> Hi, all:
>>>
>>> After several rounds of discussion, I think that adding a -t option to the
>>> `info mtree` command, which enables the display of tree-like node characters
>>> (e.
From: Shameer Kolothum
default_bus_bypass_iommu tells us whether the bypass_iommu is set
for the default PCIe root bus. Make sure we check that before adding
the "iommu-map" DT property.
Cc: qemu-sta...@nongnu.org
Fixes: 6d7a85483a06 ("hw/arm/virt: Add default_bus_bypass_iommu machine option")
S
From: Souleymane Conte
Convert the qed_spec.txt file to reStructuredText and
include it in the manual.
buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Souleymane Conte
Message-id: 20250609135124.45078-1-conte.souleym...@gmail.com
Reviewed-by: Peter Maydell
[PMM: adjus
From: Ethan Chen
The documentation for the -icount option incorrectly describes the behavior
of the sleep suboption. Based on the actual implementation and system
behavior, the effects of sleep=on and sleep=off were inadvertently reversed.
This commit updates the description to reflect their inte
From: Akihiko Odaki
Raw writes to PMCNTENCLR and PMCNTENCLR_EL0 incorrectly used their
default write function, which clears written bits instead of writes the
raw value.
PMINTENCLR and PMINTENCLR_EL1 are similar registers, but they instead
had ARM_CP_NO_RAW. Commit 7a0e58fa6487 ("target-arm: Spl
From: Frederic Konrad
This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).
Signed-off-by: Clément Chigot
Message-id: 20250526085523.809003-3-chi...@adacore.com
Reviewed-by: Peter Maydell
[PMM: slightly expanded comment documentin
From: J. Neuschäfer
Although the emulated cacheflush syscall does nothing, it still needs to
return zero to indicate success.
Cc: qemu-sta...@nongnu.org
Signed-off-by: J. Neuschäfer
Message-id: 20250613-cache-v1-1-ee9f4a9ba...@gmx.net
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
--
The AN500 application note documents that it configures the Cortex-M7
CPU to have 16 MPU regions. We weren't doing this in our emulation,
so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions
property to 16 for this board.
This bug doesn't affect any of the other board types we mod
From: Clément Chigot
Currently, arm booting processus assumes that the first_cpu is the CPU
that will boot: `arm_load_kernel` is powering off all but the `first_cpu`;
`do_cpu_reset` is setting the loader address only for this `first_cpu`.
For most of the boards, this isn't an issue as the kernel
From: Thomas Huth
Check that we can boot a Linux kernel here and that we can at
least send one ping network packet.
Signed-off-by: Thomas Huth
Message-id: 20250603101526.21217-1-th...@redhat.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS
in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20250616
for you to fetch changes up to 5ad2b1f443a96444cf3e7a2fbe17aae696201012:
linux-user/arm: Fix return value of SYS_cacheflush (2025-06-16 11:2
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU. This
event is used to send CPI identifiers from the guest to the
host. The CPI identifiers are: system type, system name,
system level and sysplex name.
System type: operating system of the
Register Control-Program Identification data with the live
migration infrastructure.
Signed-off-by: Shalini Chellathurai Saroja
Reviewed-by: Nina Schoetterl-Glausch
Reviewed-by: Thomas Huth
---
hw/s390x/sclpcpi.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/s390x/scl
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU.
Changed since v5:
- Add identifiers as class properties instead of object properties
- Add description for all the class properties
- Remove S390ControlProgramId as it is not needed anymore
Add Control-Program Identification (CPI) data to the QEMU Object
Model (QOM), along with the timestamp in which the data was received
as shown below.
virsh # qemu-monitor-command vm --pretty '{"execute":"qom-list",
"arguments":{"path":"/machine/sclp/s390-sclp-event-facility/sclpcpi"}}'
{
"return
On 2025/6/16 13:55, Markus Armbruster wrote:
Chao Liu writes:
From: Chao Liu
Hi, all:
After several rounds of discussion, I think that adding a -t option to the
`info mtree` command, which enables the display of tree-like node characters
(e.g., +--, |--), is a better approach.
As BALATON Z
On 6/13/25 18:44, Sean Wei wrote:
Some of the GPLv2 boiler-plate still contained the
obsolete "51 Franklin Street" postal address.
Replace it with the canonical GNU licenses URL recommended by the FSF:
https://www.gnu.org/licenses/
Signed-off-by: Sean Wei
---
include/hw/i2c/aspeed_i2c.h
No need to strstr() check the class name when we can use
kvm_irqchip_in_kernel() to check if the ITS from the host can be used.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Reviewed-by: Gustavo Romero
---
hw/arm/virt.c | 17 +++--
1
Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), the single
implementation of its_class_name() no longer returns NULL (it now always
returns a valid char pointer). Hence, update the prototype docstring and
remove the tautological checks that use the its_class_name() returned
value.
Si
On 6/16/25 14:49, Sean Wei wrote:
Hi Cédric & Daniel,
On 2025/6/16 3:55 AM, Cédric Le Goater wrote:
On 6/16/25 09:47, Daniel P. Berrangé wrote:
On Mon, Jun 16, 2025 at 09:29:35AM +0200, Cédric Le Goater wrote:
On 6/16/25 09:13, Daniel P. Berrangé wrote:
On Sat, Jun 14, 2025 at 07:29:09AM +02
After commit 0caed25cd171 vhost_vdpa_net_load_vlan() started seeing
VIRTIO_NET_F_CTRL_VLAN flag and making 4096 calls to the kernel with
VIRTIO_NET_CTRL_VLAN_ADD command. However, it forgot to convert the
16-bit VLAN IDs to LE format. On BE machine, the kernel calls failed
when they saw "VLAN IDs"
Hi Gustavo, why reset authorship?
On 16/6/25 15:18, Gustavo Romero wrote:
Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), the single
implementation of its_class_name() no longer returns NULL (it now always
returns a valid char pointer). Hence, update the prototype docstring and
rem
1 - 100 of 207 matches
Mail list logo
