Re: [PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function

On Thu, Jun 5, 2025 at 8:14 PM Florian Lugou wrote: > > The current handler for TXFIFO writes schedules an async callback to > pop characters from the queue. When software writes to TXFIFO faster > than the async callback delay (100ns), the timer may be pushed back > while the previous character h

Re: [PATCH v2] ramfb: Add property to control if load the romfile

On 6/6/25 4:07 PM, Cédric Le Goater wrote: On 6/6/25 10:06, Cédric Le Goater wrote: On 6/6/25 09:52, Daniel P. Berrangé wrote: On Fri, Jun 06, 2025 at 03:02:34AM -0400, Shaoqin Huang wrote: Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only the x86 need the vgabios-ramf

Re: [PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function

On Thu, Jun 5, 2025 at 8:14 PM Florian Lugou wrote: > > The current handler for TXFIFO writes schedules an async callback to > pop characters from the queue. When software writes to TXFIFO faster > than the async callback delay (100ns), the timer may be pushed back > while the previous character h

Re: [PATCH v2] target/riscv: Fix fcvt.s.bf16 NaN box checking

On Thu, May 1, 2025 at 9:44 PM Anton Blanchard wrote: > > fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16 > quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN. > > Signed-off-by: Anton Blanchard Thanks! Applied to riscv-to-apply.next Alistair > --- > target/ri

Re: [PATCH v2] target/riscv: Fix fcvt.s.bf16 NaN box checking

On Thu, May 1, 2025 at 9:44 PM Anton Blanchard wrote: > > fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16 > quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN. > > Signed-off-by: Anton Blanchard Acked-by: Alistair Francis Alistair > --- > target/riscv/fpu_help

Re: [PATCH v4 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype

On Fri, Apr 25, 2025 at 10:22 PM Ran Wang wrote: > > From: Huang Borong <3543977...@qq.com> > > This implementation provides emulation for the Xiangshan Kunminghu > FPGA prototype platform, including support for UART, CLINT, IMSIC, > and APLIC devices. More details can be found at > https://github

Re: [PATCH v5 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState

On Sat, Jun 7, 2025 at 12:12 PM Chao Liu wrote: > > Hi, > > Thanks to Daniel's testing, I have fixed this bug. > > PATCHv5: > > The differences are as follows: > > ``` > @@ -790,10 +790,11 @@ static void sifive_u_soc_realize(DeviceState *dev, > Error **errp) > MemoryRegion *mask_rom = g_new(

Re: [PATCH v5 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly

On Sat, Jun 7, 2025 at 12:13 PM Chao Liu wrote: > > riscv_plic_hart_config_string() when getting CPUState via qemu_get_cpu() > should be consistent with keeping sifive_plic_realize() > by hartid_base + cpu_index. > > A better approach is to use cpu_by_arch_id() instead of qemu_get_cpu(), > in risc

Re: [PATCH v2 0/1] riscv: qemu_chr_fe_write_all() in CONSOLE_WRITE_BYTE

On Thu, Jun 5, 2025 at 7:45 PM Daniel Henrique Barboza wrote: > > Hi, > > In this version I removed the reference of SBI_EXT_DBCN_CONSOLE_WRITE in > the commit message. That API is *non-blocking*, and citing it to justify > a change in a blocking API sounds weird. It's also uneeded since we have >

Re: [PATCH v4 5/5] hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class

On Fri, Jun 6, 2025 at 7:29 PM Zhenzhong Duan wrote: > > RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed > parent class, class_init on them may corrupt their parent class > fields. > > It's lucky that parent_realize and parent_phases are not initialized > or used until now, so ju

Re: [PATCH v2] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register

On Thu, Jun 5, 2025 at 10:50 PM Nutty Liu wrote: > > The original implementation incorrectly performed a bitwise AND > operation between the PPN of iova and PPN Mask, leading to an > incorrect PPN field in Translation-reponse register. > > The PPN of iova should be set entirely in the PPN field of

Re: [PATCH v2] ramfb: Add property to control if load the romfile

Hi Daniel, On 6/6/25 3:52 PM, Daniel P. Berrangé wrote: On Fri, Jun 06, 2025 at 03:02:34AM -0400, Shaoqin Huang wrote: Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only the x86 need the vgabios-ramfb.bin, this can cause that when use the release package on arm64 it can't f

Re: [PATCH v6 0/5] Enable shared device assignment

Hi Paolo, Since this series has received Reviewed-by/Acked-by on all patches, besides some coding style comments from Alexey and the suggestion to document the bitmap consistency from David in patch #4, Any other comments? Or I would send the next version to resolve them. Thanks Chenyi On 5/30/2

RE: [PATCH v4 4/5] hw/char/sh_serial: Remove dummy definition of SH_SERIAL class

>-Original Message- >From: Philippe Mathieu-Daudé >Subject: Re: [PATCH v4 4/5] hw/char/sh_serial: Remove dummy definition of >SH_SERIAL class > >On 6/6/25 12:40, Philippe Mathieu-Daudé wrote: >> On 6/6/25 11:24, Zhenzhong Duan wrote: >>> SH_SERIAL is declared with OBJECT_DECLARE_SIMPLE_T

Re: [PATCH v5 2/2] target/riscv: Make PMP region count configurable

On Fri, Jun 6, 2025 at 5:28 PM Jay Chang wrote: > > Previously, the number of PMP regions was hardcoded to 16 in QEMU. > This patch replaces the fixed value with a new `pmp_regions` field, > allowing platforms to configure the number of PMP regions. > > If no specific value is provided, the defaul

Re: [PATCH v5 2/2] target/riscv: Make PMP region count configurable

On Fri, Jun 6, 2025 at 5:28 PM Jay Chang wrote: > > Previously, the number of PMP regions was hardcoded to 16 in QEMU. > This patch replaces the fixed value with a new `pmp_regions` field, > allowing platforms to configure the number of PMP regions. > > If no specific value is provided, the defaul

Re: [PATCH v6] target/riscv/kvm: add max_satp_mode from host cpu

On Fri, Jun 6, 2025 at 1:45 PM Meng Zhuo wrote: > > This patch adds max_satp_mode from host kvm cpu setting. > > Tested on: Milkv Megrez (Eswin 7700x) > > Reviewed-by: Andrew Jones > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931 > Signed-off-by: Meng Zhuo Thanks! Applied to risc

Re: [PATCH v14 0/5] arm/virt: CXL support via pxb_cxl

On 28/05/2025 19:07, Jonathan Cameron via wrote: > Jonathan Cameron (5): >hw/cxl-host: Add an index field to CXLFixedMemoryWindow >hw/cxl: Make the CXL fixed memory windows devices. >hw/cxl-host: Allow split of establishing memory address and mmio > setup. With above 3 patches +

Re: [PATCH v14 2/5] hw/cxl: Make the CXL fixed memory windows devices.

On 28/05/2025 19:07, Jonathan Cameron via wrote: > Previously these somewhat device like structures were tracked using a list > in the CXLState in each machine. This is proving restrictive in a few > cases where we need to iterate through these without being aware of the > machine type. Just mak

Re: [PATCH v14 3/5] hw/cxl-host: Allow split of establishing memory address and mmio setup.

In patch 2/5, we introduced `cxl_fmws_set_memmap_and_update_mmio()`. Initially, I assumed patch 3/5 would split `cxl_fmws_set_memmap_and_update_mmio()` into two steps: 1. Traverse CXLFixedWindow and update `fw->base`. 2. Call `sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base)`. For example (my pe

[PATCH v9 5/9] plugins: Add memory hardware address read/write API

From: novafacing This patch adds functions to the plugins API to allow plugins to read and write memory via hardware addresses. The functions use the current address space of the current CPU in order to avoid exposing address space information to users. A later patch may want to add a function to

Re: [PATCH v8 0/9] Add additional plugin API functions to read and write memory and registers

I added another update I missed to v9, so please disregard this version and check https://lore.kernel.org/qemu-devel/20250608230819.3382527-1-rowanbh...@gmail.com/T/#t instead. -Rowan

[PATCH v9 7/9] plugins: Add hypercalls plugin and test

From: novafacing This patch adds a plugin that implements a simple form of hypercalls from guest code to the plugin by using the register read API. It accepts only one hypercall, which writes a magic value to guest memory. Signed-off-by: Rowan Hart --- tests/tcg/Makefile.target

[PATCH v9 8/9] plugins: Remove use of qemu_plugin_read_register where it is not permitted

This patch is required to make the insn plugin work after adding enforcement of QEMU_PLUGIN_CB_ flags in calls to read or write registers. Previously, these flags were not enforced and the API could be called from anywhere, but this was not intended as described by the documentation. Now, the flags

[PATCH v9 9/9] plugins: Update plugin version and add notes

From: novafacing This patch updates the plugin version to gate new APIs and adds notes describing what has been added. Signed-off-by: Rowan Hart --- include/qemu/qemu-plugin.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/

[PATCH v9 6/9] plugins: Add patcher plugin and test

From: novafacing This patch adds a plugin that exercises the virtual and hardware memory read-write API functions added in a previous patch. The plugin takes a target and patch byte sequence, and will overwrite any instruction matching the target byte sequence with the patch. Signed-off-by: Rowa

[PATCH v9 3/9] plugins: Add enforcement of QEMU_PLUGIN_CB flags in register R/W callbacks

This patch adds functionality to enforce the requested QEMU_PLUGIN_CB_ flags level passed when registering a callback function using the plugins API. Each time a callback is about to be invoked, a thread-local variable will be updated with the level that callback requested. Then, called API functio

[PATCH v9 0/9] Add additional plugin API functions to read and write memory and registers

This patch series adds several new API functions focused on enabling use cases around reading and writing guest memory from QEMU plugins. To support these new APIs, some utility functionality around retrieving information about address spaces is added as well. The new qemu_plugin_write_register ut

[PATCH v9 4/9] plugins: Add memory virtual address write API

From: novafacing This patch adds functions to the plugins API to allow reading and writing memory via virtual addresses. These functions only permit doing so on the current CPU, because there is no way to ensure consistency if plugins are allowed to read or write to other CPUs that aren't current

[PATCH v9 1/9] gdbstub: Expose gdb_write_register function to consumers of gdbstub

From: novafacing This patch exposes the gdb_write_register function from gdbstub/gdbstub.c via the exec/gdbstub.h header file to support use in plugins to write register contents. Reviewed-by: Alex Bennée Reviewed-by: Julian Ganz Reviewed-by: Pierrick Bouvier Signed-off-by: Rowan Hart --- g

[PATCH v9 2/9] plugins: Add register write API

From: novafacing This patch adds a function to the plugins API to allow plugins to write register contents. It also moves the qemu_plugin_read_register function so all the register-related functions are grouped together in the file. Reviewed-by: Pierrick Bouvier Signed-off-by: Rowan Hart ---

[PATCH v8 8/9] plugins: Remove use of qemu_plugin_read_register where it is not permitted

This patch is required to make the insn plugin work after adding enforcement of QEMU_PLUGIN_CB_ flags in calls to read or write registers. Previously, these flags were not enforced and the API could be called from anywhere, but this was not intended as described by the documentation. Now, the flags

[PATCH v8 6/9] plugins: Add patcher plugin and test

From: novafacing This patch adds a plugin that exercises the virtual and hardware memory read-write API functions added in a previous patch. The plugin takes a target and patch byte sequence, and will overwrite any instruction matching the target byte sequence with the patch. Signed-off-by: Rowa

[PATCH v8 9/9] plugins: Update plugin version and add notes

From: novafacing This patch updates the plugin version to gate new APIs and adds notes describing what has been added. Signed-off-by: Rowan Hart --- include/qemu/qemu-plugin.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/

[PATCH v8 2/9] plugins: Add register write API

From: novafacing This patch adds a function to the plugins API to allow plugins to write register contents. It also moves the qemu_plugin_read_register function so all the register-related functions are grouped together in the file. Reviewed-by: Pierrick Bouvier Signed-off-by: Rowan Hart ---

[PATCH v8 0/9] Add additional plugin API functions to read and write memory and registers

This patch series adds several new API functions focused on enabling use cases around reading and writing guest memory from QEMU plugins. To support these new APIs, some utility functionality around retrieving information about address spaces is added as well. The new qemu_plugin_write_register ut

[PATCH v8 3/9] plugins: Add enforcement of QEMU_PLUGIN_CB flags in register R/W callbacks

This patch adds functionality to enforce the requested QEMU_PLUGIN_CB_ flags level passed when registering a callback function using the plugins API. Each time a callback is about to be invoked, a thread-local variable will be updated with the level that callback requested. Then, called API functio

[PATCH v8 7/9] plugins: Add hypercalls plugin and test

From: novafacing This patch adds a plugin that implements a simple form of hypercalls from guest code to the plugin by using the register read API. It accepts only one hypercall, which writes a magic value to guest memory. Signed-off-by: Rowan Hart --- tests/tcg/Makefile.target

[PATCH v8 4/9] plugins: Add memory virtual address write API

From: novafacing This patch adds functions to the plugins API to allow reading and writing memory via virtual addresses. These functions only permit doing so on the current CPU, because there is no way to ensure consistency if plugins are allowed to read or write to other CPUs that aren't current

[PATCH v8 1/9] gdbstub: Expose gdb_write_register function to consumers of gdbstub

From: novafacing This patch exposes the gdb_write_register function from gdbstub/gdbstub.c via the exec/gdbstub.h header file to support use in plugins to write register contents. Reviewed-by: Alex Bennée Reviewed-by: Julian Ganz Reviewed-by: Pierrick Bouvier Signed-off-by: Rowan Hart --- g

[PATCH v8 5/9] plugins: Add memory hardware address read/write API

From: novafacing This patch adds functions to the plugins API to allow plugins to read and write memory via hardware addresses. The functions use the current address space of the current CPU in order to avoid exposing address space information to users. A later patch may want to add a function to

Re: [PATCH v1] migration: Wait for cpr.sock file to appear before connecting

On 6/6/2025 2:37 PM, Steven Sistare wrote: On 6/6/2025 2:06 PM, JAEHOON KIM wrote: On 6/6/2025 12:04 PM, Steven Sistare wrote: On 6/6/2025 12:06 PM, Daniel P. Berrangé wrote: On Fri, Jun 06, 2025 at 11:50:10AM -0400, Steven Sistare wrote: On 6/6/2025 11:43 AM, Daniel P. Berrangé wrote: On

[PATCH] docs/devel: Convert image-fuzzer.txt to restructredText format

From: Souleymane Conte buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Souleymane Conte --- This patch convert image-fuzzer.txt to restructuredText format. Here are the main updates: - Move file to docs/devel/testing directory - Properly structured sections with RST hea

Re: [PATCH 2/4] backends/tpmL Avoid using g_alloca()

On 6/6/25 4:14 AM, Thomas Huth wrote: On 05/06/2025 21.35, Philippe Mathieu-Daudé wrote: tpm_emulator_ctrlcmd() is not in hot path. Use the heap instead of the stack, removing the g_alloca() call. Signed-off-by: Philippe Mathieu-Daudé ---   backends/tpm/tpm_emulator.c | 4 ++--   1 file chan

Re: [PATCH 2/4] backends/tpmL Avoid using g_alloca()

On 6/5/25 3:35 PM, Philippe Mathieu-Daudé wrote: tpm_emulator_ctrlcmd() is not in hot path. Use the heap instead of the stack, removing the g_alloca() call. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Berger --- backends/tpm/tpm_emulator.c | 4 ++-- 1 file changed, 2 in

[PATCH v8 3/8] ppc/pnv: Add XIVE2 controller to Power11

Add a XIVE2 controller to Power11 chip and machine. The controller has the same logic as Power10. Cc: Frédéric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Cédric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 133

[PATCH v8 2/8] ppc/pnv: Introduce Power11 PowerNV machine

The Powernv11 machine doesn't have XIVE & PHBs as of now XIVE2 interface and PHB5 added in later patches to Powernv11 machine Also add mention of Power11 to powernv documentation Note: A difference from P10's and P11's machine_class_init is, in P11 different number of PHBs cannot be used on the

[PATCH v8 8/8] MAINTAINERS: Add myself as a reviewer of PowerNV emulation

Proposing myself as a reviewer in the PowerNV emulation in QEMU Have been working on PowerNV QEMU for sometime, with contributions in Power11, MPIPL and minor fixes and things such as dtb support Cc: Cédric Le Goater Cc: Frédéric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nich

[PATCH v8 7/8] tests/powernv: Add PowerNV test for Power11

With all Power11 support in place, add Power11 PowerNV test. Cc: Cédric Le Goater Cc: Frédéric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Cédric Le Goater Signed-off-by: Aditya Gupta --- tests/functional/test_ppc64_powernv.py | 4 1 file ch

[PATCH v8 5/8] ppc/pnv: Add ChipTOD model for Power11

Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod code as the Power11 core is same as Power10 core. Cc: Cédric Le Goater Cc: Frédéric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Cédric Le Goater Signed-off-by: Aditya Gupta -

[PATCH v8 6/8] tests/powernv: Switch to buildroot images instead of op-build

As op-build images haven't been updated from long time (and may not get updated in future), use buildroot images provided by cedric [1]. Use existing nvme device being used in the test to mount the initrd. Also replace the check for "zImage loaded message" to skiboot's message when it starts the

[PATCH v8 4/8] ppc/pnv: Add PHB5 PCIe Host bridge to Power11

Power11 also uses PHB5, same as Power10. Add Power11 PHBs with similar code as the corresponding Power10 implementation. Cc: Frédéric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Reviewed-by: Cédric Le Goater Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 57 +

[PATCH v8 0/8] Power11 support for QEMU [PowerNV]

Overview Note: No changes from v7, fixed minor merge conflicts on rebase. Add support for Power11 powernv machine type. As Power11 core is same as Power10, hence much of the code has been reused from Power10. Split Powernv11 chip/machine code into commits introducing: chip,machine

[PATCH v8 1/8] ppc/pnv: Introduce Pnv11Chip

Implement Pnv11Chip, currently without chiptod, xive and phb. Chiptod, XIVE, PHB are implemented in later patches. Since Power11 core is same as Power10, the implementation of Pnv11Chip is a duplicate of corresponding Pnv10Chip. Cc: Frédéric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivas

[PATCH] docs/interop: convert text file to restructuredText format

From: Souleymane Conte buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Souleymane Conte --- docs/interop/index.rst| 1 + docs/interop/qed_spec.rst | 219 ++ docs/interop/qed_spec.txt | 138 3 files chan

Re: [PATCH v4 09/17] hw/display: re-arrange memory region tracking

On 2025/06/07 0:02, Akihiko Odaki wrote: On 2025/06/06 19:16, Alex Bennée wrote: Akihiko Odaki writes: On 2025/06/05 20:57, Alex Bennée wrote: Akihiko Odaki writes: On 2025/06/03 20:01, Alex Bennée wrote: QOM objects can be embedded in other QOM objects and managed as part of their lif

Re: [PULL 13/17] include/exec: fix assert in size_memop

On 2025/06/06 1:26, Alex Bennée wrote: We can handle larger sized memops now, expand the range of the assert. Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits) Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-ID: <20250603110204.838117-14-alex.ben...@linaro.org> diff --git a/

Re: [PULL 12/17] virtio-gpu: support context init multiple timeline

On 2025/06/06 1:26, Alex Bennée wrote: From: Yiwei Zhang Venus and later native contexts have their own fence context along with multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in the flags must be dispatched to be created on the target context. Fence signaling also has to

Re: [PATCH RESEND v3] meson: fix Windows build

Am So., 8. Juni 2025 um 02:43 Uhr schrieb Pierrick Bouvier : > > On 6/7/25 2:45 AM, oltolm wrote: > > Sorry, I forgot to cc the maintainers. > > > > The build failed when run on Windows. I replaced calls to Unix programs > > like ´cat´, ´sed´ and ´true´ with calls to ´python´. I wrapped calls to >

Re: [PATCH RESEND v3] meson: fix Windows build

Am Sa., 7. Juni 2025 um 21:12 Uhr schrieb Stefan Hajnoczi : > > On Sat, Jun 07, 2025 at 11:45:04AM +0200, oltolm wrote: > > Sorry, I forgot to cc the maintainers. > > > > The build failed when run on Windows. I replaced calls to Unix programs > > like ´cat´, ´sed´ and ´true´ with calls to ´python´.

Re: [PULL 10/17] virtio-gpu: refactor async blob unmapping

On 2025/06/06 1:26, Alex Bennée wrote: From: Manos Pitsidianakis Change the 3 part async cleanup of a blob memory mapping to check if the unmapping has finished already after deleting the subregion; this condition allows us to skip suspending the command and responding to the guest right away.