Hi Cédric
> Subject: Re: [PATCH v1 03/22] hw/misc/aspeed_hace: Improve readability and
> consistency in variable naming
>
> On 3/21/25 10:25, Jamin Lin wrote:
> > Currently, users define multiple local variables within different
> > if-statements.
> > To improve readability and maintain consiste
Hi Cédric
> Subject: Re: [PATCH v1 06/22] hw/misc/aspeed_hace: Support accumulative
> mode for direct access mode
>
> On 3/21/25 10:26, Jamin Lin wrote:
> > Enable accumulative mode for direct access mode operations. In direct
> > access mode, only a single source buffer is used, so the "iovec" c
Fix following two issues in the amd viommu
1. The guest fails to setup the passthrough device when for following setup
because amd iommu enables the no DMA memory region even when guest is
using DMA remapping mode.
-device amd-iommu,intremap=on,xtsup=on,pt=on \
-device vfio-pci,host
Hi Cédric
> Subject: Re: [PATCH v1 04/22] hw/misc/aspeed_hace: Update hash source
> address handling to 64-bit for AST2700
>
> On 3/21/25 10:26, Jamin Lin wrote:
> > The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and
> > its DRAM address space is also 64-bit. To support future A
On 5/8/2025 9:35 PM, Philippe Mathieu-Daudé wrote:
The CPUX86State::enable_cpuid_0xb boolean was only disabled
for the pc-q35-2.6 and pc-i440fx-2.6 machines, which got
removed. Being now always %true, we can remove it and simplify
cpu_x86_cpuid().
Signed-off-by: Philippe Mathieu-Daudé
---
tar
On Thu, May 08, 2025 at 03:35:33PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:33 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 10/27] hw/i386/pc: Remove linuxboot.bin
> X-Mailer: git-send-email 2.47.1
>
> All PC machines now use the linuxboot_dma.bin binary,
>
On Thu, May 08, 2025 at 03:35:29PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:29 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 06/27] hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() ->
> fw_cfg_init_mem_dma()
> X-Mailer: git-send-email 2.47.1
>
> "wide" in fw_
On Thu, May 08, 2025 at 03:35:32PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:32 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 09/27] hw/nvram/fw_cfg: Remove
> fw_cfg_io_properties::dma_enabled
> X-Mailer: git-send-email 2.47.1
>
> Now than all calls to fw_cf
On Thu, May 08, 2025 at 03:35:31PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:31 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 08/27] hw/i386/pc: Remove multiboot.bin
> X-Mailer: git-send-email 2.47.1
>
> All PC machines now use the multiboot_dma.bin binary,
>
Nabih Estefan writes:
> From: Peter Foley
>
> e.g.
> I 2025-02-28 09:51:05.240071-0800 624 stream.go:47qemu:
> Uninitialized value was created by an allocation of 'key_in_cur.i' in the
> stack frame
> I 2025-02-28 09:51:05.240187-0800 624 stream.go:47qem
On Thu, 8 May 2025 at 19:27, Fabiano Rosas wrote:
> > During multifd migration, zero pages are are written if
> > they are migrated more than ones.
>
> s/ones/once/
> s/ones/once/
> extra blank line here^
>
> nit: Inconsistent use of capitalization for the feature names. I'd keep
> it all lowercas
On Fri, 9 May 2025 at 00:34, Peter Xu wrote:
> I may not have followed the whole discussions, but have you tried to avoid
> this global?
-> https://lore.kernel.org/qemu-devel/875xkyyxyy@suse.de/
* Yes, it was discussed, passing it as a parameter would change the
function prototype and en
From: Xuemei Liu
Address an error in migration by discarding 'riscv_aplic' and 'riscv_imsic'
in vmstate_register_with_alias_id() when aia is configured as
'aplic-imsic' in riscv kvm vm.
Previously, the fields in the vmsds of 'riscv_aplic' and 'riscv_imsic' can
only be initialized under certain s
Philippe Mathieu-Daudé 於 2025年5月8日 週四 下午2:19寫道：
>
> Hi Tim,
>
> On 8/5/25 04:15, Tim Lee wrote:
> > Fix flash device part number to `mx66l1g45g` according image-bmc run on
> > npcm8xx
> > evb board (SPIFlash...SF: Detected mx66l1g45g, total 128 MiB)
> >
> > And add auto zero flash image size to r
Hi Cédric
> Subject: Re: [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit
> digest_addr variable for AST2700
>
> On 3/21/25 10:26, Jamin Lin wrote:
> > The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a
> > 64-bit DRAM address space. To support future AST2700 updates, a
On Thu, May 08, 2025 at 03:35:30PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:30 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 07/27] hw/i386/x86: Remove
> X86MachineClass::fwcfg_dma_enabled field
> X-Mailer: git-send-email 2.47.1
>
> The X86MachineClass::fwc
On Thu, May 08, 2025 at 03:35:26PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:26 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 03/27] hw/nvram/fw_cfg: Rename fw_cfg_init_mem() with
> '_nodma' suffix
> X-Mailer: git-send-email 2.47.1
>
> Rename fw_cfg_init_mem
On Thu, May 08, 2025 at 03:35:28PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:28 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 05/27] hw/nvram/fw_cfg: Factor
> fw_cfg_init_mem_internal() out
> X-Mailer: git-send-email 2.47.1
>
> Factor fw_cfg_init_mem_interna
On Sun, Apr 27, 2025 at 10:26:52AM +0800, Chenyi Qiang wrote:
>Hi David,
>
>Any thought on patch 10-12, which is to move the change attribute into a
>priority listener. A problem is how to handle the error handling of
>private_to_shared failure. Previously, we thought it would never be able
>to fai
On Thu, May 08, 2025 at 03:35:29PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:29 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 06/27] hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() ->
> fw_cfg_init_mem_dma()
> X-Mailer: git-send-email 2.47.1
>
> "wide" in fw_
From: Nabih Estefan
Sent: Friday, May 9, 2025 6:07 AM
To: qemu-devel@nongnu.org
Cc: CS20 KFTing ; wuhao...@google.com;
peter.mayd...@linaro.org; faro...@suse.de; lviv...@redhat.com;
pbonz...@redhat.com; qemu-...@nongnu.org; Nabih Estefan
Subject: [PATCH 2/2] tests/qtest: Migrate GMAC test from
On Thu, May 08, 2025 at 03:35:27PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Thu, 8 May 2025 15:35:27 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v4 04/27] hw/mips/loongson3_virt: Prefer using
> fw_cfg_init_mem_nodma()
> X-Mailer: git-send-email 2.47.1
>
> fw_cfg_init_mem_wide() i
Ensure successful migration over RDMA by verifying that RLIMIT_MEMLOCK is
set to at least 128MB. This allocation is necessary due to the requirement
to pin significant portions of guest memory, typically exceeding 100MB
in this test, while the remainder is transmitted as compressed zero pages.
Oth
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Reviewed-by: Jack Wang
Signed-off-by: Li Zhijian
---
V2:
- Co
From: Nabih Estefan
Sent: Friday, May 9, 2025 6:07 AM
To: qemu-devel@nongnu.org
Cc: CS20 KFTing ; wuhao...@google.com;
peter.mayd...@linaro.org; faro...@suse.de; lviv...@redhat.com;
pbonz...@redhat.com; qemu-...@nongnu.org; Nabih Estefan
Subject: [PATCH 1/2] hw/arm: Add GMAC devices to NPCM8XX
From: Tim Lee
Sent: Thursday, May 8, 2025 10:15 AM
To: peter.mayd...@linaro.org; wuhao...@google.com; CS20 KFTing
; CS20 CHLi30
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Tim Lee
Subject: [v2] hw/arm/npcm8xx_boards: Add auto zero flash image and device part
number
Fix flash device part
From: Collin Walling
In order to support secure IPL (aka secure boot) for the s390-ccw BIOS,
a new s390 DIAGNOSE instruction is introduced to leverage QEMU for
handling operations such as signature verification and certificate
retrieval.
Currently, only subcode 0 is supported with this patch, wh
Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB
When secure boot is enabled (-secure-boot on) and certificate(s) are
provided, the boot operates in True Secure IPL mode.
Any verification error during True Secure IPL mode will cause the
entire boot process to terminate.
Secure IPL in audit mode requires at least one certificate provided in
the
Introduce Secure-IPL (SIPL) facility.
Use fac_ipl to represent bytes 136 and 137 for IPL device facilities
of the SCLP Read Info block.
Availability of SIPL facility is determined by byte 136 bit 1 of the
SCLP Read Info block. Byte 136's facilities cannot be represented
without the availability o
On 5/8/25 2:34 PM, Daniel Borkmann wrote:
> Extend inhibit=on setting with the option to specify a pinned XSK map
> path along with a starting index (default 0) to push the created XSK
> sockets into. Example usage:
>
> # ./build/qemu-system-x86_64 [...] \
> -netdev
> af-xdp,ifname=eth0,id=
Add -secure-boot as a parameter of s390-ccw-virtio machine type option.
The `-secure-boot on|off` command line option is implemented
to enable secure IPL.
By default, -secure-boot is set to false if not specified in
the command line.
Signed-off-by: Zhuoying Cai
---
hw/s390x/s390-virtio-ccw.c
DIAG 320 is supported when the certificate-store (CS) facility
is installed.
Availability of CS facility is determined by byte 134 bit 5 of the
SCLP Read Info block. Byte 134's facilities cannot be represented
without the availability of the extended-length-SCCB, so add it as
a check for consisten
The secure-IPL-code-loading-attributes facility (SCLAF)
provides additional security during IPL.
Availability of SCLAF is determined by byte 136 bit 3 of the
SCLP Read Info block.
Signed-off-by: Zhuoying Cai
---
target/s390x/cpu_features.c | 1 +
target/s390x/cpu_features_def.h.inc | 1
The IPL information report block (IIRB) contains information used
to locate IPL records and to report the results of signature verification
of one or more secure components of the load device.
IIRB is stored immediately following the IPL Parameter Block. Results on
component verification in any ca
If `-secure-boot on` is specified on the command line option, indicating
true secure IPL enabled, set Secure-IPL bit and IPL-Information-Report
bit on in IPIB Flags field, and trigger true secure IPL in the S390 BIOS.
Any error that occurs during true secure IPL will cause the IPL to
terminate.
S
Refactor to enhance readability before enabling secure IPL in later
patches.
Signed-off-by: Zhuoying Cai
---
pc-bios/s390-ccw/bootmap.c | 58 ++
1 file changed, 34 insertions(+), 24 deletions(-)
diff --git a/pc-bios/s390-ccw/bootmap.c b/pc-bios/s390-ccw/bootm
DIAG 320 subcode 1 provides information needed to determine
the amount of storage to store one or more certificates.
The subcode value is denoted by setting the left-most bit
of an 8-byte field.
The verification-certificate-storage-size block (VCSSB) contains
the output data when the operation co
From: Collin Walling
DIAG 508 subcode 1 performs signature-verification on signed components.
A signed component may be a Linux kernel image, or any other signed
binary. **Verification of initrd is not supported.**
The instruction call expects two item-pairs: an address of a device
component, an
Add documentation for secure IPL.
Signed-off-by: Collin Walling
Signed-off-by: Zhuoying Cai
---
docs/system/s390x/secure-ipl.rst | 249 +++
1 file changed, 249 insertions(+)
create mode 100644 docs/system/s390x/secure-ipl.rst
diff --git a/docs/system/s390x/secure-i
Create a function to validate the address parameter of DIAGNOSE.
Refactor the function for reuse in the next patch, which allows address
validation in read or write operation of DIAGNOSE.
Signed-off-by: Zhuoying Cai
---
hw/s390x/ipl.h | 6 ++
target/s390x/diag.c | 4 +---
2 files chang
This patch is necessary because of the architectural design of
IPL Parameter Block (IPLB) and IPL Information Report Block (IIRB).
IIRB will be introduced in the next patch.
Define a memory space for both IPL Parameter Block (IPLB) and
IPL Information Report Block (IIRB) since IIRB is stored immed
The IPL Information Report Block (IIRB) immediately follows the IPL
Parameter Block (IPLB).
The IPLB struct is allocated 4KB in memory, and iplb->len indicates
the amount of memory currently used by the IPLB.
To ensure proper alignment of the IIRB and prevent overlap, set
iplb->len to the maximum
Make the address variable a parameter of zipl_load_segment and return
segment length.
Modify this function for reuse in the next patch, which allows
loading segment or signature data to the destination memory address.
Add a comp_len variable to store the length of a segment and return this
variab
Add additional checks to ensure that components do not overlap with
signed components when loaded into memory.
Add additional checks to ensure the load addresses of unsigned components
are greater than or equal to 0x2000.
When the secure IPL code loading attributes facility (SCLAF) is installed,
Create a certificate store for boot certificates used for secure IPL.
Load certificates from the -boot-certificate option into the cert store.
Currently, only x509 certificates in DER format and uses SHA-256 hashing
algorithm are supported, as these are the types required for secure boot
on s390.
If secure boot in audit mode or True Secure IPL mode is enabled without
specifying a boot device, the boot process will terminate with an error.
Signed-off-by: Zhuoying Cai
---
hw/s390x/ipl.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index 4c
The current approach to enabling secure boot relies on providing
-secure-boot and -boot-certificates options, which apply to all boot
devices.
With the possibility of multiple boot devices, secure boot expects all
provided devices to be supported and eligible (e.g.,
virtio-blk/virtio-scsi using th
Add -boot-certificates as a parameter of s390-ccw-virtio machine type option.
The `-boot-certificates /path/dir:/path/file` option is implemented
to provide path to either a directory or a single certificate.
Multiple paths can be delineated using a colon.
Signed-off-by: Zhuoying Cai
---
hw/s3
DIAGNOSE 320 is introduced to support certificate store facility,
which includes operations such as query certificate storage
information and provide certificates in the certificate store.
Currently, only subcode 0 is supported with this patch, which is
used to query a bitmap of which subcodes are
Changelog v1->v2:
- Fix typos in patches
- Edit cover letter
- Add secure IPL documentation
QEMU Command-Line Interface:
- Move boot-certificates under the machine-type option for s390x-virtio-ccw
- Move secure-boot under the machine-type option for s390x-virtio-ccw
hw/s390x/ipl: Create Certific
Enable secure IPL in audit mode, which performs signature verification,
but any error does not terminate the boot process. Only warnings will be
logged to the console instead.
Add a comp_len variable to store the length of a segment in
zipl_load_segment. comp_len variable is necessary to store the
DIAG 320 subcode 2 provides verification-certificates (VCs) that are in the
certificate store. Only X509 certificates in DER format and SHA-256 hash
type are recognized.
The subcode value is denoted by setting the second-left-most bit
of an 8-byte field.
The Verification Certificate Block (VCB) c
This patch series modifies the gdbstub to address a bug running a
multi cluster machine in QEMU using TCG. The machine where the
problem was seen had several clusters of CPUs with similar
architectures and similar memory layout all working with physical
addresses. It was discovered under gdb debugg
From: Roque Arcudia Hernandez
In the context of using the remote gdb with multiple
processes/inferiors (multi cluster machine) a given breakpoint will
target an specific inferior. Current implementation of
tcg_insert_breakpoint and tcg_remove_breakpoint apply a given
breakpoint to all the cpus av
From: Roque Arcudia Hernandez
In the context of using the remote gdb with multiple
processes/inferiors (multiple cluster machine) a given breakpoint
will target an specific inferior. If needed the remote protocol will
use the packet 'H op thread-id' with op = 'g' to change focus to the
inferior w
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
From: Peter Foley
e.g.
Uninitialized value was created by an allocation of 'host_pc' in the stack
frame
#0 0xc07df87c in tb_gen_code
third_party/qemu/accel/tcg/translate-all.c:297:5
Signed-off-by: Peter Foley
Signed-off-by: Nabih Estefan
---
accel/tcg/translate-all.c | 2 +-
1 file
Fixes for miscellaneous msan finding in QEMU
Peter Foley (2):
util: fix msan findings in keyval
accel/tcg: fix msan findings in translate-all
accel/tcg/translate-all.c | 2 +-
util/keyval.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--
2.49.0.1015.ga840276032-goog
From: Peter Foley
e.g.
I 2025-02-28 09:51:05.240071-0800 624 stream.go:47qemu:
Uninitialized value was created by an allocation of 'key_in_cur.i' in the stack
frame
I 2025-02-28 09:51:05.240187-0800 624 stream.go:47qemu:
#0 0xc49f489c in keyval_p
For upstreaming we migrated this test to 7xx (since that was already
upstream) move it back to 8xx where it can check the 4 GMACs since that
is the board this test was originally created for.
Signed-off-by: Nabih Estefan
---
tests/qtest/meson.build | 6 ++-
tests/qtest/npcm_gmac-test.c | 8
This is a set of patches to add the GMAC devices to the 8xx board and
migrate the GMAC tests to 8xx, which is how they were originally
created.
Hao Wu (1):
hw/arm: Add GMAC devices to NPCM8XX SoC
Nabih Estefan Diaz (1):
tests/qtest: Migrate GMAC test from 7xx to 8xx
hw/arm/npcm8xx.c
From: Hao Wu
The GMAC was originally created for the 8xx machine. During upstreaming
both the GMAC and the 8XX we removed it so they would not depend on each
other for the process, that connection should be added back in.
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
---
hw/arm/npcm8xx.c
This removes the TARGET_I386 condition from the rtc-reset-reinjection
command. This requires providing a QMP command stub for non-i386 target.
This in turn requires moving the command out of misc-target.json, since
that will trigger symbol poisoning errors when built from target
independent code.
On 5/7/25 14:28, Helge Deller wrote:
On 5/7/25 23:12, Richard Henderson wrote:
v3: https://lore.kernel.org/qemu-devel/20240909172823.649837-1-
richard.hender...@linaro.org/
v4: https://lore.kernel.org/qemu-devel/20250224171444.440135-1-
richard.hender...@linaro.org/
Changes for v5:
- Rebas
On Thu, May 8, 2025 at 9:38 PM Stefan Hajnoczi wrote:
> On Thu, May 08, 2025 at 01:24:38AM +0100, Alberto Faria wrote:
> > Signed-off-by: Alberto Faria
> > ---
> > block/export/virtio-blk-handler.c | 7 ++--
> > hw/block/virtio-blk.c | 2 ++
> > hw/core/machine.c |
On 5/8/25 6:58 AM, Daniel P. Berrangé wrote:
Pierrick has proposed a series that introduces a concept of runtime
conditionals to the QAPI schema, in order to adapt the TARGET_*
conditionals currently used at build time:
https://lists.nongnu.org/archive/html/qemu-devel/2025-05/msg01699.html
F
On 5/8/25 02:50, Paolo Bonzini wrote:
Errors about TCI are pointless if only tools are being built; suppress
them even if the user did not specify --disable-tcg.
Signed-off-by: Paolo Bonzini
---
meson.build | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Richar
On 5/8/25 02:54, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 36
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index cda32ee6784..
On 5/8/25 6:58 AM, Daniel P. Berrangé wrote:
This removes the TARGET_* conditions from all the CPU commands
that are conceptually target independent. Top level stubs are
provided to cope with targets which do not currently implement
all of the commands.
Signed-off-by: Daniel P. Berrangé
---
q
On 5/8/25 7:40 AM, Daniel P. Berrangé wrote:
On Wed, May 07, 2025 at 04:14:39PM -0700, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
qapi/machine-target.json | 84
qapi/misc-target.json| 48 ---
scripts/qapi/expr
On 5/7/25 11:53 PM, Philippe Mathieu-Daudé wrote:
On 8/5/25 01:14, Pierrick Bouvier wrote:
This new entry can be used in QAPI json to specify a runtime conditional
to expose any entry, similar to existing 'if', that applies at compile
time, thanks to ifdef. The element is always defined in C, bu
On Thu, May 08, 2025 at 01:24:38AM +0100, Alberto Faria wrote:
> Signed-off-by: Alberto Faria
> ---
> block/export/virtio-blk-handler.c | 7 ++--
> hw/block/virtio-blk.c | 2 ++
> hw/core/machine.c | 4 ++-
> hw/virtio/virtio-qmp.c| 2 ++
> tests/qtest/
On 5/7/25 11:57 PM, Philippe Mathieu-Daudé wrote:
On 8/5/25 01:14, Pierrick Bouvier wrote:
We are about to expose various target specific commands for all targets,
so we need to stub not implemented qmp_* functions.
MinGW does not support weak symbols without at least one strong
definition, so
On 5/7/25 11:40 PM, Philippe Mathieu-Daudé wrote:
On 8/5/25 01:14, Pierrick Bouvier wrote:
Add runtime helpers for target and config queries.
Note: This will be reimplemented later [1] using proper information in
TargetInfo. Meanwhile, just add a simple implementation.
[1]
https://patchew.org
On 5/8/25 7:21 AM, Daniel P. Berrangé wrote:
On Wed, May 07, 2025 at 04:14:33PM -0700, Pierrick Bouvier wrote:
We add a new .hidden field to qlit entries, which gets ignored when
creating the associated QObject.
By default .hidden is 0, so it means the entry is visible. This way,
only potentiall
On Thu, Apr 24, 2025 at 03:44:49PM +0200, Marco Cavenati wrote:
> > If we decide we need to explicitly select that new code, I don't think
> > we need any new capability, because the user has no choice in it. We
> > know that loadvm needs it, but -loadvm doesn't, any other sort of
> > mapped-ram mi
On 5/8/25 3:05 AM, Thomas Huth wrote:
On 07/05/2025 20.45, Pierrick Bouvier wrote:
On 5/7/25 12:39 AM, Thomas Huth wrote:
Then I don't understand the previous argument from Thomas to not make
thorough the default: "The thorough functional tests download a
lot of assets from the internet, so if
Following changes are implemented in this series.
1. Fixed the cache(L2,L3) property details in all the EPYC models.
2. Add RAS feature bits (SUCCOR, McaOverflowRecov) on all EPYC models
3. Add missing SVM feature bits required for nested guests on all EPYC models
4. Add the missing feature bit
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
support for IC prefetch.
CPUID_Fn8021_EAX
BitFeature description
20 Indicates support for IC prefetch.
1 FsGsKernelGsBaseNonSerializing.
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Add the support for AMD EPYC zen 5 processors (EPYC-Turin).
Add the following new feature bits on top of the feature bits from
the previous generation EPYC models.
movdiri : Move Doubleword as Direct Store Instruction
movdir64b : Move 64 Bytes as Direct Store Instruction
avx
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
TDX advertises core crystal clock with cpuid[0x15] as 25MHz for TD
guests and it's unchangeable from VMM. As a result, TDX guest reads
the APIC timer at the same frequency, 25MHz.
While KVM's default emulated frequency for APIC bus is 1GHz, set the
APIC bus rate to match with TDX explicitly to ens
On Thu, 2025-05-08 at 18:53 +0100, Daniel P. Berrangé wrote:
>
> > This patch moves those stubs from hw/i386/kvm/xen-stubs.c which was
> > built if !CONFIG_XEN_EMU, and moves them elsewhere if !CONFIG_KVM? So
> > at first glance I think it might fail for KVM && !XEN_EMU builds... ?
>
> The files
On Thu, May 08, 2025 at 05:58:48PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Add new qtests to run postcopy migration with multifd
> channels enabled.
>
> Signed-off-by: Prasad Pandit
> ---
> tests/qtest/migration/compression-tests.c | 18
> tests/qtest/migration/postcopy-
For TDX guest, the phys_bits is not configurable and can only be
host/native value.
Validate phys_bits inside tdx_check_features().
Signed-off-by: Xiaoyao Li
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Zhao Liu
---
Changes in v9:
- return -EINVAL instead of exit(1); (Zhao Liu)
---
target/i3
On Thu, May 08, 2025 at 04:41:17PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> The definitions from console.h are not needed in the bcm2835_fb.h
> header file yet, so let's move it to the place that really needs
> its definitions, i.e. into the bcm2835_fb.c file.
> This way the header can a
On Thu, May 08, 2025 at 04:41:20PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> This reverts commit 2d6d995709482cc8b6a76dbb5334a28001a14a9a.
>
> OpenBSD 7.7 fixed the problem with the -fzero-call-used-regs on OpenBSD,
> see https://github.com/openbsd/src/commit/03eca72d1e030b7a542cd6aec1 f
On Thu, May 08, 2025 at 08:09:18PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> qemu-system-hppa shuts down automatically when the BIOS is
> unable to boot from any device. So this test currently fails
> occasionally when QEMU already quit, but the test still
> expected it to be around (e.g.
On Thu, May 08, 2025 at 04:41:19PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> OpenBSD 7.7 has been released at the end of April 2025, so let's
> update to that version.
>
> Reported-by: Brad Smith
> Signed-off-by: Thomas Huth
> ---
> tests/vm/openbsd | 4 ++--
> 1 file changed, 2 inser
AioContext locking was removed in commit b49f4755c7 ("block: remove
AioContext locking").
Signed-off-by: Fiona Ebner
---
block.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/block.c b/block.c
index 0ece805e41..33f78dbe1c 100644
--- a/block.c
+++ b/block.c
@@ -4359,8 +4359,6 @@ bdrv_recu
bdrv_drained_begin() polls and is not allowed to be called with the
block graph lock held. Mark the function as such.
Suggested-by: Kevin Wolf
Signed-off-by: Fiona Ebner
---
This does not catch the issue reported by Andrey, because there
is a bdrv_graph_rdunlock_main_loop() before bdrv_drained_
From: Thomas Huth
qemu-system-hppa shuts down automatically when the BIOS is
unable to boot from any device. So this test currently fails
occasionally when QEMU already quit, but the test still
expected it to be around (e.g. to shut it down cleanly).
Adding a "-no-shutdown" seems to make it relia
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE on guest TD access of PENDING pages.
Some guest OS (e.g., Linux TD guest) may require this bit as 1.
Otherwise refuse to boot.
Add sept-ve-disable property for tdx-guest object, for user to c
On Thu, May 08, 2025 at 10:48:22AM -0700, David Woodhouse wrote:
> On Thu, 2025-05-08 at 17:01 +0200, Philippe Mathieu-Daudé wrote:
> > Cc'ing Zhao
> >
> > On 8/5/25 15:58, Daniel P. Berrangé wrote:
>
> Hm, what mailer does that? Does it mean August 5th or May 8th? Even in
> the original definiti
On Thu, 2025-05-08 at 17:01 +0200, Philippe Mathieu-Daudé wrote:
> Cc'ing Zhao
>
> On 8/5/25 15:58, Daniel P. Berrangé wrote:
Hm, what mailer does that? Does it mean August 5th or May 8th? Even in
the original definition of RFC821 they knew not to use dates in those
forms :)
> > This removes the
Prasad Pandit writes:
> From: Prasad Pandit
>
> Enable Multifd and Postcopy migration together.
> The migration_ioc_process_incoming() routine checks
> magic value sent on each channel and helps to properly
> setup multifd and postcopy channels.
>
> The Precopy and Multifd threads work during th
From: Thomas Huth
console.h brings a dependency on the and the pixman
header file (if available), so we should avoid to include this file
if it is not really necessary (otherwise we have to specify the
dependency in the meson.build file, too, to get the right include
paths everywhere). console.h
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