John Snow writes:
> On Tue, May 6, 2025 at 10:17 AM Thomas Huth wrote:
>
>> On 06/05/2025 00.49, John Snow wrote:
>> ...
>> > If there are no objections to moving to 3.9 as the minimum, I certainly
>> > don't mind. Go right ahead and I'll clean up afterwards as part of my
>> > "delint qapi" seri
On 5/6/25 23:09, Pierrick Bouvier wrote:
On 5/6/25 7:22 AM, Peter Maydell wrote:
On Mon, 5 May 2025 at 10:12, Cédric Le Goater wrote:
From: Steven Lee
Introduce a new test suite for ast2700fc machine.
Rename the original test_aarch64_aspeed.py to
test_aarch64_aspeed_ast2700.py.
Signed-off-
On 5/7/25 05:27, Steven Lee wrote:
Hi Cédric, Peter,
-Original Message-
From: Cédric Le Goater
Sent: Tuesday, May 6, 2025 11:15 PM
To: Peter Maydell
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Steven Lee
; Jamin Lin
Subject: Re: [PULL 22/23] tests/function/aspeed: Add functional
On Tue, May 06, 2025 at 04:34:54PM +0200, Philippe Mathieu-Daudé wrote:
> Include "exec/target_page.h" to be able to compile HVF on x86_64:
>
> ../target/i386/hvf/hvf.c:139:49: error: use of undeclared identifier
> 'TARGET_PAGE_SIZE'
> uint64_t dirty_page_start = gpa & ~(TARGET_PA
On Fri, May 02, 2025 at 08:56:39PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 2 May 2025 20:56:39 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 07/19] hw/i386/pc: Remove pc_compat_2_6[] array
> X-Mailer: git-send-email 2.47.1
>
> The pc_compat_2_6[] array was only used by the
On Fri, May 02, 2025 at 08:56:36PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 2 May 2025 20:56:36 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 04/19] hw/nvram/fw_cfg: Factor
> fw_cfg_init_mem_internal() out
> X-Mailer: git-send-email 2.47.1
>
> Factor fw_cfg_init_mem_interna
On Fri, May 02, 2025 at 08:56:38PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 2 May 2025 20:56:38 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 06/19] hw/nvram/fw_cfg: Remove
> fw_cfg_io_properties::dma_enabled
> X-Mailer: git-send-email 2.47.1
>
> Now than all calls to fw_cf
On Fri, May 02, 2025 at 08:56:35PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 2 May 2025 20:56:35 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 03/19] hw/mips/loongson3_virt: Prefer using
> fw_cfg_init_mem()
> X-Mailer: git-send-email 2.47.1
>
> fw_cfg_init_mem_wide() is pref
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 3fffa4a3328..625889783ec 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -1465,9 +1465,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> }
> aml_append(dsdt, scope);
>
> -if (pcmc->legac
On Fri, May 02, 2025 at 08:56:33PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 2 May 2025 20:56:33 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 01/19] hw/i386/pc: Remove deprecated pc-q35-2.6 and
> pc-i440fx-2.6 machines
> X-Mailer: git-send-email 2.47.1
>
> These machines ha
On Tue, May 06, 2025 at 04:39:05PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:39:05 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 19/19] hw/net/vmxnet3: Merge DeviceRealize in
> InstanceInit
> X-Mailer: git-send-email 2.47.1
>
> Simplify merging vmxnet3_realize(
On Tue, May 06, 2025 at 04:39:04PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:39:04 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 18/19] hw/net/vmxnet3: Remove
> VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
> X-Mailer: git-send-email 2.47.1
>
> VMXNET3_COMPAT_FLA
On Tue, May 06, 2025 at 04:39:00PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:39:00 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 14/19] hw/scsi/vmw_pvscsi: Remove
> PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
> X-Mailer: git-send-email 2.47.1
>
> PVSCSI_COMP
On Tue, May 06, 2025 at 04:39:03PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:39:03 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 17/19] hw/net/vmxnet3: Remove
> VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
> X-Mailer: git-send-email 2.47.1
>
> VMXNET3_COMPAT_
On Tue, May 06, 2025 at 04:39:02PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:39:02 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 16/19] hw/scsi/vmw_pvscsi: Convert DeviceRealize ->
> InstanceInit
> X-Mailer: git-send-email 2.47.1
>
> Simplify replacing pvscsi_r
From: Qiang Yu
We need spice version >= 0.15.3 which has spice_qxl_gl_scanout2
API for multi plane scanout support.
v2:
* use new dmabuf API and check length
* check spice_qxl_gl_scanout2 present instead of
bump spice version dependency
Signed-off-by: Qiang Yu
Reviewed-by: Marc-André L
From: Qiang Yu
It's used already, just check it explicitly.
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
Message-ID: <20250327025848.46962-3-yuq...@gmail.com>
---
ui/egl-helpers.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/ui/egl-helpers.c b/ui/eg
From: Qiang Yu
v2:
* use new dmabuf API and check length
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
[ Fix style ]
Signed-off-by: Marc-André Lureau
Message-ID: <20250327025848.46962-5-yuq...@gmail.com>
---
include/ui/egl-helpers.h | 5 ++-
ui/dbus-listener.c | 19 +---
From: Marc-André Lureau
The following changes since commit 5134cf9b5d3aee4475fe7e1c1c11b093731073cf:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2025-04-30 13:34:44 -0400)
are available in the Git repository at:
https://gitlab.com/marcandre.lureau/qemu
From: Qiang Yu
To handle multi plane.
v3:
* rename interface
* add x/y/backing_width/backing_height arg
v2:
* use new dmabuf API and check length
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
Message-ID: <20250327025848.46962-6-yuq...@gmail.com>
[ Fix style ]
Signed-off-by: Ma
From: Qiang Yu
0 is used as DRM_FORMAT_MOD_LINEAR already.
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
Message-ID: <20250327025848.46962-4-yuq...@gmail.com>
---
hw/display/vhost-user-gpu.c | 3 ++-
hw/display/virtio-gpu-udmabuf.c | 4 +++-
ui/egl-helpers.c| 3 ++
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier which
may export a multi-plane texture. For example, texture with
DCC enabled (a compressed format) has two planes, one with
compressed data, the other with meta data for compression.
v2:
* change API qemu_dmabuf_get_fd/offset/
On 5/7/25 07:20, Harsh Prateek Bora wrote:
pseries-3.0, 3.1 and 4.0 had been deprecated and due for removal now.
Also removing pre-4.1 backward compatibility hacks that aren't needed
anymore.
Harsh Prateek Bora (3):
ppc/spapr: remove deprecated machine pseries-3.0
ppc/spapr: remove depreca
On Tue, May 06, 2025 at 04:39:01PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:39:01 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 15/19] hw/scsi/vmw_pvscsi: Remove
> PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
> X-Mailer: git-send-email 2.47.1
>
> PVSCSI_COMPAT_DI
On Tue, May 06, 2025 at 04:38:59PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:59 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 13/19] hw/block/fdc-isa: Remove 'fallback' property
> X-Mailer: git-send-email 2.47.1
>
> The "fallback" property was only used by th
John Snow writes:
> On Mon, May 5, 2025 at 8:19 AM Akihiko Odaki
> wrote:
>
>> sphinx 5.3.0 fails with Python 3.13.1:
>>
>> ../docs/meson.build:37: WARNING:
>> /home/me/qemu/build/pyvenv/bin/sphinx-build:
>> Extension error:
>> Could not import extension sphinx.builders.epub3 (exception: No modu
pseries-3.0 had been deprecated and due for removal now as per policy.
Also remove legacy irq support which existed for pre pseries-3.1 machines.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h | 1 -
include/hw/ppc/spapr_irq.h | 1 -
hw/ppc/spa
pseries-3.1 had been deprecated and due for removal now as per policy.
Also remove backward compatibility flags and related code introduced for
pre pseries-4.0 machines.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h | 3 --
hw/ppc/spapr.c |
pseries-3.0, 3.1 and 4.0 had been deprecated and due for removal now.
Also removing pre-4.1 backward compatibility hacks that aren't needed
anymore.
Harsh Prateek Bora (3):
ppc/spapr: remove deprecated machine pseries-3.0
ppc/spapr: remove deprecated machine pseries-3.1
ppc/spapr: remove dep
pseries-4.0 had been deprecated and due for removal now as per policy.
Also remove pre-4.1 migration hacks which were introduced for backward
compatibility.
Suggested-by: Cédric Le Goater
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h | 1 -
hw/ppc/spapr.c | 27 --
On Tue, May 06, 2025 at 04:38:57PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:57 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 11/19] hw/nvram/fw_cfg: Remove legacy
> FW_CFG_ORDER_OVERRIDE
> X-Mailer: git-send-email 2.47.1
>
> The MachineClass::legacy_fw_cfg_
On Tue, May 06, 2025 at 04:38:58PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:58 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 12/19] hw/core/machine: Remove hw_compat_2_5[] array
> X-Mailer: git-send-email 2.47.1
>
> The hw_compat_2_5[] array was only used by
Hi Cédric, Peter,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 6, 2025 11:15 PM
> To: Peter Maydell
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Steven Lee
> ; Jamin Lin
> Subject: Re: [PULL 22/23] tests/function/aspeed: Add functional test for
> ast2700fc
>
On Tue, May 06, 2025 at 04:38:56PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:56 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 10/19] hw/i386/x86: Remove X86MachineClass::save_tsc_khz
> field
> X-Mailer: git-send-email 2.47.1
>
> The X86MachineClass::save_tsc
On Tue, May 06, 2025 at 04:38:55PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:55 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 09/19] hw/i386/pc: Remove deprecated pc-q35-2.5 and
> pc-i440fx-2.5 machines
> X-Mailer: git-send-email 2.47.1
>
> These machines ha
On Tue, May 06, 2025 at 04:38:54PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:54 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 08/19] hw/virtio/virtio-pci: Remove
> VIRTIO_PCI_FLAG_DISABLE_PCIE definition
> X-Mailer: git-send-email 2.47.1
>
> VIRTIO_PCI_FLAG_
On Tue, May 06, 2025 at 04:38:53PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:53 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 07/19] hw/virtio/virtio-pci: Remove
> VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
> X-Mailer: git-send-email 2.47.1
>
> VIRTIO_PCI_FLAG
On Tue, May 06, 2025 at 04:38:52PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:52 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 06/19] hw/net/e1000: Remove unused E1000_FLAG_MAC flag
> X-Mailer: git-send-email 2.47.1
>
> E1000_FLAG_MAC was only used by the hw_c
Rename memory region iomem32_low with iomem, also change ops name
as follows:
loongarch_pch_pic_reg32_low_ops --> loongarch_pch_pic_ops
loongarch_pch_pic_low_readw --> loongarch_pch_pic_read
loongarch_pch_pic_low_writew --> loongarch_pch_pic_write
Signed-off-by: Bibo Mao
Reviewed-
Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 31 ++-
1 file changed, 10 insertions(+)
Add trace event trace_loongarch_pch_pic_read(), replaces the following
three events:
trace_loongarch_pch_pic_low_readw()
trace_loongarch_pch_pic_high_readw()
trace_loongarch_pch_pic_readb()
The similiar with write trace event.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loon
The original iomem region only supports 4 bytes access size, set it ok
with 1/2/4/8 bytes. Also unaligned memory access is not supported.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --gi
Since memory region iomem supports memory access size with 1/2/4/8,
it can be used for memory region iomem8 and iomem32_high. Now remove
memory region iomem8 and iomem32_high, merge them into iomem together.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c
Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed
as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to
understand.
Signed-off-by: Bibo Mao
Reviewed-by: Clement Mathieu--Drif
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 20 +++
For memory region iomem32_low, generic write callback is used.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 140 +++-
1 file changed, 73 insertions(+), 67 deletions(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarc
For memory region iomem32_low, generic read callback is used.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 67 ++---
1 file changed, 47 insertions(+), 20 deletions(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch
Parameter address for read and write callback in MemoryRegionOps is
relative offset with base address of this MemoryRegionOps. It can
be directly used as offset and offset calculation can be removed.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 34
Add register read operation emulation in generic read function
loongarch_pch_pic_read(), and use this function for iomem32_high region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 27 ---
1 file changed, 8 insertions(+), 19 deletions(-
Add iomem8 region register read operation emulation in generic read
function loongarch_pch_pic_read(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 28
1 file changed, 8 insertions(+), 20 de
The meaning of macro definition STATUS_LO_START is simliar with
PCH_PIC_INT_STATUS, only that offset is different, the same for
macro POL_LO_START. Now remove these duplicated macro definitions.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 20 ++
For some registers with width 8 bytes, its name is something like
PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual,
register name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID
is used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI.
Signed-off-by: Bibo Mao
Reviewed-by: Cl
Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
be set at initial stage, rather than read callback.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 9 ++---
hw/in
With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw
This series patchset is to clean up with memory regions of loongarch pch
pic interrupt controller. Originally there are three iomem regions:
iomem32_low, iomem8, iomem32_highm. Since these regions only support
4 bytes/1 byte/4 bytes access, it is divided into three regions.
Now it is merged into o
Add iomem32_high region register write operation emulation in generic
write function loongarch_pch_pic_write(), and use this function for
iomem32_high region.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 28 +---
1 file changed, 5 inser
On Tue, May 06, 2025 at 04:38:47PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:47 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 01/19] hw/i386/pc: Remove deprecated pc-q35-2.4 and
> pc-i440fx-2.4 machines
> X-Mailer: git-send-email 2.47.1
>
> These machines ha
On Tue, May 06, 2025 at 04:38:51PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:51 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 05/19] hw/core/machine: Remove hw_compat_2_4[] array
> X-Mailer: git-send-email 2.47.1
>
> The hw_compat_2_4[] array was only used by
On Tue, May 06, 2025 at 04:38:50PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:50 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 04/19] target/i386/cpu: Remove X86CPU::check_cpuid field
> X-Mailer: git-send-email 2.47.1
>
> The X86CPU::check_cpuid boolean was on
On Tue, May 06, 2025 at 04:38:48PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:48 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 02/19] hw/i386/pc: Remove
> PCMachineClass::broken_reserved_end field
> X-Mailer: git-send-email 2.47.1
>
> The PCMachineClass::brok
On Tue, May 06, 2025 at 04:38:49PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Tue, 6 May 2025 16:38:49 +0200
> From: Philippe Mathieu-Daudé
> Subject: [PATCH v3 03/19] hw/i386/pc: Remove pc_compat_2_4[] array
> X-Mailer: git-send-email 2.47.1
>
> The pc_compat_2_4[] array was only used by the
On 4/29/2025 6:06 PM, Zhao Liu wrote:
On Thu, Apr 24, 2025 at 01:51:55PM +0800, Xiaoyao Li wrote:
Date: Thu, 24 Apr 2025 13:51:55 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v8 31/55] i386/cpu: introduce
x86_confidential_guest_cpu_instance_init()
Hi Paolo,
On 4/1/2025 9:01 PM, Xiaoyao Li wro
This patch is much better than before, except that there is redundant
char [[PATCH V3] with title :)
Reviewed-by: Bibo Mao
On 2025/5/6 下午4:09, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel, the initrd
is loaded in the ram. If the initrd size is too large,
On Wed, May 7, 2025 at 2:28 AM Richard Henderson
wrote:
>
> On 5/6/25 10:50, Richard Henderson wrote:
> >> +*(uint64_t *)&x = 0x4ff0UL;
> >> +*(uint64_t *)&y = 0x4ff0UL;
> >
> > 0x1.0p256
> >
> >> +*(uint64_t *)&z = 0x2ff0UL;
> >
> > 0x1.0p-256
>
Hi Eric,
On 5/6/25 21:51, Gustavo Romero wrote:
Hi Eric,
On 5/6/25 12:58, Eric Auger wrote:
Hi Gustavo,
On 5/5/25 3:26 PM, Gustavo Romero wrote:
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
This series enables APCI PCI hotplug/hotunplug on ARM
and makes it default for 10.1 machine type. Th
Hi Richard,
On Wed, May 7, 2025 at 1:50 AM Richard Henderson
wrote:
>
> On 5/6/25 08:26, WANG Rui wrote:
> > This patch fixes incorrect results for [xv]fnm{add,sub}.{s,d}
> > instructions when rounding toward zero, postive, negative.
> >
> > According to the LoongArch ISA specification, these ins
Hi Eric,
On 5/6/25 12:58, Eric Auger wrote:
Hi Gustavo,
On 5/5/25 3:26 PM, Gustavo Romero wrote:
Hi Eric,
On 4/28/25 07:25, Eric Auger wrote:
This series enables APCI PCI hotplug/hotunplug on ARM
and makes it default for 10.1 machine type. This aligns with
x86 q35 machine. Expected benefits
Maybe an assert is really more appropriate, but technically doing so on
actual hardware should run flawlessly so I think the emu should work too...
Maybe I'm wrong though
On Tue, May 6, 2025, 19:48 Daniel P. Berrangé wrote:
> On Tue, May 06, 2025 at 07:41:32PM +0300, Elisha Hollander wrote:
> >
On Thu, May 01, 2025 at 08:58:33AM -0700, Pierrick Bouvier wrote:
> On 5/1/25 7:28 AM, Peter Xu wrote:
> > On Wed, Apr 30, 2025 at 09:10:30AM -0700, Pierrick Bouvier wrote:
> > > On 4/29/25 8:21 AM, Thomas Huth wrote:
> > > > From: Thomas Huth
> > > >
> > > > We've got this nice vmstate-static-ch
On 5/6/25 7:22 AM, Peter Maydell wrote:
On Mon, 5 May 2025 at 10:12, Cédric Le Goater wrote:
From: Steven Lee
Introduce a new test suite for ast2700fc machine.
Rename the original test_aarch64_aspeed.py to
test_aarch64_aspeed_ast2700.py.
Signed-off-by: Steven Lee
Change-Id: I3855f55c9f6e5c
On 5/6/25 7:47 AM, Markus Armbruster wrote:
Shameer Kolothum via writes:
Although this change does not affect functionality at present, it lays
the groundwork for enabling user-created SMMUv3 devices in
future patches
Signed-off-by: Shameer Kolothum
---
hw/arm/smmuv3.c | 26
On 03.05.2025 10:58, Paolo Bonzini wrote:
Because LSS need not trigger an IRQ shadow, gen_movl_seg can't just use
the destination register to decide whether to inhibit IRQs. Add an
argument.
Cc: qemu-sta...@nongnu.org
This one does not apply cleanly (to 10.0) after 9a688e70bdb2f23112
"target/
On Tue, May 6, 2025 at 10:17 AM Thomas Huth wrote:
> On 06/05/2025 00.49, John Snow wrote:
> ...
> > If there are no objections to moving to 3.9 as the minimum, I certainly
> > don't mind. Go right ahead and I'll clean up afterwards as part of my
> > "delint qapi" series in which I'd like to fix
On Mon, May 5, 2025 at 8:19 AM Akihiko Odaki
wrote:
> sphinx 5.3.0 fails with Python 3.13.1:
>
> ../docs/meson.build:37: WARNING:
> /home/me/qemu/build/pyvenv/bin/sphinx-build:
> Extension error:
> Could not import extension sphinx.builders.epub3 (exception: No module
> named 'imghdr')
>
> ../doc
On 5/6/25 10:50, Richard Henderson wrote:
+ *(uint64_t *)&x = 0x4ff0UL;
+ *(uint64_t *)&y = 0x4ff0UL;
0x1.0p256
+ *(uint64_t *)&z = 0x2ff0UL;
0x1.0p-256
+
+ fesetround(FE_DOWNWARD);
+ asm("fnmsub.d %[x], %[x], %[y], %[z]\n\t"
+
From: Aleksandr Partanen
If we have request without lock and hit unlocked or invalid
entry during the search, we remap it immediately,
even if we have matching entry in next entries in bucket.
This leads to duplication of mappings of the same size,
and to possibility of selecting the wrong elemen
From: "Edgar E. Iglesias"
The following changes since commit a9e0c9c0f14e19d23443ac24c8080b4708d2eab8:
Merge tag 'pull-9p-20250505' of https://github.com/cschoenebeck/qemu into
staging (2025-05-05 11:26:59 -0400)
are available in the Git repository at:
https://gitlab.com/edgar.iglesias/qe
From: "Edgar E. Iglesias"
Today, we don't track write-abiliy in the cache, if a user
requests a readable mapping followed by a writeable mapping
on the same page, the second lookup will incorrectly hit
the readable entry.
Split mapcache_grants by ro and rw access. Grants will now
have separate w
On 06/05/2025 18.00, Daniel P. Berrangé wrote:
Since we deprecate and remove versioned machine types on a fixed
schedule, we can automatically ensure that the docs reflect the
latest version info, rather than requiring manual updates on each
dev cycle.
The first patch in this series removes the
On 5/6/25 08:26, WANG Rui wrote:
This patch fixes incorrect results for [xv]fnm{add,sub}.{s,d}
instructions when rounding toward zero, postive, negative.
According to the LoongArch ISA specification, these instructions perform
a fused multiply-add followed by a negation of the final result.
Pre
Apologies. I'm just fighting git. Much more used to just using github.com
and PRs, but I totally understand that different projects have their own
preferences. Hopefully v4 looks a bit better?
Is there anything else I need to do? What are the next steps? Just wait for
it to be merged?
Sorry, this
When running applications which make large (sparsely populated) address ranges
(e.g. when using address sanitizer with LibAFL) the inability to exclude these
regions from any core dump can result in very large files which fill the disk.
A coredump is obvously very useful for performing a post-morte
USB NICs have a "40:" prefix hardcoded for all MAC addresses.
This overrides user-provided configuration and leads to an inconsistent
experience.
I couldn't find any documented reason (comment or git commits) for this
behavior. It seems like everyone is just expecting the MAC address to be
fully
On 06/05/2025 17.31, Pierrick Bouvier wrote:
On 5/6/25 2:33 AM, Daniel P. Berrangé wrote:
On Mon, May 05, 2025 at 10:46:52AM -0700, Pierrick Bouvier wrote:
On 5/5/25 3:32 AM, Thomas Huth wrote:
On 03/05/2025 22.18, Pierrick Bouvier wrote:
Allows all tests to be visible by default when using m
On Fri, 2 May 2025 08:57:36 -0700
Fan Ni wrote:
> On Fri, May 02, 2025 at 10:01:55AM +0100, Jonathan Cameron wrote:
> > On Thu, 1 May 2025 20:21:56 +
> > Fan Ni wrote:
> >
> > > On Thu, Apr 24, 2025 at 11:42:59AM +0100, Jonathan Cameron wrote:
> > > > On Mon, 17 Mar 2025 16:31:30 +
On Mon, 5 May 2025 16:40:18 +
Anisa Su wrote:
> On Thu, Apr 24, 2025 at 12:19:59PM +0100, Jonathan Cameron wrote:
> > On Mon, 17 Mar 2025 16:31:35 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Se
On Tue, May 06, 2025 at 05:46:02PM +0100, WorksButNotTested wrote:
> When running applications which make large (sparsely populated) address ranges
> (e.g. when using address sanitizer with LibAFL) the inability to exclude these
> regions from any core dump can result in very large files which fill
On Tue, May 06, 2025 at 07:41:32PM +0300, Elisha Hollander wrote:
> Gave an example for a case where QEMU would try to allocate 0 bytes thus
> fail here in the original version of the patch.
>
> > As I mentioned earlier, let's say you don't initialize the vertical
> display end registers, and set
When running applications which make large (sparsely populated) address ranges
(e.g. when using address sanitizer with LibAFL) the inability to exclude these
regions from any core dump can result in very large files which fill the disk.
A coredump is obvously very useful for performing a post-morte
> As I mentioned earlier, let's say you don't initialize the vertical
display end registers, and set the minimum scanline register, the emulation
will then have to allocate some display buffer, but because the vertical
display end is initilized as 0 the buffer will be empty and the program
break.
Since the ctx->vill is only really applicable if the LMUL value is
set to an invalid state (4) we can free the tbflag up by just using
the LMUL field.
This was discussed in [1] as part of a way of extending the space in
tbflags to allow our big-endian work to have a bit in there.
Signed-off-by: B
Gave an example for a case where QEMU would try to allocate 0 bytes thus
fail here in the original version of the patch.
> As I mentioned earlier, let's say you don't initialize the vertical
display end registers, and set the minimum scanline register, the emulation
will then have to allocate some
On Tue, May 06, 2025 at 07:17:25PM +0300, Elisha Hollander wrote:
> Sorry for former patch something is messed up with my email.
The commit message needs to explain what problem is being solved by
making this change as allowing 0 bytes looks dubious on the surface.
>
> Signed-off-by: donno2048
On Tue, 6 May 2025, Markus Armbruster wrote:
Akihiko Odaki writes:
On 2025/02/06 18:48, Markus Armbruster wrote:
Akihiko Odaki writes:
[...]
I understand we have something like this:
* true: on if possible, else off
* false: off (always possible)
Which one is the default?
It depends
Sorry for former patch something is messed up with my email.
Signed-off-by: donno2048
---
util/memfd.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/util/memfd.c b/util/memfd.c
index 8a2e906..e96e5af 100644
--- a/util/memfd.c
+++ b/util/memfd.c
@@ -108,7 +108,7 @
Signed-off-by: donno2048
---
util/memfd.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/util/memfd.c b/util/memfd.c
index 8a2e906..e96e5af 100644
--- a/util/memfd.c
+++ b/util/memfd.c @@ -108,7 +108,7 @@ err:
void *qemu_memfd_alloc(const char *name, size_t size,
On 5/6/25 5:58 PM, Eric Auger wrote:
> Hi Gustavo,
>
> On 5/5/25 3:26 PM, Gustavo Romero wrote:
>> Hi Eric,
>>
>> On 4/28/25 07:25, Eric Auger wrote:
>>> This series enables APCI PCI hotplug/hotunplug on ARM
>>> and makes it default for 10.1 machine type. This aligns with
>>> x86 q35 machine. E
We deprecate versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the deprecated.rst document that always
has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 7 +++
docs/conf.py | 33 +++
This reverts commit c9fd2d9a48ee3c195cf83cc611b87b09f02f0013.
When we introduced the specialized machine type deprecation policy, we
allow automatic deprecation to take effect immediately, but blocked the
automatic deletion of machine types for 2 releases. This ensured we
complied with the histori
We remove versioned machine types on a fixed schedule. This allows us
to auto-generate a paragraph in the removed-features.rst document that
always has accurate version info.
Signed-off-by: Daniel P. Berrangé
---
docs/about/removed-features.rst | 10 ++
docs/conf.py|
Since we deprecate and remove versioned machine types on a fixed
schedule, we can automatically ensure that the docs reflect the
latest version info, rather than requiring manual updates on each
dev cycle.
The first patch in this series removes the hack which postponed
automatic removal of version
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