On 2025/4/29 下午10:04, Stefan Hajnoczi wrote:
Please take a look at the following CI failure:
Fail: The memory reads and writes count does not match.
Expected Reads: 114688, Actual Reads: 0
Expected Writes: 63488, Actual Writes: 32768
make[1]: *** [Makefile:202: run-plugin-memory-with-libmem.s
Hi,
On 13/2/25 13:37, Philippe Mathieu-Daudé wrote:
+AMD folks
On 12/2/25 23:01, Richard Henderson wrote:
Use out-of-line helpers to implement extended address memory ops.
With this, we can reduce TARGET_LONG_BITS to the more natural 32
for this 32-bit cpu.
I thought about something similar
On 4/29/25 10:40 PM, Thomas Huth wrote:
On 29/04/2025 21.48, Pierrick Bouvier wrote:
...
I'm not keen to have a default target set, but it's a personal opinion based
on fear of "implicit smart choice hurts", so I'll be happy to change my mind
with a good argument for it.
No default target, ple
> On 29.4.2025 07:17 CEST Marc-André Lureau wrote:
>
>
> Hi
>
> On Mon, Apr 28, 2025 at 4:08 PM Dietmar Maurer wrote:
> >
> > > In file included from /home/elmarco/src/qemu/include/ui/console.h:4,
> > > from ../system/runstate.c:54:
> > > /home/elmarco/src/qemu/include/ui/q
On 4/29/25 11:06 PM, Philippe Mathieu-Daudé wrote:
On 29/4/25 23:11, Pierrick Bouvier wrote:
On 4/29/25 11:01 AM, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 29/4/25 07:00, Pierrick Bouvier wrote:
Following what we did for hw/, we need target specific common libraries
for target. We need 2
On 30/4/25 00:02, Pierrick Bouvier wrote:
On 4/29/25 2:14 PM, Pierrick Bouvier wrote:
On 4/29/25 3:28 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
"linux/kvm.h" is not included for code compiled without
COMPILING_PER_TARGET, and headers are different depending architecture
(arm, arm64).
T
On 29/4/25 23:11, Pierrick Bouvier wrote:
On 4/29/25 11:01 AM, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 29/4/25 07:00, Pierrick Bouvier wrote:
Following what we did for hw/, we need target specific common libraries
for target. We need 2 different libraries:
- code common to a base archite
On 30/04/2025 02.00, Nicholas Piggin wrote:
On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
On 08/04/2025 14.45, Nicholas Piggin wrote:
The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the
On 29/04/2025 21.48, Pierrick Bouvier wrote:
...
I'm not keen to have a default target set, but it's a personal opinion based
on fear of "implicit smart choice hurts", so I'll be happy to change my mind
with a good argument for it.
No default target, please! We've seen this with the default ma
Provide a system reset vector and handle it similar to hmp_system_reset
We don't use a QMP related shutdown reason because the mcdserver is
implemented independent of the used communication protocol.
(In fact, another communication protocol implementation for MCD already
exists and can be found at
Currently, only global stop is implemented
Signed-off-by: Mario Fleischmann
---
mcd/mcd_server.c | 74 +--
mcd/mcd_stub.c | 52
qapi/mcd.json| 100 +++
3 files changed, 222 insertions(+),
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 7 ---
include/exec/gdbstub.h | 8 +++-
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 565f6b3..291ac55 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -48,1
This commit implements the necessary operations required to establish
a connection with the MCD server:
* query information about the server
* connect to "
* disconnect from "
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 13 +++
mcd/mcd_qapi.h | 2 +
mcd/mcd_server.c
In MCD, core-specific operations require an open connection to the core.
This commit implements the necessary operations to open and close the
connection to cores.
Signed-off-by: Mario Fleischmann
---
mcd/mcd_server.c | 176 +++---
mcd/mcd_stub.c | 129 +
Depending on the VM and CPU state, core states can be queried:
* MCD_CORE_STATE_DEBUG: VM halted or CPU artifically stopped
* MCD_CORE_STATE_RUNNING: VM and CPU running
* MCD_CORE_STATE_HALTED: CPU suspended
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 16 ++
mcd/mcd_qa
qtest_qmp provides a convenient way to automatically serialize into the
client JSON protocol and to send the command to the QMP socket.
Since qtest has a strong dependency to the QMP monitor, a minimal number
of function has been added to mcd-test.c for interoperability with MCD's
protocol.
Signed
In MCD, the target system is divided into system, devices and cores:
[ system ] 1-* [ devices ] 1-* [cores]
This commit implements the necessary functions to query information
about the target system.
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 48 ++
mcd/mcd_qapi.h
The MCD implementation follows a remote procedure call approach:
Each function from mcd_api.h will correspond to one command in mcd.json.
Signed-off-by: Mario Fleischmann
---
MAINTAINERS | 1 +
docs/interop/mcd.rst | 13 +
mcd/meson.build | 27 +
The target initialization API ensures that the requested and provided
MCD versions are compatible.
* implement mcd_initialize_f and mcd_qry_error_info_f in mcdserver
* implement QMP stub functionality
* add QTest
Thanks to the QMP integration in QTest, function arguments and results
can be (de)se
Directly map MCD register groups to GDB features lists
Signed-off-by: Mario Fleischmann
---
mcd/mcd_qapi.c | 48 +++
mcd/mcd_qapi.h | 8 ++
mcd/mcd_server.c | 237 +++--
mcd/mcd_stub.c | 93 +
qapi/mcd.json |
This patch series introduces support for the Multi-Core Debug (MCD) API, a
commonly used debug interface by emulators. The MCD API, defined through a
header file, consists of 54 functions for implementing debug and trace.
However, since it is a header-file-only interface, MCD does not specify a
com
MCD's trigger API functions support multiple triggers by expecting a pointer
to the trigger instance. Each trigger structure reserves the first four bytes
for its size. To get the specific structure, read a uint32_t at passed pointer
and compare it to the sizes of known trigger structures.
This ap
The MCD implementation follows a remote procedure call approach
and will use a client JSON protocol for communication.
While the MCD server implements the MCD API, the server stub will be
responsible for handling the JSON connection and for dispatching the
corresponding server functions.
Signed-o
gdbstub: abort gdb_set_stop_cpu when step is issued by mcdserver
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 6 ++-
mcd/mcd_server.c | 115 ++
mcd/mcd_stub.c| 18
qapi/mcd.json | 38 ++-
4 files changed, 16
To keep the MCD JSON protocol separate from QMP, a custom monitor has been
implemented in mcd_monitor.c which can be run in parallel to the QMP monitor.
It is responsible for handling the JSON communication and for dispatching
the corresponding functions in mcd_stub.c
The MCD server stub will call
Signed-off-by: Mario Fleischmann
---
gdbstub/gdbstub.c | 2 +-
include/exec/gdbstub.h | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index 291ac55..6ace944 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -527,7
In MCD, all accesses to register or memory are issued over transaction lists.
This commit implements three types of transactions:
* register access
* logical memory access (with MMU)
* physical memory access (no MMU)
In contrast to GDB's remote serial protocol, MCD supports specifying an
access w
Support three main memory space types:
* Physical memory
* Logical memory (MMU)
* GDB Registers
Use custom memory type to mark memory spaces as secure
V=1 QTEST_QEMU_BINARY="./qemu-system-arm -M virt,secure=on -cpu cortex-a15"
tests/qtest/mcd-test
Signed-off-by: Mario Fleischmann
---
mcd/mcd
Signed-off-by: Mario Fleischmann
---
docs/interop/mcd.rst | 6 ++
meson.build | 1 +
meson_options.txt | 3 +++
scripts/meson-buildoptions.sh | 3 +++
4 files changed, 13 insertions(+)
diff --git a/docs/interop/mcd.rst b/docs/interop/mcd.rst
index 9587c
Hi, all:
Currently info mtre prints the memory-region hierarchy using two spaces as
indentation, which is not very clear when there are too many nodes.
```
(qemu) info mtree
memory-region: system
- (prio 0, i/o): system
1000- (pri
Make the hierarchical relationship between nodes clearer by adding characters
Signed-off-by: Chao Liu
---
system/memory.c | 34 +++---
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/system/memory.c b/system/memory.c
index 71434e7ad0..e723928068 100644
在 2025/4/30 上午11:04, Bibo Mao 写道:
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled when system power on,
the first PC i
On 4/29/25 08:56, Nabih Estefan wrote:
v2: used ldl_le_p and lduw_l_p instead of memcpy as per upstream
suggestion.
```
../tests/qtest/libqos/igb.c:106:5: runtime error: load of misaligned address
0x562040be8e33 for type 'uint32_t', which requires 4 byte alignment
```
Instead of straight castin
On 4/29/25 08:39, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (4):
hw/arm/virt: Update comment about Multiprocessor Affinity Register
hw/arm/virt: Remove deprecated virt-3.0 machine
hw/arm/virt: Remove deprecated virt-3.1 machine
hw/arm/virt: Remove deprecated virt-4.0 machin
On 4/29/25 14:35, Alistair Francis wrote:
On Sat, Apr 26, 2025 at 3:36 AM Jonathan Cameron via
wrote:
On Tue, 22 Apr 2025 12:26:55 -0700
Richard Henderson wrote:
Recover two bits from the inline flags.
Hi Richard,
Early days but something (I'm fairly sure in this patch) is tripping up m
On 2025/3/26 下午7:40, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel,
the initrd is loaded in the ram. If the initrd size is too large,
the loading fails, resulting in a VM startup failure.
This patch first loads initrd near the kernel.
When the nearby memory
On Wed Apr 30, 2025 at 7:09 AM AEST, BALATON Zoltan wrote:
> On Tue, 29 Apr 2025, Alex Bennée wrote:
>> BALATON Zoltan writes:
>>> On Tue, 29 Apr 2025, Alex Bennée wrote:
BALATON Zoltan writes:
> On Mon, 28 Apr 2025, Richard Henderson wrote:
>> On 4/28/25 06:26, BALATON Zoltan wrote:
On Wed Apr 23, 2025 at 8:09 PM AEST, Ben Dooks wrote:
> In adding a new feature to the riscv target, it turns out the tb_flags
> had already got to the 32-bit limit. Everyone other target has been
> fine with uint32_t (except perhaps arm which does somethng strange to
> extend tb_flags, I think).
>
On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
> On 08/04/2025 14.45, Nicholas Piggin wrote:
>> The per-core SCRATCH0-7 registers are shared between big cores, which
>> was missed in the big-core implementation. It is difficult to model
>> well with the big-core == 2xPnvCore scheme we move
On Tue, Apr 29, 2025 at 4:20 PM Joel Stanley wrote:
>
> This is a set of cleanups for the riscv virt machine device tree
> generation that apply on top of Daniel's recent series.
>
> Using dumpdtb the old and new device trees are identical for -M virt and
> -M virt,aia=aplic-imsic.
>
> The final p
On Mon, Apr 28, 2025 at 05:39:46PM +0200, Cédric Le Goater wrote:
> > +static void vfio_device_get_all_region_info(VFIODevice *vbasedev)
> > +{
> > +struct vfio_region_info *info;
> > +int i;
> > +
> > +for (i = 0; i < vbasedev->num_regions; i++) {
> > +vfio_device_get_region_i
On Tue, Apr 29, 2025 at 05:21:40PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> For automatic tests, we need reference files from older QEMU versions.
> QEMU 7.2 is a long term stable release, so it's a good candidate for
> checking whether the migration could still work correctly. Let's add
On Tue, Apr 29, 2025 at 05:21:39PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> ghes_addr_le has been renamed to hw_error_le in commit 652f6d86cbb
> ("acpi/ghes: better name the offset of the hardware error firmware").
> Adjust the checker script to allow that changed field name.
>
> Signed
On Tue, Apr 29, 2025 at 05:21:38PM +0200, Thomas Huth wrote:
> From: Thomas Huth
>
> These files reference QEMU machine types that have already been
> removed and thus are of no use anymore.
>
> Signed-off-by: Thomas Huth
I never noticed these files, but when looking it seems to me these two
d
On 4/29/25 2:14 PM, Pierrick Bouvier wrote:
On 4/29/25 3:28 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
"linux/kvm.h" is not included for code compiled without
COMPILING_PER_TARGET, and headers are different depending architecture
(arm, arm64).
Thus we need to manually expose some definit
On Sat, Apr 26, 2025 at 3:36 AM Jonathan Cameron via
wrote:
>
> On Tue, 22 Apr 2025 12:26:55 -0700
> Richard Henderson wrote:
>
> > Recover two bits from the inline flags.
>
>
> Hi Richard,
>
> Early days but something (I'm fairly sure in this patch) is tripping up my
> favourite
> TCG corner ca
On 4/30/25 00:19, Alex Bennée wrote:
>> This change makes QEMU to crash.
> What is your command line to cause the crash?
I applied this patch on top of native context v11, ran AMD nctx and got a crash
on SDDM startup.
(gdb) bt
#0 0x75411b54 in __pthread_kill_implementation () at /lib64/
Dmitry Osipenko writes:
> On 4/28/25 15:59, Alex Bennée wrote:
>> From: Manos Pitsidianakis
>>
>> This commit fixes an indefinite hang when using VIRTIO GPU blob objects
>> under TCG in certain conditions.
>>
>> The VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB VIRTIO command creates a
>> MemoryRegion and
On 4/29/25 3:28 AM, Alex Bennée wrote:
Pierrick Bouvier writes:
"linux/kvm.h" is not included for code compiled without
COMPILING_PER_TARGET, and headers are different depending architecture
(arm, arm64).
Thus we need to manually expose some definitions that will
be used by target/arm, ensurin
On 4/29/25 11:01 AM, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 29/4/25 07:00, Pierrick Bouvier wrote:
Following what we did for hw/, we need target specific common libraries
for target. We need 2 different libraries:
- code common to a base architecture
- system code common to a base archit
On Tue, 29 Apr 2025, Alex Bennée wrote:
BALATON Zoltan writes:
On Tue, 29 Apr 2025, Alex Bennée wrote:
BALATON Zoltan writes:
On Mon, 28 Apr 2025, Richard Henderson wrote:
On 4/28/25 06:26, BALATON Zoltan wrote:
I have tried profiling the dst in real card vfio vram with dcbz
case (with 100
On Tue, Apr 29, 2025 at 05:56:54PM +0200, Kevin Wolf wrote:
> Block devices that don't support discard have a discard_granularity of
> 0. Currently, this results in a division by zero when we try to make
> sure that it's a multiple of request_alignment. Only try to update
> bs->bl.pdiscard_alignmen
On Thu, Mar 27, 2025 at 10:12:34AM +0800, Li Zhijian wrote:
> Recently, we removed ipv6 restriction[0] from RDMA migration, add a
> test for it.
>
> [0]
> https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
>
> Cc: Jack Wang
> Cc: Michael R. Galaxy
> Cc: Peter Xu
>
On 4/29/25 12:13 AM, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 29/4/25 06:59, Pierrick Bouvier wrote:
On MacOS x86_64:
In file included from ../target/i386/hvf/x86_task.c:13:
/Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type
name 'vaddr'
vaddr pc;
^
/U
On 4/29/25 5:26 AM, Anton Johansson wrote:
On 29/04/25, Pierrick Bouvier wrote:
Remove TARGET_BIG_ENDIAN dependency.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/ar
On 4/29/25 10:03 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Add a simple qdev test to check that allocated properties get free with
get freed
the object. This test exhibited array leaks before the fixes.
Signed-off-by: Marc-André Lureau
---
tests/unit/test-qdev.c
On 4/29/25 10:03 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Fix a memory leak, and allow it to be called multiple times safely.
Signed-off-by: Marc-André Lureau
---
hw/core/qdev-properties.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff
On 4/29/25 10:03 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
So it can eventually be called multiple times safely.
Signed-off-by: Marc-André Lureau
---
backends/tpm/tpm_util.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/backends/tpm/tpm_util.c b/backends/tpm/t
On 4/29/25 10:03 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
So it can eventually be called multiple times safely.
Signed-off-by: Marc-André Lureau
---
hw/core/qdev-properties-system.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/core/qdev-properties-system.
On Tue, 29 Apr 2025, Alex Bennée wrote:
Richard Henderson writes:
On 4/29/25 08:27, Alex Bennée wrote:
- 45.16% rr_cpu_thread_fn
Hmm you seem to be running in icount mode here for some reason.
For some reason ppc32 does not enable mttcg.
I'm not sure what's missing to enabl
On 4/29/25 10:03 AM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
So it can eventually be called multiple times safely.
Signed-off-by: Marc-André Lureau
---
hw/core/qdev-properties.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/core/qdev-propert
On 4/22/25 8:48 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
+ if ((ret < 0) || (!ret && !dte_mode)) {
+ /*
+ * The DTE could not be retrieved, it is not valid, or it is
not setup
+ * for paging. In either case, ensure that if pagin
From: Percival Foss
This test utilizes pegasos2 to show the cross page overflow bug on 32 bit
systems. We patch the firmware
image to cause the overflow. The instructions to do this are as follows:
li r3, 0
li r4, -1
lwz r5, 0x0(r4)
lwz r5, 0x0(r3)
This test will add an invalid translation when
Since v1:
-Updated git commits to have proper signed off by tags/messages
Our company found and fixed a bug in TCG that caused 32 bit guests
running on 64 bit hosts to crash. If a 32 bit host has a page
translation that crosses beyond the last page. This causes a invalid
translation to be added to
From: Percival Foss
The bug being resolved is that the current code in mmu_lookup() assumes
a valid 64-bit address space. If a guest has a 32-bit address space, a
page translation that crosses beyond the last page in the address space
will overflow out of the allocated guest virtual memory space
On 4/29/25 12:57 PM, Pierrick Bouvier wrote:
On 4/29/25 2:35 AM, Philippe Mathieu-Daudé wrote:
If a distro wants to name a binary 'qemu-kvm' it can drop the
-target option and hard-wire its target_info() to a distro-specific
TargetInfo implementation, or &target_info_x86_64_system.
Having upd
On 4/28/25 23:39, Philippe Mathieu-Daudé wrote:
On 28/4/25 22:10, Richard Henderson wrote:
This function is only relevant to tcg.
Move it to a tcg-specific file.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 97 -
target/riscv/tcg/tcg-
On 4/29/25 2:35 AM, Philippe Mathieu-Daudé wrote:
If a distro wants to name a binary 'qemu-kvm' it can drop the
-target option and hard-wire its target_info() to a distro-specific
TargetInfo implementation, or &target_info_x86_64_system.
Having updated my Debian stable to next stable (trixie)
On 4/28/25 23:44, Philippe Mathieu-Daudé wrote:
On 28/4/25 22:10, Richard Henderson wrote:
Initialize all instances with cpu_reset(), so that there
is no functional change.
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 2 ++
accel/tcg/cpu-exec.c | 3 ++-
target/
On 4/29/25 2:20 AM, Thomas Huth wrote:
On 29/04/2025 10.23, Markus Armbruster wrote:
...
I don't wish to derail this thread, but we've been dancing around the
question of how to best fix the target for some time. I think we should
talk about it for real.
Sure, and no problem about that, that
On 4/22/25 8:38 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the
address and size of the invalidation and sync the guest page table state
with the host. This requires walking the guest page table an
On 4/29/25 1:37 AM, Daniel P. Berrangé wrote:
On Tue, Apr 29, 2025 at 09:43:24AM +0200, Markus Armbruster wrote:
Pierrick Bouvier writes:
After looking at the introspection code, I don't see any major blocker.
We need to keep some of existing "if", as they are based on config-host,
and should
On 4/29/25 12:43 AM, Markus Armbruster wrote:
Pierrick Bouvier writes:
On 4/25/25 11:21 PM, Markus Armbruster wrote:
Trouble is some uses of the second kind are in QAPI conditionals. I can
see three options:
(1) Drop these conditionals.
(2) Replace them by run-time checks.
(3) Have target
On 4/29/25 11:55 AM, Richard Henderson wrote:
On 4/28/25 15:37, Richard Henderson wrote:
On 4/28/25 15:26, Pierrick Bouvier wrote:
On 4/28/25 3:07 PM, Richard Henderson wrote:
On 4/28/25 15:00, Pierrick Bouvier wrote:
On 4/28/25 1:10 PM, Richard Henderson wrote:
diff --git a/include/accel/tc
On 4/28/25 15:59, Alex Bennée wrote:
> Seeing as I've taken a few patches to here now I might as well put
> myself forward to maintain virtio-gpu. I've marked it as Odd Fixes as
> it's not my core focus. If someone with more GPU experience comes
> forward we can always update again.
>
> Signed-of
On 4/28/25 15:37, Richard Henderson wrote:
On 4/28/25 15:26, Pierrick Bouvier wrote:
On 4/28/25 3:07 PM, Richard Henderson wrote:
On 4/28/25 15:00, Pierrick Bouvier wrote:
On 4/28/25 1:10 PM, Richard Henderson wrote:
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index
On 4/28/25 15:59, Alex Bennée wrote:
> From: Manos Pitsidianakis
>
> This commit fixes an indefinite hang when using VIRTIO GPU blob objects
> under TCG in certain conditions.
>
> The VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB VIRTIO command creates a
> MemoryRegion and attaches it to an offset on a PCI
On 4/29/25 01:51, Philippe Mathieu-Daudé wrote:
VMSTATE_CPU() is only used in 4 places and doesn't provide
much, directly inline it using VMSTATE_STRUCT().
This removes the last COMPILING_PER_TARGET in "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 1
Hi Pierrick,
On 29/4/25 07:00, Pierrick Bouvier wrote:
Following what we did for hw/, we need target specific common libraries
for target. We need 2 different libraries:
- code common to a base architecture
- system code common to a base architecture
For user code, it can stay compiled per targ
Richard Henderson writes:
> On 4/29/25 08:27, Alex Bennée wrote:
>>> - 45.16% rr_cpu_thread_fn
>> Hmm you seem to be running in icount mode here for some reason.
>
> For some reason ppc32 does not enable mttcg.
> I'm not sure what's missing to enable it properly.
I seem to recall
BALATON Zoltan writes:
> On Tue, 29 Apr 2025, Alex Bennée wrote:
>> BALATON Zoltan writes:
>>> On Mon, 28 Apr 2025, Richard Henderson wrote:
On 4/28/25 06:26, BALATON Zoltan wrote:
> I have tried profiling the dst in real card vfio vram with dcbz
> case (with 100 iterations instead
On Thu, Apr 24, 2025 at 11:11:31AM +0100, Jonathan Cameron wrote:
> On Mon, 17 Mar 2025 16:31:28 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > Add supported_blk_size field to CXLDCRegion struct in preparation for
> > next patch. It is needed by command 0x5600 Get DC Region Co
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 260dd461bd..9e004fb511 100644
-
This variable is no longer used outside tcg-target.c.inc.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-has.h | 6 --
tcg/sparc64/tcg-target.c.inc | 6 --
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/tcg/sparc64/tcg-tar
or-upstream' of https://repo.or.cz/qemu/kevin into staging
(2025-04-27 12:47:23 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250429
for you to fetch changes up to 70ab4f4ed9bbe9bcfdb105681291b4695f151522:
tcg/sparc64: Implement CTP
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 37 ++
tcg/aarch64/tcg-target.c.inc | 52 +++---
tcg/arm/tcg-target.c.inc | 72 +--
tcg/i386/tcg-target.c.inc| 114 ++--
On 4/29/25 08:27, Alex Bennée wrote:
- 45.16% rr_cpu_thread_fn
Hmm you seem to be running in icount mode here for some reason.
For some reason ppc32 does not enable mttcg.
I'm not sure what's missing to enable it properly.
r~
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On Wed, Apr 02, 2025 at 07:13:06AM +0200, Jack Wang wrote:
> I hit following error which testing migration in pure RoCE env:
> "-incoming rdma:[::]:8089: RDMA ERROR: You only have RoCE / iWARP devices in
> your
> systems and your management software has specified '[::]', but IPv6 over RoCE
> /
>
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
On 4/29/25 3:12 AM, Joel Stanley wrote:
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/virt.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
On 4/29/25 3:12 AM, Joel Stanley wrote:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits
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