On 29/4/25 08:24, Wei Liu wrote:
Include exec/target_page.h to fix the following build error.
x86_64-softmmu.a.p/target_i386_hvf_hvf.c.o -c ../target/i386/hvf/hvf.c
../target/i386/hvf/hvf.c:139:49: error: use of undeclared identifier
'TARGET_PAGE_SIZE'
139 | uint64_t dirty_page_s
(merged as commit 9728fb5c22a)
On 21/5/24 03:30, Nicholas Piggin wrote:
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU regis
On 28/4/25 22:10, Richard Henderson wrote:
Test for the hook being present instead of ifdef TARGET_I386.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 28/4/25 22:10, Richard Henderson wrote:
Initialize all instances with cpu_reset(), so that there
is no functional change.
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 2 ++
accel/tcg/cpu-exec.c| 3 ++-
target/alpha/cpu.c | 1 +
target/arm/cpu.c
On 28/4/25 22:10, Richard Henderson wrote:
Move set_helper_retaddr and clear_helper_retaddr
to a new header file.
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ldst.h | 34 ---
include/accel/tcg/helper-retaddr.h | 43 ++
acc
On 28/4/25 22:10, Richard Henderson wrote:
This function is only relevant to tcg.
Move it to a tcg-specific file.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 97 -
target/riscv/tcg/tcg-cpu.c | 98 ++
On Tue, 2025-04-29 at 00:10 +0800, Tomita Moeko wrote:
> CAUTION: External Email!!
> x-igd-gms is used for overriding DSM region size in GGC register in
> both config space and MMIO BAR0, by default host value is used.
> There is no need to emulate it in default case.
>
> Signed-off-by: Tomita Mo
v1:
Add initial support for AST27x0
The purpose of vbootrom here is to simulate the work of BootMCU SPL (riscv)
in AST2700, because QEMU doesn't support heterogenous architecture yet.
ast27x0_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for
ASPEED AST27x0 BMC SOC. It currently
The boot ROM is a minimal implementation designed to load an AST27x0 boot image.
Its source code is available at:
https://github.com/google/vbootrom
Commit id: d6e3386709b3e49322a94ffadc2aaab9944ab77b
Build Information:
```
Build Date : Apr 29 2025 01:23:18
FW Version : git-d6e3386
```
Signed-off-
Include exec/target_page.h to fix the following build error.
x86_64-softmmu.a.p/target_i386_hvf_hvf.c.o -c ../target/i386/hvf/hvf.c
../target/i386/hvf/hvf.c:139:49: error: use of undeclared identifier
'TARGET_PAGE_SIZE'
139 | uint64_t dirty_page_start = gpa & ~(TARGET_PAGE_SIZE - 1u
On Tue, Apr 01, 2025 at 09:01:42AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:42 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 32/55] i386/tdx: implement tdx_cpu_instance_init()
> X-Mailer: git-send-email 2.34.1
>
> Currently, pmu is not supported for TDX by KVM.
>
> Signed-off-by:
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
On Tue, Apr 01, 2025 at 09:01:41AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:41 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 31/55] i386/cpu: introduce
> x86_confidential_guest_cpu_instance_init()
> X-Mailer: git-send-email 2.34.1
>
> To allow execute confidential guest specific c
Signed-off-by: Joel Stanley
---
hw/riscv/virt.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cd19c266e62a..1162b3a4b71a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -80,27 +80,27 @
The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.
Signed-off-by: Joel Stanley
---
hw/riscv/virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 17a790821484..e4c0ac8a2a9a 100644
--- a
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
---
hw/riscv/virt.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 873d41d10c70..ed28bc06114a 100644
--
There are cases where we do not want the memory layout of a texture to
be tiled as the component processing the texture would not know how to
de-tile either via software or hardware. Therefore, ensuring that the
memory backing the texture has a linear layout is absolutely necessary
in these situati
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.
Signed-off-by: Joel Stanley
---
hw/riscv/virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 17a790821484..e4c0ac8a2a9a 100644
--- a
This is a set of cleanups for the riscv virt machine device tree
generation that apply on top of Daniel's recent series.
Using dumpdtb the old and new device trees are identical for -M virt and
-M virt,aia=aplic-imsic.
The final patch is not meant for merging, but demonstrates bugs in the
existi
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
In cases where the scanout buffer is provided as a texture (e.g. Virgl)
we need to check to see if it has a linear memory layout or not. If
it doesn't have a linear layout, then blitting it onto the texture
associated with the display surface (which already has a linear layout)
seems to ensure that
In the specific case where the display layer (virtio-gpu) is using
dmabuf, and if remote clients are enabled (-spice gl=on,port=),
it makes sense to limit the maximum (streaming) rate to 60 FPS
using the GUI timer. This matches the behavior of GTK UI where the
display updates are submitted at 6
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
Giving users an option to choose a particular codec will enable
them to make an appropriate decision based on their hardware and
use-case.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Dmitry Osipenko
Cc: Frediano Ziglio
Cc: Dongwon Kim
Signed-off-by: Vivek Kasireddy
---
qemu-options.hx | 5
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Signed-off-by: Joel Stanley
-
Since most encoders/decoders (invoked by Spice) may not work with
tiled memory associated with a texture, we need to create another
texture that has linear memory layout and use that instead.
Note that, there does not seem to be a direct way to indicate to the
GL implementation that a texture's ba
To address the limitation that this option is incompatible with
remote clients, this patch series adds an option to select a
preferred codec and also enable gl=on option for clients that
are connected via the network. In other words, with this option
enabled (and the below linked Spice series merge
Newer versions of Spice server should be able to accept dmabuf
fds from Qemu for clients that are connected via the network.
In other words, when this option is enabled, Qemu would share
a dmabuf fd with Spice which would encode and send the data
associated with the fd to a client that could be loc
Hi Cedric,
> Cc: Troy Lee ; nabiheste...@google.com
> Subject: Re: [PATCH v7 1/1] pc-bios: Add AST27x0 vBootrom
>
> Hello Jamin,
>
> On 4/29/25 03:59, Jamin Lin wrote:
> > The boot ROM is a minimal implementation designed to load an AST27x0
> boot image.
> > Its source code is available at:
> >
Hello Jamin,
On 4/29/25 03:59, Jamin Lin wrote:
The boot ROM is a minimal implementation designed to load an AST27x0 boot image.
Its source code is available at:
https://github.com/google/vbootrom
Commit id: d6e3386709b3e49322a94ffadc2aaab9944ab77b
Build Information:
```
Build Date : Apr 29 2025
> > What I'm a bit hesitant about is that, if different arches add similar
> > "conditional" enumerations later, it could cause the enumeration values
> > to change under different compilation conditions (correct? :-)). Although
> > it might not break anything, since we don't rely on the specific n
Steven Sistare writes:
> On 4/28/2025 4:04 AM, Markus Armbruster wrote:
>> Steven Sistare writes:
>>
>>> On 4/9/2025 3:39 AM, Markus Armbruster wrote:
Hi Steve, I apologize for the slow response.
Steve Sistare writes:
> Using qom-list and qom-get to get all the nodes an
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v4 3/3] intel_iommu: Take the VTD lock when looking for and
>creating address spaces
>
>Hi Zhenzhong,
>
>On 28/04/2025 10:55 am, Duan, Zhenzhong wrote:
>> Caution: External email. Do not open attachments or click links
Eric Blake writes:
> On Mon, Apr 28, 2025 at 01:59:00AM +0300, Nir Soffer wrote:
>> When the `read-zeroes` is set, reads produce zeroes, and block status
>> return BDRV_BLOCK_ZERO, emulating a sparse image.
>>
>> If we don't set `read-zeros` we report BDRV_BLOCK_DATA, but image data
>> is undefi
On 4/29/2025 11:02 AM, Ewan Hai wrote:
Hi Community,
This email contains 3 bugs appear to share the same root cause.
[1] We ran into the following warnings when running QEMU v10.0.0 in TCG
mode:
qemu-system-x86_64 \
-machine q35 \
-m 4G -smp 4 \
-kernel ./arch/x86/boot/bzImage \
Eric Blake writes:
> From: "Richard W.M. Jones"
>
> Add multi-conn option to the NBD client. This commit just adds the
> option, it is not functional.
>
> Setting this to a value > 1 permits multiple connections to the NBD
> server; a typical value might be 4. The default is 1, meaning only a
On 29/4/25 06:59, Pierrick Bouvier wrote:
On MacOS x86_64:
In file included from ../target/i386/hvf/x86_task.c:13:
/Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type
name 'vaddr'
vaddr pc;
^
/Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown
On Fri, 25 Apr 2025 at 22:03, Daniel Henrique Barboza
wrote:
>
>
>
> On 4/24/25 6:41 AM, Joel Stanley wrote:
> > On Wed, 23 Apr 2025 at 20:39, Daniel Henrique Barboza
> > wrote:
> >>
> >> We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt
> >> strings for uint64_t and hwaddr
On Fri, 25 Apr 2025 at 21:23, Daniel Henrique Barboza
wrote:
>
>
>
> On 4/24/25 6:51 AM, Joel Stanley wrote:
> > On Wed, 23 Apr 2025 at 20:37, Daniel Henrique Barboza
> > wrote:
> >>
> >> Throughout the code we're accessing the board memmap, most of the time,
> >> by accessing it statically via '
On 29/04/2025 02.17, Alexey Kardashevskiy wrote:
The recent kernel update 8a141be3233af7d broke the headers update,
fix it in the script.
Thanks, but the same patch is already on the list:
https://lore.kernel.org/qemu-devel/20250425052401.8287-2-rre...@linux.ibm.com/
Or we want both __ASSEMB
The reset performed by subcode 3 of the diag308 instruction specifies
that system memory should be reset. This patch implements that
behaviour.
Introduce S390_RESET_REIPL_CLEAR to differentiate between subcode 3 and
subcode 4 resets.
When doing a clear reset, discard the ramblock containing the s
Hi
On Mon, Apr 28, 2025 at 4:08 PM Dietmar Maurer wrote:
>
> > In file included from /home/elmarco/src/qemu/include/ui/console.h:4,
> > from ../system/runstate.c:54:
> > /home/elmarco/src/qemu/include/ui/qemu-pixman.h:10:10: fatal error:
> > pixman.h: No such file or directory
>
Remove TARGET_BIG_ENDIAN dependency.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e7a15ade8b4..85e886944f6 100644
--- a/target/arm/cpu.c
+++ b/target/arm
"linux/kvm.h" is not included for code compiled without
COMPILING_PER_TARGET, and headers are different depending architecture
(arm, arm64).
Thus we need to manually expose some definitions that will
be used by target/arm, ensuring they are the same for arm amd aarch64.
As well, we must but pruden
Following what we did for hw/, we need target specific common libraries
for target. We need 2 different libraries:
- code common to a base architecture
- system code common to a base architecture
For user code, it can stay compiled per target for now.
Signed-off-by: Pierrick Bouvier
---
meson.b
Other accelerators define a CONFIG_{accel}_IS_POSSIBLE when
COMPILING_PER_TARGET is not defined, except hvf.
Without this change, target/arm/cpu.c can't find hvf_enabled.
Signed-off-by: Pierrick Bouvier
---
include/system/hvf.h | 14 +-
accel/hvf/hvf-stub.c | 3 +++
accel/hvf/mes
On MacOS x86_64:
In file included from ../target/i386/hvf/x86_task.c:13:
/Users/runner/work/qemu/qemu/include/system/hvf.h:42:5: error: unknown type
name 'vaddr'
vaddr pc;
^
/Users/runner/work/qemu/qemu/include/system/hvf.h:43:5: error: unknown type
name 'vaddr'
vaddr saved_insn;
This function is called only under kvm_enabled(), so this is safe.
Previous commit took care to add kvm_arm_set_irq stub if needed.
We need to keep a CONFIG_KVM_IS_POSSIBLE guard because
this function uses KVM_ARM_IRQ_CPU_IRQ, KVM_ARM_IRQ_CPU_FIQ and
KVM_ARM_IRQ_TYPE_CPU which are only available i
Whem removing CONFIG_KVM from target/arm/cpu.c, we need more stubs.
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm-stub.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index 2b73d0598c1..2d369489543 100644
--- a/target/arm/kvm-s
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index c39ddc4427b..89e305eb56a 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,6 @@
ar
It could be squashed with commit introducing it, but I would prefer to
introduce target/arm/cpu.c first.
Signed-off-by: Pierrick Bouvier
---
target/arm/meson.build | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
i
Need to stub cpu64 finalize functions.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 2 --
target/arm/cpu32-stubs.c | 24
target/arm/meson.build | 11 +++
3 files changed, 31 insertions(+), 6 deletions(-)
create mode 100644 target/arm/cpu32-s
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 85e886944f6..48ebaf614ee 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1213,8 +1213,6 @@ static void arm_disas_set_info(CPUStat
From: Philippe Mathieu-Daudé
CPUARMState::pc is of type uint64_t.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
target/arm/internals.h | 6 +++---
target/arm/hyp_gdbstub.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
We have to be careful to expose struct kvm_vcpu_init only when kvm is
possible, thus the additional CONFIG_KVM_IS_POSSIBLE around
kvm_arm_create_scratch_host_vcpu.
Signed-off-by: Pierrick Bouvier
---
target/arm/kvm_arm.h | 84 ++-
target/arm/kvm-stub.c |
More work toward single-binary.
This series convert target/arm/cpu.c.
Built on {linux, windows, macos} x {x86_64, aarch64}
Fully tested on linux-x86_64
https://github.com/pbo-linaro/qemu/actions/runs/14722101993
Philippe Mathieu-Daudé (1):
target/arm: Replace target_ulong -> uint64_t for HWBrea
On Fri, 25 Apr 2025 at 23:37, Djordje Todorovic
wrote:
>
> Add a network device e1000e to the boston-aia board model.
> There is no pch_gbe emulation, so we add e1000e in slot 0 func 1,
> instead. We need to pass func to call pci_parse_devaddr to find
> out slot and func.
>
> Signed-off-by: Chao-y
On Mon, 28 Apr 2025 at 17:10, Paolo Bonzini wrote:
I think a typo has snuck into the subject here. s/TT/Thead/
>
> Reviewed-by: Alistair Francis
> Signed-off-by: Paolo Bonzini
> ---
> target/riscv/cpu.c | 61 +-
> 1 file changed, 28 insertions(+), 3
Hi Community,
We have observed that the 'ht' feature bit cannot be disabled when QEMU runs
with KVM acceleration.
qemu-system-x86_64 \
--enable-kvm \
-machine q35 \
-cpu host,-ht \
-smp 4 \
-m 4G \
-drive file=rootfs.img,format=raw \
-nographic \
-append 'console=ttyS0 root=/de
On Mon, Apr 28, 2025 at 8:47 PM Peter Maydell wrote:
>
> On Thu, 24 Apr 2025 at 09:57, Zhang Chen wrote:
> >
> > On Thu, Apr 3, 2025 at 10:23 AM Zhang Chen wrote:
> > >
> > > On Thu, Apr 3, 2025 at 2:43 AM Richard Henderson
> > > wrote:
> > > >
> > > > On 4/2/25 06:54, Zhang Chen wrote:
> > > >
On 4/29/25 11:02 AM, Ewan Hai wrote:
Hi Community,
This email contains 3 bugs appear to share the same root cause.
[1] We ran into the following warnings when running QEMU v10.0.0 in TCG mode:
qemu-system-x86_64 \
-machine q35 \
-m 4G -smp 4 \
-kernel ./arch/x86/boot/bzImage \
-
Hi Community,
This email contains 3 bugs appear to share the same root cause.
[1] We ran into the following warnings when running QEMU v10.0.0 in TCG mode:
qemu-system-x86_64 \
-machine q35 \
-m 4G -smp 4 \
-kernel ./arch/x86/boot/bzImage \
-bios /usr/share/ovmf/OVMF.fd \
-drive file=
Hi Cédric,
I may have misunderstood the otpmem machine option. Please correct me if I am
wrong.
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 28, 2025 7:01 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley
Hi,
Gentle ping on this patch.
Thanks,
Jim
On Wed, Apr 9, 2025 at 10:58 AM Jim Shu wrote:
>
> Sorry, I forgot to write v2 changes in cover-letter.
>
> Changes in v2:
> - Remove duplicated code in riscv_timer_stce_changed() function
> - Add sstc spec description in the commit log
>
>
> On Wed, A
The boot ROM is a minimal implementation designed to load an AST27x0 boot image.
Its source code is available at:
https://github.com/google/vbootrom
Commit id: d6e3386709b3e49322a94ffadc2aaab9944ab77b
Build Information:
```
Build Date : Apr 29 2025 01:23:18
FW Version : git-d6e3386
```
Signed-off-
v1:
Add initial support for AST27x0
The purpose of vbootrom here is to simulate the work of BootMCU SPL (riscv)
in AST2700, because QEMU doesn't support heterogenous architecture yet.
ast27x0_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for
ASPEED AST27x0 BMC SOC. It currently
On 4/28/25 6:10 PM, BALATON Zoltan wrote:
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
On 4/28/25 11:44 AM, BALATON Zoltan wrote:
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
On 4/28/25 3:31 AM, BALATON Zoltan wrote:
Since you are touching the lines using DEFINE_MACHINE it's a good
opportunit
Hi Jonathan,
I apologize for the delayed response; I have just returned from vacation.
On 16/04/2025 00:47, Jonathan Cameron wrote:
> On Mon, 7 Apr 2025 02:59:20 +
> "Zhijian Li (Fujitsu)" wrote:
>
>> Ping
>
> Sorry, I wrote half a reply but then lost it before sending
> - was still in m
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
On 4/28/25 11:44 AM, BALATON Zoltan wrote:
On Mon, 28 Apr 2025, Pierrick Bouvier wrote:
On 4/28/25 3:31 AM, BALATON Zoltan wrote:
Since you are touching the lines using DEFINE_MACHINE it's a good
opportunity to change the macro to be more general to
The recent kernel update 8a141be3233af7d broke the headers update,
fix it in the script.
Cc: Thomas Huth
Signed-off-by: Alexey Kardashevskiy
---
Or we want both __ASSEMBLY__ and __ASSEMBLER__?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8a141be3233af7d
---
sc
On 4/28/25 3:57 PM, Kyle Evans wrote:
Gentle ping on this series.
As we didn't have any feedback from BSD side, could we consider to
enable this upstream?
Sorry- I have no strong opinion on plugins, but the diff looks
incredibly reasonable and non-invasive. I'm not really seeing any
reason we
On 4/28/25 14:36, Pierrick Bouvier wrote:
On 3/31/25 4:42 PM, Pierrick Bouvier wrote:
Nothing prevent plugins to be enabled on this platform for user
binaries, only the option in the driver is missing.
Signed-off-by: Pierrick Bouvier
---
bsd-user/main.c | 12
1 file changed, 12
On Sat, Apr 26, 2025 at 1:25 AM Richard Henderson
wrote:
>
> As discussed, the use of GETPC() within write_misa is wrong.
> I've done just enough plumbing to get the helper return address
> piped down to write_misa, so that we can make use of unwind data.
Thanks Richard!
>
> AFAIK, nothing in ch
On Sat, Apr 26, 2025 at 1:26 AM Richard Henderson
wrote:
>
> Do not examine a random host return address, but
> properly compute the next pc for the guest cpu.
>
> Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Ali
On Sat, Apr 26, 2025 at 1:24 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/internals.h | 5 +
> target/riscv/translate.c | 5 -
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/ri
On 4/28/25 15:26, Pierrick Bouvier wrote:
On 4/28/25 3:07 PM, Richard Henderson wrote:
On 4/28/25 15:00, Pierrick Bouvier wrote:
On 4/28/25 1:10 PM, Richard Henderson wrote:
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f5e5746976..8dbe79ea7c 100644
--- a/include
On Sat, Apr 26, 2025 at 1:23 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 4 ++--
> target/riscv/csr.c | 8
> target/riscv/op_helper.c | 9 +
> 3 files changed, 11 insertions(
On Sat, Apr 26, 2025 at 1:26 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 8
> hw/riscv/riscv_hart.c| 2 +-
> target/riscv/csr.c | 8
> target/riscv/op_helper.c | 4 ++--
On Sat, Apr 26, 2025 at 1:24 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e9
On Sat, Apr 26, 2025 at 1:24 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 3 +-
> target/riscv/csr.c | 226 +++--
> 2 files changed, 118 insertions(+), 111 deleti
On Sat, Apr 26, 2025 at 1:25 AM Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 15 +++
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> i
On 4/28/25 3:07 PM, Richard Henderson wrote:
On 4/28/25 15:00, Pierrick Bouvier wrote:
On 4/28/25 1:10 PM, Richard Henderson wrote:
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f5e5746976..8dbe79ea7c 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tc
On 4/28/25 15:00, Pierrick Bouvier wrote:
On 4/28/25 1:10 PM, Richard Henderson wrote:
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f5e5746976..8dbe79ea7c 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -18,8 +18,13 @@
#include "exe
On 4/28/25 1:10 PM, Richard Henderson wrote:
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f5e5746976..8dbe79ea7c 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -18,8 +18,13 @@
#include "exec/vaddr.h"
#include "tcg/tcg-mo.h"
-vo
On Mon, Apr 28, 2025 at 01:59:00AM +0300, Nir Soffer wrote:
> When the `read-zeroes` is set, reads produce zeroes, and block status
> return BDRV_BLOCK_ZERO, emulating a sparse image.
>
> If we don't set `read-zeros` we report BDRV_BLOCK_DATA, but image data
> is undefined; posix_memalign, _aligne
On 4/28/25 1:10 PM, Richard Henderson wrote:
Move the global function name to a hook on TCGCPUOps.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-common.h | 2 +-
include/accel/tcg/cpu-ops.h | 8 ++--
target/arm/internals.h | 1 +
target/ppc/internal.h | 2 ++
acce
On Mon, Apr 28, 2025 at 01:58:59AM +0300, Nir Soffer wrote:
> If read-zeroes is not set, we did not report BDRV_BLOCK_DATA or
> BDRV_BLOCK_ZERO. This is not consistent with other drivers and can
> confuse users or other programs:
>
> % qemu-img map --output json "json:{'driver': 'raw', 'file':
On 4/28/25 1:10 PM, Richard Henderson wrote:
Move set_helper_retaddr and clear_helper_retaddr
to a new header file.
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ldst.h | 34 ---
include/accel/tcg/helper-retaddr.h | 43 ++
a
On 4/28/25 1:10 PM, Richard Henderson wrote:
For some targets, simply remove the local definition.
For other targets, move the inline definition out of line.
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 3 ++
target/alpha/cpu.h | 11 --
target/arm/cpu.h
On 4/28/25 1:10 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 2 --
accel/tcg/meson.build | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Pierrick Bouvier
On 4/28/25 1:10 PM, Richard Henderson wrote:
This function is only relevant to tcg.
Move it to a tcg-specific file.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_helper.c | 97 -
target/riscv/tcg/tcg-cpu.c | 98
On 4/28/25 1:10 PM, Richard Henderson wrote:
Note that target/i386/cpu.h defines CPU_INTERRUPT_INIT
as CPU_INTERRUPT_RESET. Therefore we can handle the
#if TARGET_I386 block in cpu_handle_interrupt with the
new TCGCPUOps.cpu_exec_reset hook.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu
On 4/28/25 1:10 PM, Richard Henderson wrote:
Initialize all instances with cpu_reset(), so that there
is no functional change.
Signed-off-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 2 ++
accel/tcg/cpu-exec.c| 3 ++-
target/alpha/cpu.c | 1 +
target/arm/cpu.c
On 4/28/25 1:10 PM, Richard Henderson wrote:
This flag is only tested by target/i386, so including this
makes no functional change. This is similar to other places
like cpu-target.c which use CPU_DUMP_CCOP unconditionally.
Signed-off-by: Richard Henderson
---
We could just as easily remove CPU
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