On 25/4/25 22:36, Pierrick Bouvier wrote:
On 4/25/25 13:29, BALATON Zoltan wrote:
On Fri, 25 Apr 2025, Pierrick Bouvier wrote:
On 4/25/25 02:43, BALATON Zoltan wrote:
On Thu, 24 Apr 2025, Pierrick Bouvier wrote:
On 4/24/25 17:16, BALATON Zoltan wrote:
On Fri, 25 Apr 2025, Philippe Mathieu-Da
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
Emscripten doesn't provide copy_file_range implementation but it declares
this function in its headers. Meson correctly detects the missing
implementation and unsets HAVE_COPY_FILE_RANGE. However, the stub defined in
file-posix.c causes a type conflict with the declaration from Emscripten
during co
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
The added Dockerfile is based on the emsdk image, which includes the
Emscripten toolchain. It also cross-compiles the necessary dependencies
(glib, libffi, pixman, and zlib) for the Emscripten target environment.
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS |
Emscripten does not support couroutine methods currently used by QEMU but
provides a coroutine implementation called "fiber". This commit introduces a
coroutine backend using fiber. Note that fiber does not support submitting
coroutines to other threads.
Signed-off-by: Kohei Tokunaga
Acked-by: St
Add GitLab CI job that builds QEMU using emscripten. The build runs in the
container defined in tests/docker/dockerfiles/emsdk-wasm32-cross.docker.
Signed-off-by: Kohei Tokunaga
---
.gitlab-ci.d/buildtest-template.yml | 27 +++
.gitlab-ci.d/buildtest.yml | 9 +++
has_int128_type is set to false on emscripten as of now to avoid errors by
libffi. Tests are disabled on emscripten because they rely on host
features that aren't supported by emscripten (e.g. fork and unix
socket).
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS | 1 +
configs/
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On emscripten, some implementations in os-posix.c can't be used such as
daemonizing and changing user. This commit introduces os-wasm.c and
os-wasm.h which are forked from os-posix.c and os-posix.h and patched for
targetting Emscripten.
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS
Emscripten does not support partial unmapping of mmapped memory
regions[1]. This limitation prevents correct implementation of qemu_ram_mmap
and qemu_ram_munmap, which rely on partial unmap behavior.
As a workaround, this commit excludes mmap-alloc.c from the Emscripten
build. Instead, for Emscrip
Daemonizing and run-with aren't supported on Emscripten so disable these
flags.
Signed-off-by: Kohei Tokunaga
Reviewed-by: Philippe Mathieu-Daudé
---
qemu-options.hx | 4 ++--
system/vl.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/qemu-options.hx b/qemu-options
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
Including is still required on Emscripten, just like on other
platforms, to make the ioctl function available.
Signed-off-by: Kohei Tokunaga
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Stefan Hajnoczi
---
block/file-posix.c | 4
1 file changed, 4 insertions(+)
diff --git a/block/fi
Although __builtin___clear_cache is used to flush the instruction cache for
a specified memory region, this operation doesn't apply to wasm, as its
memory isn't executable. Moreover, Emscripten does not support this builtin
and fails to compile it with the following error.
> fatal error: error in
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
V3:
- Fixed the argument type of cpreg_key_compare to use gpointer instead of
void*.
- Fixed the multiline comment to ensure it starts with "/*" on a separate
line.
- Fixed the commit message to remove a confusing link in the
util/cacheflush.c patch.
- Resolved patch conflicts against the la
On Mon, Apr 21, 2025 at 11:19 AM Jason Wang wrote:
>
> On Thu, Apr 17, 2025 at 6:25 PM Cindy Lu wrote:
> >
> > For VDPA devices, Allow configurations where the hardware MAC address
> > is non-zero while the MAC address in the QEMU command line is zero.
> > In this case, QEMU will use the hardware
On Mon, Apr 21, 2025 at 11:22 AM Jason Wang wrote:
>
> On Thu, Apr 17, 2025 at 6:26 PM Cindy Lu wrote:
> >
> > For VDPA devices, Allow configurations where both the hardware MAC address
> > and QEMU command line MAC address are zero.
> > In this case, QEMU will automatically generate a random MAC
Address space creation might end up being called without holding the
bql as it is exposed through the IOMMU ops.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dffd7ee885
vtd_switch_address_space needs to take the BQL if not already held.
Use BQL_LOCK_GUARD to make the iommu implementation more consistent.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/i386/intel_iomm
vtd_find_add_as can be called by multiple threads which leads to a race
condition on address space creation. The IOMMU lock must be taken to
avoid such a race.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 28 ++--
1 file changed, 26 insertions(+), 2 de
This series introduces 2 fixes and improves locking style
consistency in the VT-d device.
Clement Mathieu--Drif (3):
intel_iommu: Take the bql before registering a new address space
intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically
intel_iommu: Take the VTD lock when looking fo
From: xiongweimin
Add initial support for vhost-user-rdma device model for qemu,
this includes the interaction(e.g feature negotiation, setting
vring baseaddr, setting device status) between guest kernel and
host vhost-user-rdma backend device
Signed-off-by: xiongweimin
---
hw/rdma/vhost-user-
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object and then itself.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c | 12 ++
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled when system power on,
the first PC i
On LoongArch virt machine, the default OEM ID and OEM table ID is
"BOCHS " and "BXPC". Here property x-oem-id and x-oem-table-id
is added on virt machine to set customized OEM ID and OEM table ID.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/loongarch/virt.c | 58 +++
The following changes since commit 019fbfa4bcd2d3a835c241295e22ab2b5b56129b:
Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into
staging (2025-04-24 13:44:57 -0400)
are available in the Git repository at:
https://github.com/bibo-mao/qemu.git tags/pull-loongarch-20250428
Add reset support with extioi irqchip, and register reset callback
support with new API resettable_class_set_parent_phases(). Clear
internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi_common.c | 41 +
Add reset support with LoongArch pci irqchip, and register reset
callback support with new API resettable_class_set_parent_phases().
Clear internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pic_common.c | 25 +
XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit
address in the table. There is LoongArch system support from ACPI
Specification 6.4 and later, XSDT is supported by LoongArch system.
Here replace RSDT with XSDT table.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/l
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object.
The internal state has been cleared in parent object
LOONGARCH_PIC_COMMON, here parent_phases.hold() is directl
Add reset support with ipi object, register reset callback and clear
internal registers when virt machine resets.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_ipi.c | 29 +
include/hw/intc/loongarch_ipi.h | 1 +
2 files changed, 30 ins
在 2025/3/4 下午3:41, Bibo Mao 写道:
On LoongArch virt machine, the default OEM ID and OEM table ID is
"BOCHS " and "BXPC". Here property x-oem-id and x-oem-table-id
is added on virt machine to set customized OEM ID and OEM table ID.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 58 +++
在 2025/3/4 下午3:41, Bibo Mao 写道:
XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit
address in the table. There is LoongArch system support from ACPI
Specification 6.4 and later, XSDT is supported by LoongArch system.
Here replace RSDT with XSDT table.
Signed-off-by: Bibo Mao
在 2025/3/24 下午5:37, Bibo Mao 写道:
Rename memory region iomem32_low with iomem, also change ops name
as follows:
loongarch_pch_pic_reg32_low_ops --> loongarch_pch_pic_ops
loongarch_pch_pic_low_readw --> loongarch_pch_pic_read
loongarch_pch_pic_low_writew --> loongarch_pch_pic_wri
在 2025/3/24 下午5:37, Bibo Mao 写道:
Add trace event trace_loongarch_pch_pic_read(), replaces the following
three events:
trace_loongarch_pch_pic_low_readw()
trace_loongarch_pch_pic_high_readw()
trace_loongarch_pch_pic_readb()
The similiar with write trace event.
Signed-off-by: Bibo Mao
--
在 2025/3/24 下午5:37, Bibo Mao 写道:
Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 31 ++-
1 file changed, 10
在 2025/3/24 下午5:37, Bibo Mao 写道:
Add iomem32_high region register write operation emulation in generic
write function loongarch_pch_pic_write(), and use this function for
iomem32_high region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 28 +---
1 file ch
On Fri, Apr 25, 2025 at 6:23 AM Philippe Mathieu-Daudé
wrote:
>
> Prefer MachineClass::get_default_cpu_type() over
> MachineClass::default_cpu_type to get CPU type,
> evaluating TCG availability at runtime calling
> tcg_enabled().
>
> It's worth noting that this is a behavior change:
>
> - Previou
在 2025/3/24 下午5:37, Bibo Mao 写道:
For memory region iomem32_low, generic write callback is used.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 140 +++-
1 file changed, 73 insertions(+), 67 deletions(-)
Reviewed-by: Song Gao
Thanks.
Song Gao
dif
On Thu, Apr 24, 2025 at 5:58 PM Philippe Mathieu-Daudé
wrote:
>
> On 24/4/25 10:56, Zhang Chen wrote:
> > On Thu, Apr 3, 2025 at 10:23 AM Zhang Chen wrote:
> >>
> >> On Thu, Apr 3, 2025 at 2:43 AM Richard Henderson
> >> wrote:
> >>>
> >>> On 4/2/25 06:54, Zhang Chen wrote:
> Because of the
在 2025/3/24 下午5:37, Bibo Mao 写道:
Add iomem8 region register read operation emulation in generic read
function loongarch_pch_pic_read(), and use this function for iomem8
region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 32 +++-
1 file changed, 11 i
在 2025/3/24 下午5:37, Bibo Mao 写道:
Add register read operation emulation in generic read function
loongarch_pch_pic_read(), and use this function for iomem32_high region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 27 ---
1 file changed, 8 insertions(+),
在 2025/3/24 下午5:37, Bibo Mao 写道:
With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 6 --
1 file changed, 6 deletions(-)
Reviewed-by: Song Gao
thanks.
在 2025/3/24 下午5:37, Bibo Mao 写道:
Parameter address for read and write callback in MemoryRegionOps is
relative offset with base address of this MemoryRegionOps. It can
be directly used as offset and offset calculation can be removed.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 34
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Correct the `valid_cpu_types` setting to match the NPCM8XX SoC.
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx_boards.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On Thu, 24 Apr 2025, BALATON Zoltan wrote:
The test case I've used came out of a discussion about very slow
access to VRAM of a graphics card passed through with vfio the reason
for which is still not clear but it was already known that dcbz is
often used by MacOS and AmigaOS for clearing memory
If read-zeroes is not set, we did not report BDRV_BLOCK_DATA or
BDRV_BLOCK_ZERO. This is not consistent with other drivers and can
confuse users or other programs:
% qemu-img map --output json "json:{'driver': 'raw', 'file': {'driver':
'null-co', 'size': '1g'}}"
[{ "start": 0, "length": 1
When the `read-zeroes` is set, reads produce zeroes, and block status
return BDRV_BLOCK_ZERO, emulating a sparse image.
If we don't set `read-zeros` we report BDRV_BLOCK_DATA, but image data
is undefined; posix_memalign, _aligned_malloc, valloc, or memalign do
not promise to zero allocated memory.
The null driver is very usefull for testing and benchmarking, but it can not
emulate an image full of zeroes or an image full of non-zero bytes. Such images
are needed for testing computing a blkhash via qemu-nbd or qemu-storage-daemon.
This change adds `read-pattern` option allowing emulution of
On both macOS and Linux, the default send buffer size too small causing poor
performance when reading and writing to qemu-nbd. A simple way to experience
this is to compare TCP and unix sockets, showing that TCP socket is much
faster. Programs like nbdcopy partly mitigate this by using multiple NBD
Like macOS we have similar issue on Linux. For TCP socket the send
buffer size is 2626560 bytes (~2.5 MiB) and we get good performance.
However for unix socket the default and maximum buffer size is 212992
bytes (208 KiB) and we see poor performance when using one NBD
connection, up to 4 times slow
On macOS we need to increase unix stream socket buffers size on the
client and server to get good performance. We set socket buffers on
macOS after connecting or accepting a client connection. For unix
datagram socket we need different configuration that can be done later.
Testing shows that sett
This patch adds host satp mode while kvm/host cpu satp mode is not
set.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
Signed-off-by: Meng Zhuo
---
target/riscv/kvm/kvm-cpu.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/risc
On 4/27/25 14:53, 刘聪 wrote:
> Hi Dmitry,
>
> The virglrender patch can fix the virgl issue, but the native context still
> fails to run on my machine.
> I'm not sure if anyone has successfully run it on an ARM64 machine before.
Thanks for the testing!
> When running with Venus, the virtual mach
刘聪 writes:
> Hi Dmitry,
>
> The virglrender patch can fix the virgl issue, but the native context still
> fails to run on my machine.
> I'm not sure if anyone has successfully run it on an ARM64 machine before.
>
> When running with Venus, the virtual machine can successfully run vkcube.
> Howe
Hi Dmitry,
The virglrender patch can fix the virgl issue, but the native context still
fails to run on my machine.
I'm not sure if anyone has successfully run it on an ARM64 machine before.
When running with Venus, the virtual machine can successfully run vkcube.
However, when using the native
On 4/27/2025 4:54 PM, Zhao Liu wrote:
>> @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
>> VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
>> VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
>> VMX_VM_EXIT_LOAD_IA32_PAT | VMX_V
On Tue, Apr 01, 2025 at 09:01:37AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:37 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 27/55] i386/tdx: Enable user exit on KVM_HC_MAP_GPA_RANGE
> X-Mailer: git-send-email 2.34.1
>
> KVM translates TDG.VP.VMCALL to KVM_HC_MAP_GPA_RANGE, and QEM
On Tue, Apr 01, 2025 at 09:01:36AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:36 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 26/55] i386/tdx: Finalize TDX VM
> X-Mailer: git-send-email 2.34.1
>
> Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
> the TD vCPUs ru
On 2025/4/25 下午11:33, Richard Henderson wrote:
On 4/24/25 19:16, Bibo Mao wrote:
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
ad
> @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> -VMX_V
...
> > diff --git a/qemu-options.hx b/qemu-options.hx
> > index dc694a99a30a..51a7c61ce0b0 100644
> > --- a/qemu-options.hx
> > +++ b/qemu-options.hx
> > @@ -232,7 +232,8 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel,
> > "eager-split-size=n (KVM Eager Page Split chunk size,
>
> > static void kvm_pmu_filter_class_init(ObjectClass *oc, void *data)
> > {
> > object_class_property_add_enum(oc, "action", "KvmPmuFilterAction",
> > @@ -116,6 +139,14 @@ static void kvm_pmu_filter_class_init(ObjectClass *oc,
> > void *data)
> > NULL, NU
On 2025/4/25 下午5:53, Philippe Mathieu-Daudé wrote:
On 24/3/25 10:37, Bibo Mao wrote:
For memory region iomem32_low, generic read callback is used.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 71 +
1 file changed, 48 insertions(+), 23 dele
Hi Philip and Markus,
Let's discuss how to handle compilation for different architectures as
well as different accelerators here.
> > And "raw" format as a lower level format can be used for other arches
> > (e.g., ARM).
>
> Since you provide the ability to use a raw format, are we sure other
>
On 2025/4/25 下午5:57, Philippe Mathieu-Daudé wrote:
On 24/3/25 10:37, Bibo Mao wrote:
Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
be set at initial stage, rather than read callback.
Signed-off-by: Bibo Ma
73 matches
Mail list logo
