Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

Pierrick Bouvier writes: > On 4/25/25 08:38, Markus Armbruster wrote: >> Pierrick Bouvier writes: >> >>> Note: This RFC was posted to trigger a discussion around this topic, and >>> it's >>> not expected to merge it as it is. >>> >>> Context >>> === >>> >>> Linaro is working towards hetero

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

Philippe Mathieu-Daudé writes: > On 25/4/25 09:35, Daniel P. Berrangé wrote: >> On Thu, Apr 24, 2025 at 11:33:47AM -0700, Pierrick Bouvier wrote: >>> Feedback >>> >>> >>> The goal of this series is to be spark a conversation around following >>> topics: >>> >>> - Would you be open to su

[PULL 056/159] tcg: Merge INDEX_op_remu_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 5 + tcg/optimize.c | 9 + tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg

[PULL 028/159] tcg: Merge INDEX_op_nand_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 -- tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg/tci

[PULL 084/159] tcg: Convert movcond to TCGOutOpMovcond

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/mips/tcg-target-con-set.h| 3 ++- tcg/s390x/tcg-target-con-set.h | 1 - tcg/sparc64/tcg-target-con-set.h | 2 +- tcg/tcg.c| 23 +++

Re: [PATCH v1 1/1] xen: mapcache: Split mapcache_grants by ro and rw

On 25/4/25 16:31, Edgar E. Iglesias wrote: From: "Edgar E. Iglesias" Today, we don't track write-abiliy in the cache, if a user requests a readable mapping followed by a writeable mapping on the same page, the second lookup will incorrectly hit the readable entry. Split mapcache_grants by ro a

Re: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64

On 25/4/25 17:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/csr.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) @@ -5647,9 +5648,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, * accesses */ t

[PULL 110/159] tcg: Expand fallback add2 with 32-bit operations

No need to expand to i64 to perform the add. This is smaller on a loongarch64 host, e.g. bstrpick_d r28, r27, 31, 0 bstrpick_d r29, r24, 31, 0 add_d r28, r28, r29 addi_w r29, r28, 0 srai_d r28, r28, 32 --- add_w r28, r27, r2

[PULL 109/159] tcg: Merge INDEX_op_extract2_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 5 + tcg/optimize.c | 10 +- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.

[PULL 129/159] target/microblaze: Use tcg_gen_addcio_i32

Use this in gen_addc and gen_rsubc, both of which need add with carry-in and carry-out. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --

Re: [PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc

On 25/4/25 18:50, Richard Henderson wrote: This is an alternate, but less exact approach. It assumes that there will never be a 16 or 48-bit csr write instruction. This feels dirtier, but it's a fair assumption involves much less faff. I prefer the other safer version which properly propagate

[PULL 152/159] tcg: Convert st to TCGOutOpStore

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 37 ++ tcg/aarch64/tcg-target.c.inc | 52 +++--- tcg/arm/tcg-target.c.inc | 72 +-- tcg/i386/tcg-target.c.inc| 114 ++--

[PULL 078/159] tcg/tci: Support negsetcond

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-has.h | 4 ++-- tcg/tci/tcg-target.c.inc | 13 + 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-h

[PULL 113/159] tcg/mips: Drop support for add2/sub2

We now produce exactly the same code via generic expansion. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 1 - tcg/mips/tcg-target-con-str.h | 1 - tcg/mips/tcg-target-has.h | 7 ++-- tcg/mips/tcg-target.c.inc | 67 +---

Re: [PATCH 1/2] tcg/sparc64: Unexport use_vis3_instructions

On 25/4/25 22:00, Richard Henderson wrote: This variable is no longer used outside tcg-target.c.inc. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target-has.h | 6 -- tcg/sparc64/tcg-target.c.inc | 6 -- 2 files changed, 4 insertions(+), 8 deletions(-) Reviewed-by: Philipp

Re: [PATCH 6/7] target/riscv: Move insn_len to internals.h

On 25/4/25 17:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/internals.h | 5 + target/riscv/translate.c | 5 - 2 files changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc

On 25/4/25 17:23, Richard Henderson wrote: Do not examine a random host return address, but properly compute the next pc for the guest cpu. Fixes: f18637cd611 ("RISC-V: Add misa runtime write support") Signed-off-by: Richard Henderson --- target/riscv/csr.c | 22 +- 1 fil

[PULL 124/159] tcg/i386: Implement add/sub carry opcodes

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 1 - tcg/i386/tcg-target-has.h | 8 +-- tcg/i386/tcg-target.c.inc | 117 +- 3 files changed, 76 insertions(+), 50 deletions(-) diff --git a/tcg/i386/tcg

Re: [PATCH 4/7] target/riscv: Pass ra to riscv_csrrw

On 25/4/25 17:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 8 hw/riscv/riscv_hart.c| 2 +- target/riscv/csr.c | 8 target/riscv/op_helper.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) Reviewed-by

[PULL 158/159] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 - tcg/aarch64/tcg-target.c.inc | 45 --- tcg/arm/tcg-target.c.inc | 61 - tcg/i386/tcg-target.c.inc| 73 --

[PULL 090/159] tcg: Convert setcond2_i32 to TCGOutOpSetcond2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 2 +- tcg/tcg.c | 19 ++ tcg/arm/tcg-target.c.inc | 25 ++-- tcg/i386/tcg-target.c.inc | 71 +-- tcg/mips/tcg-target.c.

[PULL 091/159] tcg: Convert bswap16 to TCGOutOpBswap

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h

[PULL 044/159] tcg: Merge INDEX_op_mulsh_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 8 tcg/tcg.c | 14 -- docs/devel/tcg-ops.rst | 2 +- 5 files changed, 15 insertions(+), 2

[PULL 096/159] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64

Even though bswap64 can only be used with TCG_TYPE_I64, rename the opcode to maintain uniformity. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 +++--- tcg/tcg-op.c

Re: [PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw

On 4/25/25 1:50 PM, Richard Henderson wrote: Signed-off-by: Richard Henderson --- Reviewed-by: Daniel Henrique Barboza target/riscv/insn_trans/trans_rvi.c.inc | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/tra

[PULL 098/159] tcg: Merge INDEX_op_extract_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 14 -- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 12

[PULL 115/159] tcg: Move i into each for loop in liveness_pass_1

Use per-loop variables instead of one 'i' for the function. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index

[PULL 159/159] tcg: Remove tcg_out_op

All integer opcodes are now converted to TCGOutOp. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 +++- tcg/aarch64/tcg-target.c.inc | 7 --- tcg/arm/tcg-target.c.inc | 7 ---

[PULL 061/159] tcg: Convert sar to TCGOutOpBinary

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++- tcg/aarch64/tcg-target.c.inc | 37 - tcg/arm/tcg-target.c.inc | 26 tcg/i386/tcg-target.c.inc| 46 - tcg/loongarch64/

[PULL 117/159] tcg: Add add/sub with carry opcodes and infrastructure

Liveness needs to track carry-live state in order to determine if the (hidden) output of the opcode is used. Code generation needs to track carry-live state in order to avoid clobbering cpu flags when loading constants. So far, output routines and backends are unchanged. Reviewed-by: Pierrick Bou

[PULL 131/159] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF

Tested-by: Nicholas Piggin Reviewed-by: Nicholas Piggin Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/ppc/translate.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate.c b/target

[PULL 140/159] tcg/s390x: Add TCG_CT_CONST_N32

We were using S32 | U32 for add2/sub2. But the ALGFI and SLGFI insns that implement this both have uint32_t immediates. This makes the composite range balanced and enables use of -0x ... -0x8001. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/s390x/tcg-targe

[PULL 143/159] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc

Pass the sparc COND_* value not the tcg TCG_COND_* value. This makes the usage within add2/sub2 clearer. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions

Re: [PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128

On 25/4/25 17:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/csr.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

[PULL 145/159] tcg/tci: Implement add/sub carry opcodes

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-has.h | 8 +-- tcg/tci.c| 120 +-- tcg/tci/tcg-target-opc.h.inc | 1 + tcg/tci/tcg-target.c.inc | 97 +--- 4 files change

[PULL 030/159] tcg: Convert nor to TCGOutOpBinary

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-ta

[PULL 094/159] tcg: Merge INDEX_op_bswap32_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 13

[PULL 123/159] tcg/i386: Honor carry_live in tcg_out_movi

Do not clobber flags if they're live. Required in order to perform register allocation on add/sub carry opcodes. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.

Re: [PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc

On 4/25/25 1:50 PM, Richard Henderson wrote: Do not examine a random host return address, but examine the guest pc via env->pc. Fixes: f18637cd611 ("RISC-V: Add misa runtime write support") Signed-off-by: Richard Henderson --- target/riscv/csr.c | 9 ++--- 1 file changed, 6 insertions

[PULL 157/159] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 32 +++- tcg/aarch64/tcg-target.c.inc | 30 +-- tcg/arm/tcg-target.c.inc | 63 +++- tcg/i386/tcg-target.c.inc| 47

[PULL 108/159] tcg: Convert extract2 to TCGOutOpExtract2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 6 - tcg/ppc/tcg-targe

Re: [PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128

On 25/4/25 17:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 4 ++-- target/riscv/csr.c | 8 target/riscv/op_helper.c | 9 + 3 files changed, 11 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn

On 25/4/25 17:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 226 +++-- 2 files changed, 118 insertions(+), 111 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h inde

[PULL 085/159] tcg: Merge INDEX_op_movcond_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 2 +- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 15 +-- tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- t

[PULL 095/159] tcg: Convert bswap64 to TCGOutOpUnary

Use TCGOutOpUnary instead of TCGOutOpBswap because the flags are not used with this opcode; they are merely present for uniformity with the smaller bswaps. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h

[PULL 081/159] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}`

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 6 ++ target/sh4/translate.c | 6 +++--- tcg/optimize.c | 32 tcg/tcg-op.c | 8 tcg/tcg.c| 30

Re: [PULL 000/159] tcg patch queue

On 25/4/25 23:52, Richard Henderson wrote: Convert TCG backend code generators to TCGOutOp structures, decomposing the monolithic tcg_out_op functions. 60 file

[PULL 136/159] tcg/aarch64: Implement add/sub carry opcodes

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 3 +- tcg/aarch64/tcg-target-has.h | 8 +- tcg/aarch64/tcg-target.c.inc | 227 --- 3 files changed, 150 insertions(+), 88 deletions(-) diff --git a/tcg/a

Re: [PATCH 2/2] tcg/sparc64: Implement CTPOP

On 25/4/25 22:00, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

[PULL 083/159] tcg: Merge INDEX_op_brcond_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 6 +++--- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 24 tcg/tci.c|

[PULL 128/159] target/hppa: Use tcg_gen_addcio_i64

Use this in do_add, do_sub, and do_ds, all of which need add with carry-in and carry-out. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/hppa/translate.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) dif

[PULL 038/159] tcg: Merge INDEX_op_not_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 13 ++--- tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 11 +-- docs/devel/tcg

[PULL 156/159] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}

Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two inputs or outputs are required. This simplifies the processing of i64/i128 depending on host word size. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 16 ++- tcg/optimiz

[PULL 114/159] tcg/riscv: Drop support for add2/sub2

We now produce exactly the same code via generic expansion. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target-has.h | 6 +-- tcg/riscv/tcg-target.c.inc | 86 +- 3 files changed,

[PULL 087/159] tcg/arm: Expand arguments to tcg_out_cmp2

Pass explicit arguments instead of arrays. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/

[PULL 047/159] tcg: Convert divu to TCGOutOpBinary

For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/loongarch64/tcg-target-h

[PULL 138/159] tcg/ppc: Implement add/sub carry opcodes

Tested-by: Nicholas Piggin Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 5 +- tcg/ppc/tcg-target-con-str.h | 1 + tcg/ppc/tcg-target-has.h | 11 +- tcg/ppc/tcg-target.c.inc | 227 ++- 4 files chang

[PULL 103/159] tcg: Convert extrl_i64_i32 to TCGOutOpUnary

Drop the cast from TCGv_i64 to TCGv_i32 in tcg_gen_extrl_i64_i32 an emit extrl_i64_i32 unconditionally. Move that special case to tcg_gen_code when we find out if the output is live or dead. In this way even hosts that canonicalize truncations can make use of a store directly from the 64-bit host

[PULL 122/159] tcg: Use sub carry opcodes to expand sub2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f17ec658fb..447b0ebacd 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1126,7 +112

[PULL 086/159] tcg/ppc: Drop fallback constant loading in tcg_out_cmp

Use U and C constraints for brcond2 and setcond2, so that tcg_out_cmp2 automatically passes in-range constants to tcg_out_cmp. Tested-by: Nicholas Piggin Reviewed-by: Nicholas Piggin Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 4 +-- tcg/

[PULL 151/159] tcg: Merge INDEX_op_ld*_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 19 +--- tcg/optimize.c | 27 - tcg/tcg-op.c | 24 +++ tcg/tcg.c| 64 ++

[PULL 104/159] tcg: Convert extrh_i64_i32 to TCGOutOpUnary

At the same time, make extrh_i64_i32 mandatory. This closes a hole in which move arguments could be cast between TCGv_i32 and TCGv_i64. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 +-- tcg/tcg.c| 5 +++--

[PULL 141/159] tcg/s390x: Implement add/sub carry opcodes

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 4 +- tcg/s390x/tcg-target-has.h | 8 +- tcg/s390x/tcg-target.c.inc | 153 +++-- 3 files changed, 96 insertions(+), 69 deletions(-) diff --git a/tcg/s390x/

[PULL 092/159] tcg: Merge INDEX_op_bswap16_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 5 ++--- docs/

[PULL 089/159] tcg: Convert brcond2_i32 to TCGOutOpBrcond2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 2 +- tcg/tcg.c | 30 + tcg/arm/tcg-target.c.inc | 20 +++ tcg/i386/tcg-target.c.inc | 62 ++- tcg/mips/tcg-tar

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

On 25/4/25 09:35, Daniel P. Berrangé wrote: On Thu, Apr 24, 2025 at 11:33:47AM -0700, Pierrick Bouvier wrote: Feedback The goal of this series is to be spark a conversation around following topics: - Would you be open to such an approach? (expose all code, and restrict commands reg

[PULL 102/159] tcg: Convert extu_i32_i64 to TCGOutOpUnary

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 15 --- tcg/aarch64/tcg-target.c.inc | 2 -- tcg/i386/tcg-target.c.inc| 2 -- tcg/loongarch64/tcg-target.c.inc | 2 -- tcg/mips/tcg-target.c.inc| 2 -- tcg/pp

[PULL 072/159] tcg: Convert muls2 to TCGOutOpMul2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-h

[PULL 116/159] tcg: Sink def, nb_iargs, nb_oargs loads in liveness_pass_1

Sink the sets of the def, nb_iargs, nb_oargs variables to the default and do_not_remove labels. They're not really needed beforehand, and it avoids preceding code from having to keep them up-to-date. Note that def had *not* been kept up-to-date; thankfully only def->flags had been used and those

[PULL 016/159] tcg: Merge INDEX_op_andc_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- target/arm/tcg/translate-a64.c | 2 +- target/tricore/translate.c | 2 +- tcg/optimize.c | 6 -- tcg/tcg-op.c | 8 tcg/tcg.c

[PULL 127/159] target/arm: Use tcg_gen_addcio_* for ADCS

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 8 ++-- target/arm/tcg/translate.c | 17 +++-- 2 files changed, 5 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a6

[PULL 082/159] tcg: Convert brcond to TCGOutOpBrcond

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/mips/tcg-target-con-set.h| 4 +-- tcg/riscv/tcg-target-con-set.h | 2 +- tcg/sparc64/tcg-target-con-set.h | 2 +- tcg/tcg.c| 26 ++

[PULL 126/159] tcg: Add tcg_gen_addcio_{i32,i64,tl}

Create a function for performing an add with carry-in and producing carry out. The carry-out result is boolean. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 4 ++ include/tcg/tcg-op.h| 2 + tcg/tcg-op.c| 95 +

[PULL 130/159] target/openrisc: Use tcg_gen_addcio_* for ADDC

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d4ce60188b..baadea4448 100644

[PULL 093/159] tcg: Convert bswap32 to TCGOutOpBswap

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h

[PULL 132/159] target/s390x: Use tcg_gen_addcio_i64 for op_addc64

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 00073c5560..a714f9c0c2 1

[PULL 022/159] tcg: Convert xor to TCGOutOpBinary

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 +++ tcg/aarch64/tcg-target.c.inc | 31 +++- tcg/arm/tcg-target.c.inc | 25 +++- tcg/i386/tcg-target.c.inc| 27 - tcg/loo

[PULL 119/159] tcg/optimize: Handle add/sub with carry opcodes

Propagate known carry when possible, and simplify the opcodes to not require carry-in when known. The result will be cleaned up further by the subsequent liveness analysis pass. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 319

[PULL 154/159] tcg: Stash MemOp size in TCGOP_FLAGS

This will enable removing INDEX_op_qemu_st8_*_i32, by exposing the operand size to constraint selection. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff

[PULL 106/159] tcg/aarch64: Improve deposit

Use ANDI for deposit 0 into a register. Use UBFIZ, aka UBFM, for deposit register into 0. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 +- tcg/aarch64/tcg-target.c.inc | 29 - 2 files changed, 29 inserti

[PULL 105/159] tcg: Convert deposit to TCGOutOpDeposit

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 33 ++ tcg/tci.c| 8 ++-- tcg/aarch64/tcg-target.c.inc | 30 + tcg/arm/tcg-target.c.inc | 29 ++-- tcg/i386/tcg-target.c.inc

[PULL 153/159] tcg: Merge INDEX_op_st*_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 15 -- tcg/optimize.c | 28 +++-- tcg/tcg-op.c | 14 ++--- tcg/tcg.c| 45 +-

[PULL 147/159] tcg: Formalize tcg_out_mb

Most tcg backends already have a function for this; the rest can split one out from tcg_out_op. Call it directly from tcg_gen_code. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg

[PULL 111/159] tcg: Expand fallback sub2 with 32-bit operations

No need to expand to i64 to perform the subtract. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8b1356c526..127338b994 100644 --- a/tcg/tcg-o

[PULL 150/159] tcg: Convert ld to TCGOutOpLoad

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 46 +++ tcg/aarch64/tcg-target.c.inc | 113 --- tcg/arm/tcg-target.c.inc | 126 --- tcg/i386/tcg-target.c.inc| 11

[PULL 042/159] tcg: Merge INDEX_op_muluh_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/optimize.c | 19 +++ tcg/tcg-op.c | 10 +- tcg/tcg.c | 13 - docs/devel/tcg-ops.rst | 2 +- 5 files changed, 22 insert

[PULL 088/159] tcg/ppc: Expand arguments to tcg_out_cmp2

Tested-by: Nicholas Piggin Reviewed-by: Nicholas Piggin Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 +++-- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/tcg/ppc/tcg-target

[PULL 052/159] tcg: Merge INDEX_op_divu2_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.rst | 10 ++ 4 files changed, 21 insertions(+), 14 deletions(-) diff --git a/inc

[PULL 121/159] tcg: Use add carry opcodes to expand add2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 127338b994..f17ec658fb 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1102,7 +110

[PULL 107/159] tcg: Merge INDEX_op_deposit_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 2 +- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst | 6 -- tcg

[PULL 134/159] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/sparc/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index adebddf27b..63dd90447b 100644 --- a/target/sparc/translate.c +++ b/target/sp

[PULL 142/159] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 67179de848..09c7ca5b44 100644 --- a/tcg/s390x/tcg

[PULL 118/159] tcg: Add TCGOutOp structures for add/sub carry opcodes

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 61 +++- tcg/aarch64/tcg-target.c.inc | 34 ++ tcg/arm/tcg-target.c.inc | 34 ++ tcg/i386/tcg-target.c.inc| 34 +++

[PULL 120/159] tcg/optimize: With two const operands, prefer 0 in arg1

For most binary operands, two const operands fold. However, the add/sub carry opcodes have a third input. Prefer "reg, zero, const" since many risc hosts have a zero register that can fit a "reg, reg, const" insn format. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/opt

[PULL 149/159] tcg: Formalize tcg_out_goto_ptr

Split these functions out from tcg_out_op. Define outop_goto_ptr generically. Call tcg_out_goto_ptr from tcg_reg_alloc_op. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 tcg/aarch64/tcg-target.c.inc | 12 +--- t

[PULL 100/159] tcg: Merge INDEX_op_sextract_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 22 +++--- tcg/tcg-op.c | 12 ++-- tcg/tcg.c| 9 +++-- tcg/tci.c

[PULL 135/159] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/tricore/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ede0c92c1e..ba36c9fcc8 1006

[PULL 133/159] target/sh4: Use tcg_gen_addcio_i32 for addc

Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/sh4/translate.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 712a57fb54..712117be22 100644 --- a/

[PULL 144/159] tcg/sparc64: Implement add/sub carry opcodes

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target-con-set.h | 3 +- tcg/sparc64/tcg-target-has.h | 8 +- tcg/sparc64/tcg-target.c.inc | 300 --- 3 files changed, 201 insertions(+), 110 deletions(-) diff --git a/tcg/

[PULL 099/159] tcg: Convert sextract to TCGOutOpExtract

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 ++ tcg/aarch64/tcg-target.c.inc | 18 + tcg/arm/tcg-target.c.inc | 21 ++- tcg/i386/tcg-target.c.inc| 63 tcg/loongarch64

  1   2   3   4   5   6   >