On 3/17/25 07:59, Troy Lee wrote:
AST27x0 has 4 EHCI controllers, where each CPU and I/O die has 2
instances. This patch use existing TYPE_PLATFORM_EHCI. After wiring up
the EHCI controller, the ast2700a1-evb can find up to 4 USB EHCI
interfaces.
ehci-platform 12061000.usb: EHCI Host Controller
On 4/22/25 02:27, Joe Komlodi wrote:
cde3247651dc998da5dc1005148302a90d72f21f fixed atomicity for LDRD, which
ends up making accesses 64-bits wide. However, the AST2600 bootloader
can sometimes compile with LDRD instructions, which causes the acceses
to fail when accessing the memory-mapped SPI f
On 4/23/25 03:40, Jamin Lin wrote:
v1:
Update to test new ASPEED SDK version for AST2600, AST2500 ,and AST1030.
v2:
Fix review issue for AST1030.
Jamin Lin (3):
tests/functional/aspeed: Update test ASPEED SDK v09.06 for AST2500
tests/functional/aspeed: Update test ASPEED SDK v09.06 f
On 4/23/25 03:40, Jamin Lin wrote:
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/functional/test_arm_aspeed_ast1030.py | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/functional/test_arm_aspeed_ast1030.py
b/tests/fun
> 2025年4月16日 10:47，Haoqian He 写道：
>
> Live migration should be terminated if the vhost-user backend crashes
> before the migration completes.
>
> Specifically, since the vhost device will be stopped when VM is stopped
> before the end of the live migration, in current implementation if the
> b
On Wed, Apr 23, 2025 at 03:19:30PM +0900, Akihiko Odaki wrote:
> This reverts commit e28fbd1c525db21f0502b85517f49504c9f9dcd8.
>
> The goal of commit 7987d2be5a8b ("virtio-net: Copy received header to
> buffer") was to remove the need to patch the (const) input buffer with a
> recomputed UDP check
On 2025/4/22 下午8:03, Li Chen wrote:
This series introduces a new machine option, spcr=on|off, allowing users
to disable the ACPI SPCR (Serial Port Console Redirection) table.
By default, SPCR is enabled. Disabling it can help ensure that the guest >
console behavior is determined solely by ke
On 4/22/25 23:24, Pierrick Bouvier wrote:
On 4/22/25 22:34, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:30, Pierrick Bouvier wrote:
On 4/22/25 11:24, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:20, Pierrick Bouvier wrote:
On 4/22/25 07:54, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philipp
On 4/22/25 22:34, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:30, Pierrick Bouvier wrote:
On 4/22/25 11:24, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:20, Pierrick Bouvier wrote:
On 4/22/25 07:54, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/targe
This reverts commit e28fbd1c525db21f0502b85517f49504c9f9dcd8.
The goal of commit 7987d2be5a8b ("virtio-net: Copy received header to
buffer") was to remove the need to patch the (const) input buffer with a
recomputed UDP checksum by copying headers to a RW region and inject the
checksum there. The
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
Do not emit an I/O page fault on amdvi_page_walk() when a valid mapping
is not found. The current role of amdvi_page_walk() is to be a helper
for the translate() method and ultimately the IOMMU replay()
functionality. These operations might be exe
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table
8: V, TV, and GV Fields in Device Table Entry), specifies that a DTE
with V=0, TV=1 does not contain a valid address translation information.
This should be "V=1, TV=0".
Reg
Hi Philippe,
>On 22/4/25 07:27, Kohei Tokunaga wrote:
>> Although __builtin___clear_cache is used to flush the instruction cache
for
>> a specified memory region[1], this operation doesn't apply to wasm, as
its
>> memory isn't executable. Moreover, Emscripten does not support this
builtin
>> and f
On Wed, Apr 23, 2025 at 05:38:20AM +, CLEMENT MATHIEU--DRIF wrote:
> Address space creation might end up being called without holding the
> bql as it is exposed through the IOMMU ops.
>
> Signed-off-by: Clement Mathieu--Drif
> ---
> hw/i386/intel_iommu.c | 6 ++
> 1 file changed, 6 inser
vtd_switch_address_space needs to take the BQL if not already held.
Use BQL_LOCK_GUARD to make the iommu implementation more consistent.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/hw/i386/intel_iomm
Address space creation might end up being called without holding the
bql as it is exposed through the IOMMU ops.
Signed-off-by: Clement Mathieu--Drif
---
hw/i386/intel_iommu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index dffd7ee885
Hi Akihiko,
On 23/4/25 07:24, Akihiko Odaki wrote:
On 2025/04/23 5:31, Pierrick Bouvier wrote:
On 4/22/25 12:45, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:36, Pierrick Bouvier wrote:
On 4/22/25 10:19, Philippe Mathieu-Daudé wrote:
When using Visual Studio Code (v1.99.3) and Apple clangd v1
On 22/4/25 20:30, Pierrick Bouvier wrote:
On 4/22/25 11:24, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:20, Pierrick Bouvier wrote:
On 4/22/25 07:54, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/target-info-impl.h | 4
configs/targets/aarch6
On 2025/04/23 5:31, Pierrick Bouvier wrote:
On 4/22/25 12:45, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:36, Pierrick Bouvier wrote:
On 4/22/25 10:19, Philippe Mathieu-Daudé wrote:
When using Visual Studio Code (v1.99.3) and Apple clangd v17.0.0
I get:
In file included from ../../qapi/st
On Tue, Apr 01, 2025 at 09:01:25AM -0400, Xiaoyao Li wrote:
> Date: Tue, 1 Apr 2025 09:01:25 -0400
> From: Xiaoyao Li
> Subject: [PATCH v8 15/55] i386/tdx: Implement user specified tsc frequency
> X-Mailer: git-send-email 2.34.1
>
> Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency an
From: Kane-Chen-AS
Dear reviewers,
This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.
The OTP memory is implemented as a QEMU device (`aspeed.otpmem
From: Kane-Chen-AS
This patch wires up the OTP memory device (`aspeed.otpmem`) into the
AST1030 and AST2600 SoC models. The device is initialized, attached
to a backing block drive (`-drive id=otpmem`) and linked to the SBC
controller via a QOM link.
The default OTP memory image can be generated
From: Kane-Chen-AS
This patch integrates the `aspeed.otpmem` device with the ASPEED
Secure Boot Controller (SBC). The SBC now accepts an OTP backend via
a QOM link property ("otpmem"), enabling internal access to OTP content
for controller-specific logic.
This connection provides the foundation
From: Kane-Chen-AS
This introduces a new model for the ASPEED OTP (One-Time Programmable)
memory. The device is implemented as a `SysBusDevice` and provides an
abstracted interface for OTP read, write (program), and default value
initialization.
OTP content is backed by a block device and suppor
Signed-off-by: Jamin Lin
---
tests/functional/test_arm_aspeed_ast1030.py | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/functional/test_arm_aspeed_ast1030.py
b/tests/functional/test_arm_aspeed_ast1030.py
index d45d9f7c1c..77037f0179 100755
--- a/tests/functi
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_arm_aspeed_ast2500.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_arm_aspeed_ast2500.py
b/tests/functional/test_arm_aspeed_ast2500.py
index 1ffba6c995..90f3940e
v1:
Update to test new ASPEED SDK version for AST2600, AST2500 ,and AST1030.
v2:
Fix review issue for AST1030.
Jamin Lin (3):
tests/functional/aspeed: Update test ASPEED SDK v09.06 for AST2500
tests/functional/aspeed: Update test ASPEED SDK v09.06 for AST2600
tests/functional/aspeed: Upd
Update test for AST2600 production revision A3.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_arm_aspeed_ast2600.py | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/tests/functional/test_arm_aspeed_ast2600.py
b/tests/functio
Hi Philip, Cedric,
>
> On 4/22/25 11:15, Jamin Lin wrote:
> > Updated test to target SDK version v03.00.
> > Removed redundant test case to simplify validation.
> > Cleaned up unsupported shell commands.
>
> Were some commands removed from SDK v03.00 ? Testing different zephyr
Thanks for revie
On 4/22/25 10:05 PM, Li Chen wrote:
From: Li Chen
The ACPI SPCR (Serial Port Console Redirection) table allows firmware
to specify a preferred serial console device to the operating system.
On ARM64 systems, Linux by default respects this table: even if the
kernel command line does not include
On Fri, Mar 14, 2025 at 11:48:33AM +0100, Alexandre Ghiti wrote:
The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Apart from what you already caught.
Extension is dependnet on Sv39. So it should be validated somewhere.
Perhaps in `riscv_cpu_validate_
The following changes since commit 1da8f3a3c53b604edfe0d55e475102640490549e:
Open 10.1 development tree (2025-04-22 15:09:23 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-avr-20250422
for you to fetch changes up to
If i/o does not cover the entire first page, allocate a portion
of ram as an i/o device, so that the entire first page is i/o.
While memory_region_init_ram_device_ptr is happy to allocate
the RAMBlock, it does not register the ram for migration.
Do this by hand.
Reviewed-by: Pierrick Bouvier
Sig
Avoid direct use of address_space_memory.
Make use of the softmmu cache of the i/o page.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.
This define is no longer used.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 6f68060ab0..9862705c6a 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -45,8
This define isn't really used.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 2 --
target/avr/helper.c | 3 +--
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 7d6954ec26..f23fa3e8ba 100644
--- a/target/
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-sta...@nongnu.org
Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 10 ++
target/avr/helper.c | 36 ++--
2 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/target/avr/cpu.h b/target/a
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into
the cpu registers with normal address space accesses.
We no longer need to trap accesses to the first page within
avr_cpu_tlb_fill but can wait until a write occurs.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
targe
Now that we can handle the MCU allocating only a portion of the
first page to i/o, increase the page size. Choose 10 as larger
than the i/o on every MCU, just so that this path is tested.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h | 8 +---
1
On Mon, Apr 14, 2025 at 3:43 AM Philippe Mathieu-Daudé
wrote:
> On 14/4/25 04:06, Tim Lee wrote:
> > Nuvoton's PSPI is a general purpose SPI module which enables
> > connections to SPI-based peripheral devices. Attach it to the NPCM8XX.
> >
> > Tested:
> > NPCM8XX PSPI driver probed successfully
On 4/22/25 12:28, Richard Henderson wrote:
In effect, hoist the check for mttcg from tcg_n_regions()
to tcg_init_machine().
Signed-off-by: Richard Henderson
---
include/tcg/startup.h | 6 +++---
tcg/tcg-internal.h| 2 +-
accel/tcg/tcg-all.c | 14 --
tcg/region.c
On 4/22/25 12:28, Richard Henderson wrote:
Delay the warning to tcg_init_machine, because we will
have resolved the CPUClass at that point.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
Reviewed-by: Pi
On 4/22/25 12:28, Richard Henderson wrote:
In qemu_tcg_mttcg_enabled, read the value from TCGState
and eliminate the separate global variable.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
Reviewed-by: Pierrick Bouvi
On 4/22/25 12:26, Richard Henderson wrote:
Recover two bits from the inline flags.
Signed-off-by: Richard Henderson
---
include/exec/tlb-flags.h | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Pierrick Bouvier
On 4/22/25 12:26, Richard Henderson wrote:
Undo the split between inline and slow flags before masking.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Pierrick Bouvier
On 4/22/25 12:26, Richard Henderson wrote:
While we're renaming things, don't modify addr; save it for
reuse in the qatomic_set. Compute the host address into a
new local variable.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 20 ++--
1 file changed, 10 insertio
On 4/22/25 12:26, Richard Henderson wrote:
The arguments to tlb_reset_dirty are host pointers.
The conversion from ram_addr_t was done in the sole
caller, tlb_reset_dirty_range_all.
Fixes: e554861766d ("exec: prepare for splitting")
Signed-off-by: Richard Henderson
---
include/exec/cputlb.h |
On 4/22/25 12:26, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/icount.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Pierrick Bouvier
On 4/22/25 12:26, Richard Henderson wrote:
Split icount stuff from system/cpu-timers.h.
There are 17 files which only require icount.h, 7 that only
require cpu-timers.h, and 7 that require both.
Signed-off-by: Richard Henderson
---
include/exec/icount.h| 68 +++
On 4/22/25 12:26, Richard Henderson wrote:
Relatively few objects in qemu care about watchpoints, so split
out to a new header. Removes an instance of CONFIG_USER_ONLY
from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/exec/watchpoint.h | 41 ++
On 4/22/25 12:26, Richard Henderson wrote:
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
semihosting/user.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Pierrick Bouvier
On 4/22/25 12:26, Richard Henderson wrote:
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 58 ++
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-13-phi...@linaro.org>
---
target/microblaze/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mic
On 4/22/25 12:45, Philippe Mathieu-Daudé wrote:
On 22/4/25 20:36, Pierrick Bouvier wrote:
On 4/22/25 10:19, Philippe Mathieu-Daudé wrote:
When using Visual Studio Code (v1.99.3) and Apple clangd v17.0.0
I get:
In file included from ../../qapi/string-output-visitor.c:14:
qemu/include/qe
From: Philippe Mathieu-Daudé
tb_check_watchpoint() calls cpu_get_tb_cpu_state(),
which is declared in each "cpu.h" header. It is indirectly
included via "tcg/insn-start-words.h". Since we want to
rework "tcg/insn-start-words.h", removing "cpu.h" in the
next commit, add the missing header now, oth
From: Philippe Mathieu-Daudé
Convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(),
restricting s390x_cpu_mmu_index() to TCG #ifdef.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-19-phi...@linaro.org>
From: Philippe Mathieu-Daudé
By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Signed-off-by: Rich
The implementation of cpu_mmu_index was split between cpu-common.h
and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the
plumbing common to user and system mode. Using MMU_USER_IDX
requires the cpu.h for a specific target, and so is restricted to
when we're compiling per-target.
Incl
On 22/4/25 20:36, Pierrick Bouvier wrote:
On 4/22/25 10:19, Philippe Mathieu-Daudé wrote:
When using Visual Studio Code (v1.99.3) and Apple clangd v17.0.0
I get:
In file included from ../../qapi/string-output-visitor.c:14:
qemu/include/qemu/cutils.h:144:12: error: 'strchrnul' is only
ava
From: Philippe Mathieu-Daudé
In preparation of having tcg_req_mo() access CPUState in
the next commit, pass it to cpu_req_mo(), its single caller.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h | 3 ++-
a
From: Philippe Mathieu-Daudé
As Richard mentioned:
We should allow RV128 in user-mode at all until there's a
kernel abi for it.
Remove the experimental 'x-rv128' CPU on user emulation
(since it is experimental, no deprecation period is required).
Reported-by: Richard Henderson
Reviewed-by
Many of the headers used by these require CONFIG_USER_ONLY.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
hw/core/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/core/meson.build b/hw/core/meson.build
index b5a545a0ed..547de6527c 10064
From: Pierrick Bouvier
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-27-pierrick.bouv...@linaro.org>
---
hw/arm/digic_boards.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/digic_
From: Philippe Mathieu-Daudé
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
accel/tcg/inte
The only place we really need to know the minimum is within
page-vary-target.c. Rename the target/arm TARGET_PAGE_BITS_MIN
to TARGET_PAGE_BITS_LEGACY to emphasize what it really means.
Move the assertions related to minimum page size as well.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard
From: Pierrick Bouvier
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-30-pierrick.bouv...@linaro.org>
---
hw/arm/meson.build | 112 ++---
1 file changed, 56 insertions(+
From: Philippe Mathieu-Daudé
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
default_mttcg_enabled
From: Philippe Mathieu-Daudé
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Me
Poison CONFIG_USER_ONLY and CONFIG_SOFTMMU unless
the compilation unit is in specific_ss, libuser_ss,
or libsystem_ss. This is intended to prevent files
being incorrectly added to common_ss.
Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks.
All they do is trigger the poison error.
Review
From: Pierrick Bouvier
Remove kvm unused headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-28-pierrick.bouv...@linaro.org>
---
hw/arm/xlnx-zynqmp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/h
Headers used by these files require CONFIG_USER_ONLY.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
plugins/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/plugins/meson.build b/plugins/meson.build
index 3be8245a69..5383c7b88b 100644
---
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/hw/s390x/css.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h
index c
From: Pierrick Bouvier
Remove kvm unused headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-29-pierrick.bouv...@linaro.org>
---
hw/arm/xlnx-versal.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/h
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-15-phi...@linaro.org>
---
target/openrisc/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openr
From: Philippe Mathieu-Daudé
Move x86_cpu_mmu_index() to tcg-cpu.c, convert
CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-10-phi...@linaro.org>
---
targe
From: Pierrick Bouvier
Now we eliminated poisoned identifiers from headers, this file can now
be compiled once for all arm targets.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-25-pierrick.bouv...@linaro.org
The arguments to tlb_reset_dirty are host pointers.
The conversion from ram_addr_t was done in the sole
caller, tlb_reset_dirty_range_all.
Fixes: e554861766d ("exec: prepare for splitting")
Signed-off-by: Richard Henderson
---
include/exec/cputlb.h | 2 +-
accel/tcg/cputlb.c| 6 +++---
2 fil
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-23-phi...@linaro.org>
---
target/xtensa/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/xtensa/
From: Philippe Mathieu-Daudé
We'll move CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-3-phi...@linaro.org>
---
include/accel/tcg/cpu-mmu-index.h | 5
From: Pierrick Bouvier
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-4-pierrick.bouv...@linaro.org>
---
include/exec/cpu-all.h | 4
From: Philippe Mathieu-Daudé
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is supported via the
The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required
outside of cputlb.c and translate-all.c.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h | 27 ---
accel/tcg/tlb-bounds.h| 32
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/trans
From: Philippe Mathieu-Daudé
Move riscv_cpu_mmu_index() to the TCG-specific file,
convert CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-17-phi...@linaro.o
From: Pierrick Bouvier
Directly condition associated calls in target/arm/helper.c for now.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-23-pierrick.bouv...@linaro.org>
---
target/arm/cpu.h| 8
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-12-phi...@linaro.org>
---
target/m68k/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/cpu.
From: Philippe Mathieu-Daudé
Rename riscv_cpu_mmu_index() -> rx_cpu_mmu_index().
Fixes: ef5cc166da1 ("target/rx: Populate CPUClass.mmu_index")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401072052.25892-1-phi...@linar
From: Pierrick Bouvier
Now we made sure important defines are included using their direct
path, we can remove cpu.h from cpu-all.h.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Message-ID: <20250325045915.994760-14-pierrick.bouv...@linaro.org
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-4-phi...@linaro.org>
---
target/alpha/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/alpha/cpu
From: Philippe Mathieu-Daudé
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by: Philippe Mathieu-Da
We do not set CONFIG_SEMIHOSTING in
configs/targets/mips*-linux-user.mak.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b207106dd7..47df5
From: Philippe Mathieu-Daudé
Only file units within the system/ directory need access to
"memory-internal.h". Restrict its scope by moving it there.
The comment from commit 9d70618c684 ("memory-internal.h:
Remove obsolete claim that header is obsolete") is now obsolete,
remove it.
Signed-off-by
Avoid testing CONFIG_USER_ONLY in semihost.h.
The only function that's required is semihosting_enabled.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/semihosting/semihost.h | 29 ++---
semihosting/stubs-al
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250401080938.32278-11-phi...@linaro.org>
---
target/loongarch/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loon
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
accel/tcg/backend-ldst.h| 41 +
accel/tcg/internal-target.h | 28 -
accel/tcg/cputlb.c
Move the declarations from exec/exec-all.h to the
private accel/tcg/internal-common.h.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
accel/tcg/internal-common.h | 34 ++
include/exec/exec-all.h | 34 --
acc
In qemu_tcg_mttcg_enabled, read the value from TCGState
and eliminate the separate global variable.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index bb759cec07..b75
From: Philippe Mathieu-Daudé
Mechanical change using:
$ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \
$(git grep -l exec/cpu_ldst.h)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
bsd-use
1 - 100 of 417 matches
Mail list logo
