Hi
On Tue, Apr 22, 2025 at 10:37 AM Dietmar Maurer wrote:
>
> > On Fri, Apr 18, 2025 at 3:30 PM Dietmar Maurer wrote:
> > >
> > > Some encoders can hang indefinetly (i.e. nvh264enc) if
> >
> > indefinitely
> >
> > > the pipeline is not stopped before it is destroyed
> > > (Observed on Debian boo
On 22/4/25 07:27, Kohei Tokunaga wrote:
Daemonizing and run-with aren't supported on Emscripten so disable these
flags.
Signed-off-by: Kohei Tokunaga
---
qemu-options.hx | 4 ++--
system/vl.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daud
On 22/4/25 07:27, Kohei Tokunaga wrote:
Including is still required on Emscripten, just like on other
platforms, to make the ioctl function available.
Signed-off-by: Kohei Tokunaga
---
block/file-posix.c | 4
1 file changed, 4 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 22/4/25 07:27, Kohei Tokunaga wrote:
Although __builtin___clear_cache is used to flush the instruction cache for
a specified memory region[1], this operation doesn't apply to wasm, as its
memory isn't executable. Moreover, Emscripten does not support this builtin
and fails to compile it with t
On 22/4/25 07:27, Kohei Tokunaga wrote:
Emscripten doesn't provide copy_file_range implementation but it declares
this function in its headers. Meson correctly detects the missing
implementation and unsets HAVE_COPY_FILE_RANGE. However, the stub defined in
file-posix.c causes a type conflict with
On 22/4/25 07:27, Kohei Tokunaga wrote:
Although __builtin___clear_cache is used to flush the instruction cache for
a specified memory region[1], this operation doesn't apply to wasm, as its
memory isn't executable. Moreover, Emscripten does not support this builtin
and fails to compile it with t
On 22/4/25 07:27, Kohei Tokunaga wrote:
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoi
On 22/4/25 07:27, Kohei Tokunaga wrote:
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoi
John Snow writes:
> Since the previous commit, python/setup.cfg applies to scripts/qapi/ as
> well. Configuration files in scripts/qapi/ override python/setup.cfg.
>
> scripts/qapi/.flake8 and scripts/qapi/.isort.cfg actually match
> python/setup.cfg exactly, and can go.
>
> The differences betw
On 22/4/25 07:27, Kohei Tokunaga wrote:
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoi
> On Fri, Apr 18, 2025 at 3:30 PM Dietmar Maurer wrote:
> >
> > Some encoders can hang indefinetly (i.e. nvh264enc) if
>
> indefinitely
>
> > the pipeline is not stopped before it is destroyed
> > (Observed on Debian bookworm).
>
> but why do you need the extra shutdown notifier?
Because Qemu
Hi Cedric,
> Subject: Re: [PATCH v4 09/10] tests/functional/aspeed: Add to test vbootrom
> for AST2700
>
> On 4/17/25 05:12, Jamin Lin wrote:
> > Add the AST2700 functional test to boot using the vbootrom image
> > instead of manually loading boot components with -device loader.
> > The boot ROM
Pierrick Bouvier writes:
[...]
> At this point, I would like to focus on having a first version of TargetInfo
> API, and not reviewing any other changes, as things may be modified, and they
> would need to be reviewed again. It's hard to follow the same abstraction
> done multiple times in mu
On 4/22/25 08:00, Aditya Gupta wrote:
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
Deprecate th
On 25/04/22 07:53AM, Cédric Le Goater wrote:
> On 4/22/25 06:41, Aditya Gupta wrote:
> > <...snip...>
> >
> > diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> > index 05381441a9ff..527f2613dcb5 100644
> > --- a/docs/about/deprecated.rst
> > +++ b/docs/about/deprecated.rst
> > @@
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
Deprecate the 8E and 8NVL variants.
Suggested-by: Cé
QEMU has a way to deprecate CPUs by setting the 'deprecation_note' in
CPUClass.
Currently PowerPC CPUs don't use this deprecation process.
Introduce 'POWERPC_DEPRECATED_CPU' macro to deprecate particular PowerPC
CPUs in future.
With the change, QEMU will print a warning like below when the
depre
Power8E and Power8NVL are not maintained, and not useful to qemu, and
upstream skiboot also has removed support till Power8 DD1.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
No direct way to depre
Philippe Mathieu-Daudé writes:
> The QAPI-generated 'TargetInfo' structure name is only used
> in a single file. We want to heavily use another structure
> similarly named. Rename the QAPI one, since structure names
> are not part of the public API.
>
> Suggested-by: Pierrick Bouvier
> Signed-of
On 4/22/25 06:41, Aditya Gupta wrote:
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
Deprecate th
On 4/22/25 06:41, Aditya Gupta wrote:
QEMU has a way to deprecate CPUs by setting the 'deprecation_note' in
CPUClass.
Currently PowerPC CPUs don't use this deprecation process.
Introduce 'POWERPC_DEPRECATED_CPU' macro to deprecate particular PowerPC
CPUs in future.
With the change, QEMU will p
On 4/22/25 03:59, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v4 02/10] hw/arm/aspeed_ast27x0 Introduce vbootrom
memory region
On 4/17/25 05:11, Jamin Lin wrote:
Introduce a new vbootrom memory region. The region is mapped at
address "0x" and has a size of 128KB, identical to the
Including is still required on Emscripten, just like on other
platforms, to make the ioctl function available.
Signed-off-by: Kohei Tokunaga
---
block/file-posix.c | 4
1 file changed, 4 insertions(+)
V2:
- Split this from the previous 12th patch into a separate commit and revised
the c
Emscripten does not support partial unmapping of mmapped memory
regions[1]. This limitation prevents correct implementation of qemu_ram_mmap
and qemu_ram_munmap, which rely on partial unmap behavior.
As a workaround, this commit excludes mmap-alloc.c from the Emscripten
build. Instead, for Emscrip
On emscripten, some implementations in os-posix.c can't be used such as
daemonizing and changing user. This commit introduces os-wasm.c and
os-wasm.h which are forked from os-posix.c and os-posix.h and patched for
targetting Emscripten.
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS
Emscripten does not support couroutine methods currently used by QEMU but
provides a coroutine implementation called "fiber". This commit introduces a
coroutine backend using fiber. Note that fiber does not support submitting
coroutines to other threads.
Signed-off-by: Kohei Tokunaga
---
MAINTAI
The added Dockerfile is based on the emsdk image, which includes the
Emscripten toolchain. It also cross-compiles the necessary dependencies
(glib, libffi, pixman, and zlib) for the Emscripten target environment.
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS |
has_int128_type is set to false on emscripten as of now to avoid errors by
libffi. Tests are disabled on emscripten because they rely on host
features that aren't supported by emscripten (e.g. fork and unix
socket).
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS | 1 +
configs/
Daemonizing and run-with aren't supported on Emscripten so disable these
flags.
Signed-off-by: Kohei Tokunaga
---
qemu-options.hx | 4 ++--
system/vl.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
V2:
- Unified two consecutive #ifndef macros into a single condition in
qemu-o
Add GitLab CI job that builds QEMU using emscripten. The build runs in the
container defined in tests/docker/dockerfiles/emsdk-wasm32-cross.docker.
Signed-off-by: Kohei Tokunaga
---
.gitlab-ci.d/buildtest-template.yml | 27 +++
.gitlab-ci.d/buildtest.yml | 9 +++
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
Emscripten doesn't provide copy_file_range implementation but it declares
this function in its headers. Meson correctly detects the missing
implementation and unsets HAVE_COPY_FILE_RANGE. However, the stub defined in
file-posix.c causes a type conflict with the declaration from Emscripten
during co
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
Although __builtin___clear_cache is used to flush the instruction cache for
a specified memory region[1], this operation doesn't apply to wasm, as its
memory isn't executable. Moreover, Emscripten does not support this builtin
and fails to compile it with the following error.
> fatal error: error
V2:
- Updated the commit message to explicitly explain that function pointer
casts are performed internally by GLib.
- Fixed typo in the comment in include/glib-compat.h: s/insted/instead/
- In util/cacheflush.c patch, added an explanation for the change to both
the code comment and the commit
On Emscripten, function pointer casts can result in runtime failures due to
strict function signature checks. This affects the use of g_list_sort and
g_slist_sort, which internally perform function pointer casts that are not
supported by Emscripten. To avoid these issues, g_list_sort_with_data and
Hi Harsh,
Thanks for reviewing.
On 25/04/21 04:21PM, Harsh Prateek Bora wrote:
>
>
> On 3/23/25 23:10, Aditya Gupta wrote:
> > <...snip...>
> >
> > +switch (cmd) {
> > +case FADUMP_CMD_REGISTER:
> > +ret_val = do_fadump_register();
> > +if (ret_val != RTAS_OUT_SUCCESS) {
On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini wrote:
>
> Allow using RISCVCPUDef to replicate all the logic of custom .instance_init
> functions. To simulate inheritance, merge the child's RISCVCPUDef with
> the parent and then finally move it to the CPUState at the end of
> TYPE_RISCV_CPU's own i
QEMU has a way to deprecate CPUs by setting the 'deprecation_note' in
CPUClass.
Currently PowerPC CPUs don't use this deprecation process.
Introduce 'POWERPC_DEPRECATED_CPU' macro to deprecate particular PowerPC
CPUs in future.
With the change, QEMU will print a warning like below when the
depre
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
Deprecate the 8E and 8NVL variants.
Suggested-by: Cé
Power8E and Power8NVL are not maintained, and not useful to qemu, and
upstream skiboot also has removed support till Power8 DD1.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
No direct way to depre
Please ignore this mail (only cover letter got sent). Resent another v5.
Sorry for posting this so late, had gone on a vacation.
Thanks,
- Aditya G
Power8E and Power8NVL are not maintained, and not useful to qemu, and
upstream skiboot also has removed support till Power8 DD1.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
No direct way to depre
Power8E and Power8NVL are not maintained, and not useful to qemu, and
upstream skiboot also has removed support till Power8 DD1.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
No direct way to depre
Hi Cedric,
> Cc: Troy Lee ; nabiheste...@google.com
> Subject: Re: [PATCH v4 06/10] hw/arm/aspeed: Add support for loading
> vbootrom image via "-bios"
>
> On 4/17/25 05:12, Jamin Lin wrote:
> > Introduce "aspeed_load_vbootrom()" to support loading a virtual boot
> > ROM image into the vbootrom
Function get_dir_base_width() is used by loongarch_page_table_walker(),
so it is used by KVM mode also, here move this function from directory
tcg to common directory.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu_helper.c | 28
Function loongarch_map_address is to get physical address from virtual
address, it is used by qmp commands to dump memory from virtual
address.
It is used by kvm mode also, here move function loongarch_map_address()
out of macro CONFIG_TCG. And it is common code, the similar with
function loongarc
Function loongarch_cpu_tlb_fill() only works in TCG mode, move its
definition from header file internals.h to file tcg/tcg_loongarch.h
Signed-off-by: Bibo Mao
---
target/loongarch/cpu.c | 1 +
target/loongarch/internals.h | 5 -
target/loongarch/tcg/tcg_loongarch.h | 4
Header file helper.h is specified for tcg mode, move this file to
directory tcg. And create new file helper.h to include header
file in tcg mode.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/helper.h | 720 +
target/loongar
Function loongarch_tlb_search() and loongarch_map_tlb_entry() works
only in TCG mode, move these functions to directory tcg.
There is no any function change, only code moving.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 146 --
target/loongarch/tc
Function loongarch_tlb_search() is only referenced in file tcg/tlb_helper.c,
define this function with static attribution.
Signed-off-by: Bibo Mao
---
target/loongarch/internals.h | 2 --
target/loongarch/tcg/tlb_helper.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --gi
Get physical address from virtual address is important for qmp command to
dump memory content. In TCG mode, it searches TLB tables firstly and
then do page table walker. In KVM mode, there are no TLB tables and page
table walker is used directly.
Here TLB tables searching is moved to directory tcg
Stub function loongarch_get_addr_from_tlb() is added if option
CONFIG_TCG is not enabled, so this function can be called in KVM
only mode.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/t
Function loongarch_get_addr_from_tlb() is added to get physical address
from TLB tables. TLB table only works in TCG mode, in future this
function will be moved to TCG directory.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu_helper.c | 32 +
Define function loongarch_get_addr_from_tlb() non-static, and add its
definition in header file tcg/tcg_loongarch.h
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c| 10 ++
target/loongarch/tcg/tcg_loongarch.h | 16
2 files changed, 18 insertions(+), 8 d
Signed-off-by: Alistair Francis
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d54b5578f8..d1551d9cc6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -328,6 +328,7 @@ F: include/hw/char/riscv_htif.h
F: include/hw/riscv/
F: linux-user/host/riscv
On Thu, Apr 17, 2025 at 5:24 PM Icenowy Zheng wrote:
>
> The j pseudoinstruction maps to a JAL instruction, which can only handle
> a jump to somewhere with a signed 20-bit destination. In case of static
> linking and LTO'ing this easily leads to "relocation truncated to fit"
> error.
>
> Switch t
On 4/18/2025 5:45 PM, Zhao Liu wrote:
On Tue, Apr 01, 2025 at 09:01:16AM -0400, Xiaoyao Li wrote:
Date: Tue, 1 Apr 2025 09:01:16 -0400
From: Xiaoyao Li
Subject: [PATCH v8 06/55] i386/tdx: Introduce is_tdx_vm() helper and cache
tdx_guest object
X-Mailer: git-send-email 2.34.1
It will need sp
On 4/18/2025 5:17 PM, Zhao Liu wrote:
configs/devices/i386-softmmu/default.mak | 1 +
hw/i386/Kconfig | 5 +++
qapi/qom.json| 15 +
target/i386/kvm/meson.build | 2 ++
target/i386/kvm/tdx.c| 43
Hi Cedric,
> Subject: Re: [PATCH v4 02/10] hw/arm/aspeed_ast27x0 Introduce vbootrom
> memory region
>
> On 4/17/25 05:11, Jamin Lin wrote:
> > Introduce a new vbootrom memory region. The region is mapped at
> > address "0x" and has a size of 128KB, identical to the SRAM region
> size.
> >
On 4/18/2025 5:47 PM, Zhao Liu wrote:
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index 86f2c34e7afa..baca2d479365 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-headers/asm-x86/kvm.h
@@ -925,4 +925,73 @@ struct kvm_hyperv_eventfd {
#define KVM_X86_SNP_VM
Hi Cedric,
> Cc: Troy Lee ; nabiheste...@google.com
> Subject: Re: [PATCH v4 02/10] hw/arm/aspeed_ast27x0 Introduce vbootrom
> memory region
>
> On 4/17/25 05:11, Jamin Lin wrote:
> > Introduce a new vbootrom memory region. The region is mapped at
> > address "0x" and has a size of 128KB
cde3247651dc998da5dc1005148302a90d72f21f fixed atomicity for LDRD, which
ends up making accesses 64-bits wide. However, the AST2600 bootloader
can sometimes compile with LDRD instructions, which causes the acceses
to fail when accessing the memory-mapped SPI flash.
To fix this, increase the MMIO r
On 4/21/25 10:58, Eric DeVolder wrote:
Hi,
I've noticed what I believe to be an error in the RISC-V
implementation. The RISC-V spec[1] states:
Note that load and load-reserved instructions generate load
exceptions, whereas store, storeconditional, and AMO instructions
generate store/AMO
On 4/17/25 05:12, Jamin Lin wrote:
Add the AST2700 functional test to boot using the vbootrom image
instead of manually loading boot components with -device loader.
The boot ROM binary is now passed via the
-bios option, using the image located in pc-bios/ast27x0_bootrom.bin.
Signed-off-by: Jami
On 4/17/25 05:12, Jamin Lin wrote:
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/functional/test_aarch64_aspeed.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests
On 4/17/25 05:12, Jamin Lin wrote:
Move the I2C test case into a common helper function (do_ast2700_i2c_test) so it
can be reused across multiple AST2700-based test cases. This reduces duplication
and improves maintainability.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
On 4/17/25 05:11, Jamin Lin wrote:
Introduce a new vbootrom memory region. The region is mapped at address
"0x" and has a size of 128KB, identical to the SRAM region size.
This memory region is intended for loading a vbootrom image file as part of the
boot process.
The vbootrom registere
On 4/17/25 05:12, Jamin Lin wrote:
Introduce "aspeed_load_vbootrom()" to support loading a virtual boot ROM image
into the vbootrom memory region, using the "-bios" command-line option.
Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
---
include/hw/arm/aspeed.h
The bytes type in *bdrv_aio_pdiscard should be int64_t rather than int.
There are no drivers implementing the *bdrv_aio_pdiscard() callback,
it appears to be an unused function. Therefore, we'll simply remove it
instead of fixing it.
Additionally, coroutine-based callbacks are preferred. If someo
Hi,
I've noticed what I believe to be an error in the RISC-V
implementation. The RISC-V spec[1] states:
Note that load and load-reserved instructions generate load
exceptions, whereas store, storeconditional, and AMO instructions
generate store/AMO exceptions.
For an AMO operation, a transla
Eric Blake wrote:
>On Mon, Apr 21, 2025 at 12:19:14AM +0800, Sunny Zhu wrote:
>> Keep it consistent with *bdrv_co_pdiscard.
>>
>> Currently, there is no BlockDriver implemented the bdrv_aio_pdiscard()
>> function,
>> so we don’t need to make any adaptations either.
>
>If there are no drivers impl
* Dongli Zhang (dongli.zh...@oracle.com) wrote:
>
>
> On 4/21/25 6:38 AM, Dr. David Alan Gilbert wrote:
> > Hi Steve,
> > I've just had a go with cpr-transfer, it's quite interesting.
> > I was just trying it on my (AMD) desktop.
> >
> > * I was running with qemu displaying graphics, and after
On 4/17/25 05:11, Jamin Lin wrote:
Introduce a new vbootrom memory region. The region is mapped at address
"0x" and has a size of 128KB, identical to the SRAM region size.
This memory region is intended for loading a vbootrom image file as part of the
boot process.
The vbootrom registere
x-igd-gms is used for overriding DSM region size in GGC register in
both config space and MMIO BAR0, by default host value is used.
There is no need to emulate it in default case.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 49 ++---
1 file changed
In previous commits, several changes were made to IGD passthrough:
* Legacy mode now requires the IGD to be Gen6–Gen9.
* OpRegion quirk is enabled by default.
* "etc/igd-bdsm-size" is set to 0 when guest firmware does not need to
allocate Data Stolen Memory and write BDSM register.
Update the doc
Check the vendor and device ID on GVT-g mdev to ensure it is a supported
device [1]. This extra check is required for automatically enabling
OpRegion access later.
Note that Cherryview and Gemini Lake are marked as supported here since
current code cannot distinguish them with other Gen8 and Gen9
Starting from Intel Core Ultra Series (Meteor Lake), Data Stolen Memory
has became a part of LMEMBAR (MMIO BAR2) [1][2], meaning that BDSM and
GGC register quirks are no longer needed on these platforms.
To support Meteor/Arrow/Lunar Lake and future IGD devices, remove the
generation limitation in
OpRegion is exposed to guest as a read-only fw_cfg item, so hotplugging
with it wouldn't cause issues. Since OpRegion needs to be set up by
guest firmware, a guest reboot is typically required. For linux guests,
i915 driver is able to mock VBT [1] when OpRegion is not present, the
reboot may not re
On Gen9 and later IGD devices, GMS 0xf0 to 0xfe represents 4MB to 60MB
pre-allocated memory size in 4MB increments. Allow users overriding
GMS with these values.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 59 +++
1 file changed, 41 insertions(
Since the last commit, vfio_pci_igd_setup_opregion is only called
in GVT-g mode. Move its functionality into vfio_pci_kvmgt_config_quirk
for more GVT-g-specific error logging.
Also, hotplugging GVT-g vGPU is now always disallowed regardless of
OpRegion to prevent potential issues. Intel has never
As proposed in a previous discussion [1], detect IGD devices based on
whether it has VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION exposed by kernel
and enables OpRegion access by default. This enables out-of-the-box
display output support for IGD passthrough without having to manually
set x-igd-opregion=
As the presence of OpRegion is used to detect IGD device now, and
guest driver usually depends on OpRegion to work. Enable OpRegion
on IGD devices by default for out-of-the-box passthrough experience
(except pre-boot display output), especially for libvirt users.
Example of IGD passthrough with li
There is currently no straightforward way to distinguish if a Intel
graphics device is IGD or discrete GPU. However, only IGD devices expose
OpRegion. Use the presence of VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION
to identify IGD devices.
Signed-off-by: Tomita Moeko
---
hw/vfio/igd.c | 26 ++
Jamin,
On 4/14/25 08:50, Jamin Lin wrote:
Hi Cedric and all,
Subject: Re: [PATCH v2 08/10] pc-bios: Add AST27x0 vBootrom
On 4/10/25 04:38, Jamin Lin wrote:
The boot ROM is a minimal implementation designed to load an AST27x0
boot image.
Its source code is available at:
https://github.com/g
ASLS register represents the base address of OpRegion, and it is
programmed with HPA. In IGD passthrough scenario, it needs to be
reprogrammed with GPA by guest firmware. To prevent guest accessing
wrong memory range, ASLS should always be emulated and cleared.
In GVT-g scenario, emulating ASLS is
Intel only provides legacy VBIOS for IGD up to Gen9, and there is no
CSM support on later devices. Additionally, Seabios can only handle
32-bit BDSM register used until Gen9. Since legacy mode requires VGA
capability, restrict it to Gen6 through Gen9 devices.
Link:
https://lore.kernel.org/qemu-de
On 4/18/25 03:46, Nicholas Piggin wrote:
On Wed Apr 16, 2025 at 5:25 AM AEST, Richard Henderson wrote:
Here we cannot rely on the default copied from
tcg_op_insert_{after,before}, because the relevant
op could be typeless, such as INDEX_op_call.
Fixes: ...
Missing ^
Yeah, I filled in that b
Hello Jamin
On 4/14/25 03:20, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v2 00/10] Support vbootrom for AST2700
Hello Jamin
On 4/10/25 04:38, Jamin Lin wrote:
v1:
Add initial support for AST27x0
The purpose of vbootrom here is to simulate the work of BootMCU SPL
(riscv)
i
On 4/18/25 10:28, Philippe Mathieu-Daudé wrote:
include/hw/core/cpu.h | 2 --
include/qemu/target_info-impl.h | 23 +++
include/qemu/target_info.h | 19 +++
cpu-target.c| 5 -
hw/core/machine-qmp-cmds.c | 1 +
On 4/18/25 10:28, Philippe Mathieu-Daudé wrote:
The QAPI-generated 'TargetInfo' structure name is only used
in a single file. We want to heavily use another structure
similarly named. Rename the QAPI one, since structure names
are not part of the public API.
Suggested-by: Pierrick Bouvier
Signe
On 4/21/25 6:38 AM, Dr. David Alan Gilbert wrote:
> Hi Steve,
> I've just had a go with cpr-transfer, it's quite interesting.
> I was just trying it on my (AMD) desktop.
>
> * I was running with qemu displaying graphics, and after migration
> the source display got updated every time I moved
On Wed, Apr 16, 2025 at 8:12 PM Jamin Lin wrote:
>
> Move the I2C test case into a common helper function (do_ast2700_i2c_test) so
> it
> can be reused across multiple AST2700-based test cases. This reduces
> duplication
> and improves maintainability.
>
> Signed-off-by: Jamin Lin
Reviewed-by:
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