Re: [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_*

On 15/4/25 21:25, Richard Henderson wrote: The i386 backend can now check TCGOP_FLAGS to select the correct set of constraints. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 tcg/aarch64/tcg-target-has.h | 1 - tcg/arm/tcg-target-has.h | 1 - tc

Re: [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS

On 15/4/25 21:25, Richard Henderson wrote: This will enable removing INDEX_op_qemu_st8_*_i32, by exposing the operand size to constraint selection. Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mat

Re: [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc

On 15/4/25 21:24, Richard Henderson wrote: Pass the sparc COND_* value not the tcg TCG_COND_* value. This makes the usage within add2/sub2 clearer. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-)

Re: [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1

On 16/4/25 00:07, Pierrick Bouvier wrote: On 4/15/25 12:24, Richard Henderson wrote: Use per-loop variables instead of one 'i' for the function. Signed-off-by: Richard Henderson ---   tcg/tcg.c | 23 +++   1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/tcg/t

Re: [RFC PATCH 1/2] tests/qtest: Fix virtio msix message endianness

Hi Nick, On 15/4/25 10:19, Nicholas Piggin wrote: msix messages are written to memory in little-endian order, so they should not be byteswapped depending on target endianness, but read as le and converted to host endian by the qtest. Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/virt

Re: [RFC V3 PATCH 05/13] acpi: Send the GPE event of suspend and wakeup for x86

On 15/4/25 23:48, Annie Li wrote: On 4/15/2025 11:29 AM, Philippe Mathieu-Daudé wrote: Hi Annie, On 15/4/25 03:24, Annie Li wrote: On 4/14/2025 11:18 AM, Alex Bennée wrote: Annie Li writes: The GPE event is triggered to notify x86 guest to suppend itself. The function acpi_send_sleep_eve

Re: [PATCH] Hexagon (target/hexagon) Remove gen_tcg_func_table.py

Hi Taylor, On 16/4/25 01:55, Taylor Simpson wrote: This can easily be done in C with opcodes_def_generated.h.inc Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c | 6 ++- target/hexagon/README| 1 - target/hexagon/gen_tcg_func_table.py | 66 -

RE: [PATCH 3/5] vfio/iommufd: Implement .get_cap() in TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO sub-class

>-Original Message- >From: Nicolin Chen >Subject: Re: [PATCH 3/5] vfio/iommufd: Implement .get_cap() in >TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO sub-class > >On Fri, Apr 11, 2025 at 06:17:05PM +0800, Zhenzhong Duan wrote: >> +static int hiod_iommufd_get_vtd_cap(HostIOMMUDevice *hiod, >> +

RE: [PATCH 3/5] hw/arm/virt: Factor out common SMMUV3 dt bindings code

> -Original Message- > From: Nicolin Chen > Sent: Wednesday, April 16, 2025 5:26 AM > To: Shameerali Kolothum Thodi > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; > eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com; > ddut...@redhat.com; berra...@redhat.com; nath...@n

Re: [PATCH v3 0/1] Fix endless translation loop of riscv

On Tue, Apr 15, 2025 at 6:05 PM Ziqiao Kong wrote: > > This version fixes the return value `old_pte` not correctly handled in > my previous patch. > > This patch refers to common usages of qatomic_cmpxchg like those in > target/i386/tcg/system/excp_helper.c and target/arm/ptw.c. I also add > a bri

RE: [PATCH 1/5] vfio/iommufd: Save host iommu capabilities in VFIODevice.caps

>-Original Message- >From: Nicolin Chen >Subject: Re: [PATCH 1/5] vfio/iommufd: Save host iommu capabilities in >VFIODevice.caps > >On Mon, Apr 14, 2025 at 09:30:41AM +, Duan, Zhenzhong wrote: >> >-Original Message- >> >From: Cédric Le Goater >> >> @@ -77,6 +77,7 @@ typedef

Re: [PATCH] virtio: Call set_features during reset

On Thu, Apr 10, 2025 at 3:42 PM Akihiko Odaki wrote: > > virtio-net expects set_features() will be called when the feature set > used by the guest changes to update the number of virtqueues. Call it > during reset as reset clears all features and the queues added for > VIRTIO_NET_F_MQ or VIRTIO_NE

RE: [PATCH 2/5] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices

> -Original Message- > From: Nicolin Chen > Sent: Wednesday, April 16, 2025 5:19 AM > To: Shameerali Kolothum Thodi > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; > eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com; > ddut...@redhat.com; berra...@redhat.com; nath...@n

RE: [PATCH 1/5] hw/arm/smmuv3: Introduce SMMUv3 device

> -Original Message- > From: Nicolin Chen > Sent: Wednesday, April 16, 2025 4:42 AM > To: Shameerali Kolothum Thodi > Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; > eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com; > ddut...@redhat.com; berra...@redhat.com; nath...@n

[PATCH v3 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState

Hi, all: PATCH v3: Use cpu_by_arch_id() instead of qemu_get_cpu(), when registering gpio in sifive_plic_create(). PATCH v2: During plic initialization, CPUSate is obtained by traversing qemu_get_cpu(), which was an early design flaw (see PATCH v1 reviewed). A better approach is to use riscv's

[PATCH v3 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly

riscv_plic_hart_config_string() when getting CPUState via qemu_get_cpu() should be consistent with keeping sifive_plic_realize() by hartid_base + cpu_index. A better approach is to use cpu_by_arch_id() instead of qemu_get_cpu(), in riscv cpu_by_arch_id() uses the mhartid. For non-numa or single-c

[PATCH v2 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState

Hi, all: I made the following changes in version 2 of the patch: Regarding the plic initialization phase to get CPUState by traversing qemu_get_cpu(), this is an early design flaw, a better approach would be to use riscv's hartid for indexing via the interface cpu_by_arch_id(). PATCH v1: https:

[PATCH v2 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly

riscv_plic_hart_config_string() when getting CPUState via qemu_get_cpu() should be consistent with keeping sifive_plic_realize() by hartid_base + cpu_index. A better approach is to use cpu_by_arch_id() instead of qemu_get_cpu(), in riscv cpu_by_arch_id() uses the mhartid. For non-numa or single-c

Re: [PATCH v3 1/1] target/riscv: fix endless translation loop on big endian systems

On Tue, Apr 15, 2025 at 6:06 PM Ziqiao Kong wrote: > > On big endian systems, pte and updated_pte hold big endian host data > while pte_pa points to little endian target data. This means the branch > at cpu_helper.c:1669 will be always satisfied and restart translation, > causing an endless transl

[PATCH v3 07/10] tests/functional/aspeed: Move I2C test into shared helper for AST2700 reuse

Move the I2C test case into a common helper function (do_ast2700_i2c_test) so it can be reused across multiple AST2700-based test cases. This reduces duplication and improves maintainability. Signed-off-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 28 + 1 f

[PATCH v3 08/10] tests/functional/aspeed: Update test ASPEED SDK v09.06

Signed-off-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tests/functional/test_aarch64_aspeed.py b/tests/functional/test_aarch64_aspeed.py index 441f7f3919..337d701917 100755 --- a/tests/functi

[PATCH v3 01/10] hw/arm/aspeed_ast27x0: Rename variable sram_name to name in ast2700 realize

The variable "sram_name" was only used for naming the SRAM memory region. Rename it to "name" for consistency with similar code and avoid unnecessary new local variable declarations. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast27x0.c | 8 1 file changed,

[PATCH v3 03/10] hw/arm/aspeed: Add vbootrom support on AST2700 EVB machines

Introduce a new "vbootrom" field in the AspeedMachineClass to indicate whether a machine supports the virtual boot ROM region. Set this field to true by default for the AST2700-A0 and AST2700-A1 EVB machines. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c |

[PATCH v3 10/10] docs/system/arm/aspeed: Support vbootrom for AST2700

Using the vbootrom image support and the boot ROM binary is now passed via the -bios option, using the image located in pc-bios/ast27x0_bootrom.bin. Signed-off-by: Jamin Lin --- docs/system/arm/aspeed.rst | 29 - 1 file changed, 28 insertions(+), 1 deletion(-) diff -

[PATCH v3 00/10] Support vbootrom for AST2700

v1: Add initial support for AST27x0 The purpose of vbootrom here is to simulate the work of BootMCU SPL (riscv) in AST2700, because QEMU doesn't support heterogenous architecture yet. ast27x0_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for ASPEED AST27x0 BMC SOC. It currently

[PATCH v3 04/10] hw/arm/aspeed: Reuse rom_size variable for vbootrom setup

Move the declaration of `rom_size` to an outer scope in aspeed_machine_init() so it can be reused for setting up the vbootrom region as well. This avoids introducing a redundant local variable and ensures consistent ROM sizing logic when both SPI boot and vbootrom are used. Signed-off-by: Jamin L

[PATCH v3 05/10] hw/arm/aspeed: Add support for loading vbootrom image via "-bios"

Introduce "aspeed_load_vbootrom()" to support loading a virtual boot ROM image into the vbootrom memory region, using the "-bios" command-line option. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 36 2 files changed,

[PATCH v3 09/10] tests/functional/aspeed: Add to test vbootrom for AST2700

Add the AST2700 functional test to boot using the vbootrom image instead of manually loading boot components with -device loader. The boot ROM binary is now passed via the -bios option, using the image located in pc-bios/ast27x0_bootrom.bin. Signed-off-by: Jamin Lin --- tests/functional/test_aar

[PATCH v3 02/10] hw/arm/aspeed_ast27x0 Introduce vbootrom memory region

Introduce a new vbootrom memory region. The region is mapped at address "0x" and has a size of 128KB, identical to the SRAM region size. This memory region is intended for loading a vbootrom image file as part of the boot process. The vbootrom registered in the SoC's address space using th

[PATCH v3 06/10] pc-bios: Add AST27x0 vBootrom

The boot ROM is a minimal implementation designed to load an AST27x0 boot image. Its source code is available at: https://github.com/google/vbootrom Signed-off-by: Jamin Lin --- MAINTAINERS | 1 + pc-bios/README | 6 ++ pc-bios/ast27x0_bootrom.bin | Bin 0 ->

Re: [PATCH v1 0/3] target/i386: Add the immediate form MSR access instruction support

On 1/3/2025 12:48 AM, Xin Li (Intel) wrote: The immediate form of MSR access instructions are primarily motivated by performance, not code size: by having the MSR number in an immediate, it is available *much* earlier in the pipeline, which allows the hardware much more leeway about how a particu

Re: [PATCH v4 04/13] memory: Introduce generic state change parent class for RamDiscardManager

On 4/10/2025 9:44 AM, Chenyi Qiang wrote: > > > On 4/10/2025 8:11 AM, Alexey Kardashevskiy wrote: >> >> >> On 9/4/25 22:57, Chenyi Qiang wrote: >>> >>> >>> On 4/9/2025 5:56 PM, Alexey Kardashevskiy wrote: On 7/4/25 17:49, Chenyi Qiang wrote: > RamDiscardManager is an interfa

Re: [PATCH 1/2] system/main: transfer replay mutex ownership from main thread to main loop thread

On Wed Apr 16, 2025 at 4:31 AM AEST, Pierrick Bouvier wrote: > On 4/14/25 19:41, Nicholas Piggin wrote: >> On Tue Apr 15, 2025 at 1:24 AM AEST, Pierrick Bouvier wrote: >>> On 4/14/25 03:25, Philippe Mathieu-Daudé wrote: On 12/4/25 19:24, Pierrick Bouvier wrote: > On 4/11/25 22:30, Nicholas

[PATCH v5 1/3] system/runstate: add VM state change cb with return value

This patch adds the new VM state change cb type `VMChangeStateHandlerWithRet`, which has return value for `VMChangeStateEntry`. Thus, we can register a new VM state change cb with return value for device. Note that `VMChangeStateHandler` and `VMChangeStateHandlerWithRet` are mutually exclusive and

[PATCH v5 2/3] vhost: return failure if stop virtqueue failed in vhost_dev_stop

This patch captures the error of vhost_virtqueue_stop() in vhost_dev_stop() and returns the error upward. Specifically, if QEMU is disconnected from the vhost backend, some actions in vhost_dev_stop() will fail, such as sending vhost-user messages to the backend (GET_VRING_BASE, SET_VRING_ENABLE)

[PATCH v5 3/3] vhost-user: return failure if backend crash when live migration

Live migration should be terminated if the vhost-user backend crashes before the migration completes. Specifically, since the vhost device will be stopped when VM is stopped before the end of the live migration, in current implementation if the backend crashes, vhost-user device set_status() won't

[PATCH v5 0/3] vhost: fix the IO error after live migration

At the end of the VM live migration, the vhost device will be stopped. Currently, if the vhost-user backend crashes, vhost device's set_status() would not return failure, live migration won't perceive the disconnection with the backend. After the live migration is successful, the stale inflight IO

RE: [PATCH v2 07/10] hw/arm/aspeed: Add support for loading vbootrom image via "-bios"

Hi Nabih, > Subject: Re: [PATCH v2 07/10] hw/arm/aspeed: Add support for loading > vbootrom image via "-bios" > > Hi Jamin, > > > On Tue, Apr 15, 2025 at 2:35 AM Jamin Lin > wrote: > > > > Hi Nabih, > > > > > ; Troy Lee > > > Subject: Re: [PATCH v2 07/10] hw/arm/aspeed: Add support for loadin

Re: [RFC PATCH 2/2] tests/qtest: Enable spapr dma with linear iommu map

On Wed Apr 16, 2025 at 4:07 AM AEST, Fabiano Rosas wrote: > Nicholas Piggin writes: > >> qtests spapr dma was broken because the iommu was not set up. >> >> spapr requires hypercalls to set up the iommu (TCE tables), but >> there is no support for that or a side-channel to the iommu in >> qtests a

Re: [PATCH v9 0/7] Allow to enable multifd and postcopy migration together

Prasad Pandit writes: > From: Prasad Pandit > > Hello, > > > * This series (v9) does minor refactoring and reordering changes as > suggested in the review of earlier series (v8). Also tried to > reproduce/debug a qtest hang issue, but it could not be reproduced. > From the shared stack tr

[PATCH] Hexagon (target/hexagon) Remove gen_tcg_func_table.py

This can easily be done in C with opcodes_def_generated.h.inc Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c | 6 ++- target/hexagon/README| 1 - target/hexagon/gen_tcg_func_table.py | 66 target/hexagon/meson.build

RE: [PATCH v3 3/5] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof

> -Original Message- > From: Brian Cain > Sent: Tuesday, April 15, 2025 12:22 PM > To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; > matheus.bernard...@oss.qualcomm.com; a...@rev.ng; a...@rev.ng; > marco.lie...@oss.qualcomm.com;

Re: [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads in liveness_pass_1

On 4/15/25 12:24, Richard Henderson wrote: Sink the sets of the def, nb_iargs, nb_oargs variables to the default and do_not_remove labels. They're not really needed beforehand, and it avoids preceding code from having to keep them up-to-date. Note that def was *not* kept up-to-date; thankfully

Re: [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1

On 4/15/25 12:24, Richard Henderson wrote: Use per-loop variables instead of one 'i' for the function. Signed-off-by: Richard Henderson --- tcg/tcg.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index ed03840988..9da6c8bb

Re: [PATCH v4 110/163] tcg/riscv: Drop support for add2/sub2

On 4/15/25 12:24, Richard Henderson wrote: We now produce exactly the same code via generic expansion. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target-has.h | 6 +-- tcg/riscv/tcg-target.c.inc | 86 +-

Re: [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2

On 4/15/25 12:24, Richard Henderson wrote: We now produce exactly the same code via generic expansion. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 1 - tcg/mips/tcg-target-con-str.h | 1 - tcg/mips/tcg-target-has.h | 7 ++-- tcg/mips/tcg-target.c.inc | 6

Re: [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts

On 4/15/25 12:24, Richard Henderson wrote: Require TCG_TARGET_HAS_{add2,sub2}_i32 be defined, one way or another. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-has.h | 2 ++ tcg/mips/tcg-target-has.h | 3 +++ tcg/ppc/tcg-target-has.h | 3 +++ tcg/tcg-has.h | 3 ---

Re: [PATCH v4 107/163] tcg: Expand fallback sub2 with 32-bit operations

On 4/15/25 12:24, Richard Henderson wrote: No need to expand to i64 to perform the subtract. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8b1356c526..127338b994 100644

Re: [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations

On 4/15/25 12:24, Richard Henderson wrote: No need to expand to i64 to perform the add. This may smaller on a loongarch64 host, e.g. bstrpick_d r28, r27, 31, 0 bstrpick_d r29, r24, 31, 0 add_d r28, r28, r29 addi_w r29, r28, 0 srai_d r28,

Re: [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64}

On 4/15/25 12:24, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 5 + tcg/optimize.c | 10 +- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++

Re: [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 6 -

Re: [PATCH v4 102/163] tcg/aarch64: Improve deposit

On 4/15/25 12:24, Richard Henderson wrote: Use ANDI for deposit 0 into a register. Use UBFIZ, aka UBFM, for deposit register into 0. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 +- tcg/aarch64/tcg-target.c.inc | 29 - 2 files ch

Re: [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 33 ++ tcg/tci.c| 8 ++-- tcg/aarch64/tcg-target.c.inc | 30 + tcg/arm/tcg-target.c.inc | 29 ++-- tcg/i38

Re: [PATCH v4 100/163] tcg: Convert extrh_i64_i32 to TCGOutOpUnary

On 4/15/25 12:24, Richard Henderson wrote: At the same time, make extrh_i64_i32 mandatory. This closes a hole in which move arguments could be cast between TCGv_i32 and TCGv_i64. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 +-- tcg/tcg.c

Re: [PATCH v4 099/163] tcg: Convert extrl_i64_i32 to TCGOutOpUnary

On 4/15/25 12:24, Richard Henderson wrote: Drop the cast from TCGv_i64 to TCGv_i32 in tcg_gen_extrl_i64_i32 an emit extrl_i64_i32 unconditionally. Move that special case to tcg_gen_code when we find out if the output is live or dead. In this way even hosts that canonicalize truncations can make

Re: [PATCH v4 098/163] tcg: Convert extu_i32_i64 to TCGOutOpUnary

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 15 --- tcg/aarch64/tcg-target.c.inc | 2 -- tcg/i386/tcg-target.c.inc| 2 -- tcg/loongarch64/tcg-target.c.inc | 2 -- tcg/mips/tcg-target.c.inc

Re: [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 22 +++--- tcg/aarch64/tcg-target.c.inc | 2 -- tcg/i386/tcg-target.c.inc| 2 -- tcg/loongarch64/tcg-target.c.inc | 2 -- tcg/mips/tcg-target.c.

Re: [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 ++ tcg/aarch64/tcg-target.c.inc | 18 + tcg/arm/tcg-target.c.inc | 21 ++- tcg/i386/tcg-target.c.inc| 63 ---

Re: [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64}

On 4/15/25 12:24, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 22 +++--- tcg/tcg-op.c | 12 ++-- tcg/tcg.c| 9 +++--

Re: [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64}

On 4/15/25 12:24, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 14 -- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c

Re: [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 20 + tcg/aarch64/tcg-target.c.inc | 28 +++- tcg/arm/tcg-target.c.inc | 23 +- tcg/i386/tcg-target.c.inc| 77 +-

Re: [RFC V3 PATCH 05/13] acpi: Send the GPE event of suspend and wakeup for x86

On 4/15/2025 11:29 AM, Philippe Mathieu-Daudé wrote: Hi Annie, On 15/4/25 03:24, Annie Li wrote: On 4/14/2025 11:18 AM, Alex Bennée wrote: Annie Li writes: The GPE event is triggered to notify x86 guest to suppend itself. The function acpi_send_sleep_event will also trigger GED events on

Re: [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64

On 4/15/25 12:24, Richard Henderson wrote: Even though bswap64 can only be used with TCG_TYPE_I64, rename the opcode to maintain uniformity. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 +++--- tcg/t

Re: [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary

On 4/15/25 12:24, Richard Henderson wrote: Use TCGOutOpUnary instead of TCGOutOpBswap because the flags are not used with this opcode; they are merely present for uniformity with the smaller bswaps. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 1 - tcg/i386/tcg-ta

Re: [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64}

On 4/15/25 12:24, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c

Re: [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap

On 4/15/25 12:24, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/

Re: [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c

Re: [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/

Re: [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 2 +- tcg/tcg.c | 19 ++ tcg/arm/tcg-target.c.inc | 25 ++-- tcg/i386/tcg-target.c.inc | 71 +-- tcg

Re: [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 2 +- tcg/tcg.c | 30 + tcg/arm/tcg-target.c.inc | 20 +++ tcg/i386/tcg-target.c.inc | 62 ++-

Re: [PATCH v4 084/163] tcg/ppc: Expand arguments to tcg_out_cmp2

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 +++-- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 1782d05290..669c5eae4a 100644 --- a/tcg

Re: [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2

On 4/15/25 12:23, Richard Henderson wrote: Pass explicit arguments instead of arrays. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc inde

Re: [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp

On 4/15/25 12:23, Richard Henderson wrote: Use U and C constraints for brcond2 and setcond2, so that tcg_out_cmp2 automatically passes in-range constants to tcg_out_cmp. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 4 +-- tcg/ppc/tcg-target.c.inc | 49

Re: [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/mips/tcg-target-con-set.h| 3 ++- tcg/s390x/tcg-target-con-set.h | 1 - tcg/sparc64/tcg-target-con-set.h | 2 +- tcg/tcg.c

Re: [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 6 +++--- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 24 tcg/tci

Re: [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/mips/tcg-target-con-set.h| 4 +-- tcg/riscv/tcg-target-con-set.h | 2 +- tcg/sparc64/tcg-target-con-set.h | 2 +- tcg/tcg.c

Re: [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}`

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 6 ++ target/sh4/translate.c | 6 +++--- tcg/optimize.c | 32 tcg/tcg-op.c | 8 tcg/tcg.c

Re: [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h| 2 +- tcg/sparc64/tcg-target-con-set.h | 1 - tcg/tcg.c| 31 tcg/aarch64/tcg-target.c.inc | 121 --- tcg/

Re: [PATCH v4 073/163] tcg/mips: Support negsetcond

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-has.h | 4 ++-- tcg/mips/tcg-target.c.inc | 25 + 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h

Re: [PATCH v4 074/163] tcg/tci: Support negsetcond

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tci/tcg-target-has.h | 4 ++-- tcg/tci/tcg-target.c.inc | 13 + 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h index 2402889be

Re: [PATCH v4 072/163] tcg/loongarch64: Support negsetcond

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-has.h | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 34 ++-- 3 files changed, 29 insertions(+), 11 deletio

Re: [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 --

Re: [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 + tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.

Re: [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 --

Re: [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 9 +++-- tcg/tcg-op.c | 21 ++--- tcg/tcg.c| 6 ++ tcg/tci.c| 6 ++ docs

Re: [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/

Re: [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 --

Re: [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 -

Re: [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 6 ++--- tcg/optimize.c | 20 - tcg/tcg-op.c | 48 tcg/tcg.c| 12 -- tcg/tci.c

Re: [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: For aarch64, arm, loongarch64, mips, we can drop rotl. For ppc, s390x we can drop rotr. Only x86, riscv (and tci) have both rotl and rotr. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h

Re: [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend

On 4/15/25 12:23, Richard Henderson wrote: Many host architectures do not implement both rotate right and rotate left and require the compiler to negate the shift count to rotate the opposite direction. We have been requiring the backend to perform this transformation. Do this during opcode expa

Re: [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++- tcg/aarch64/tcg-target.c.inc | 37 - tcg/arm/tcg-target.c.inc | 26 tcg/i386/tcg-target.c.inc| 46 -

Re: [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 +++-- tcg/aarch64/tcg-target.c.inc | 37 ++- tcg/arm/tcg-target.c.inc | 24 ++ tcg/i386/tcg-target.c.inc| 33 +++

Re: [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg

Re: [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Rename to INDEX_op_rems to emphasize signed inputs, and mirroring INDEX_op_remu_*. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 +++- tcg/tcg-op.c | 8 tcg/tcg.

Re: [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 -- tcg/tci.c| 4 ++-- tcg/

Re: [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Rename to INDEX_op_divs2 to emphasize signed inputs, and mirroring INDEX_op_divu2_*. Document the opcode. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/tcg-op.c | 16 tcg/tcg.c |

Re: [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem

On 4/15/25 12:23, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/riscv/tcg-target-has.h | 2 -- tcg/s390x/tcg-target-has.h | 2 -- tcg/tcg-has.h| 7

Re: [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary

On 4/15/25 12:23, Richard Henderson wrote: For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/loongar

Re: [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64}

On 4/15/25 12:23, Richard Henderson wrote: Rename to INDEX_op_divs to emphasize signed inputs, and mirroring INDEX_op_divu_*. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 +++- tcg/tcg-op.c | 16

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