Hi Cedric and all,
> Subject: Re: [PATCH v2 08/10] pc-bios: Add AST27x0 vBootrom
>
> On 4/10/25 04:38, Jamin Lin wrote:
> > The boot ROM is a minimal implementation designed to load an AST27x0
> boot image.
> > Its source code is available at:
> > https://github.com/google/vbootrom
>
> See comm
On 19/02/2025 15.24, Philippe Mathieu-Daudé wrote:
Not all binaries contain the same set of devices. Since some
tests depend on specific devices, we need to check their
availability in the binary.
QemuSystemTest::require_device() allows for system tests to
explicitly check for a particular devic
On 4/11/2025 3:42 PM, Ewan Hai wrote:
On 4/11/25 11:22 AM, Zhao Liu wrote:
On Thu, Apr 10, 2025 at 10:07:15PM +0800, Ewan Hai wrote:
Date: Thu, 10 Apr 2025 22:07:15 +0800
From: Ewan Hai
Subject: Re: [PATCH v2] target/i386: Fix model number of Zhaoxin
YongFeng
vCPU template
On 4/10/25 8
Annie Li writes:
> Followng hmp/qmp commands are implemented for pressing virtual
> sleep button,
>
> hmp: system_sleep
> qmp: { "execute": "system_sleep" }
>
> These commands put the guest into suspend or other power states
> depending on the power settings inside the guest.
>
> These hmp/qmp co
Support dropping all existing mappings on reset. When the guest kernel
reboots it will create new ones, but other components that run before
the kernel (e.g. OVMF) should not be able to use existing mappings from
the previous boot.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 68 ++
Simplify amdvi_page_walk() by making it call the fetch_pte() helper that
is already in use by the shadow page synchronization code. Ensures all
code uses the same page table walking algorithm.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 60 +
Raman Dzehtsiar writes:
> This patch extends the blockdev-backup QMP command to allow users to specify
> how to behave when IO errors occur during copy-before-write operations.
> Previously, the behavior was fixed and could not be controlled by the user.
>
> The new 'on-cbw-error' option can be s
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table
8: V, TV, and GV Fields in Device Table Entry), specifies that a DTE
with V=0, TV=1 does not contain a valid address translation information.
If a request requires a table walk, the walk is terminated when this
condition is enco
On Fri, Apr 11, 2025 at 2:19 AM Paolo Bonzini wrote:
>
> qtest_set_command_cb passed to g_once should match GThreadFunc,
> which it does not. But using g_once is actually unnecessary,
> because the function is called by riscv_harts_realize() under
> the Big QEMU Lock.
>
> Reported-by: Kohei Tokun
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34 +++
On 4/8/25 11:55 AM, Zhuoying Cai wrote:
Enable secure IPL in audit mode, which performs signature verification,
but any error does not terminate the boot process. Only warnings will be
logged to the console instead.
Add a comp_len variable to store the length of a segment in
zipl_load_segment
Hi Cedric,
> Subject: Re: [PATCH v2 04/10] hw/arm/aspeed_ast27x0 Introduce vbootrom
> memory region
>
> On 4/10/25 04:38, Jamin Lin wrote:
> > Introduce a new vbootrom memory region. The region is mapped at
> > address "0x" and has a size of 128KB, identical to the SRAM region
> size.
> >
Sorry for sending this again as I found previous patch series does not
work on riscv32 due to target_ulong is not le64. Please ignore my
previous v1 patch. Below is the original cover letter to illustrate the
purpose of the patch:
Hello! I'm Ziqiao Kong, the maintainer of Unicorn Engine, a fork of
On big endian systems, pte and updated_pte hold big endian host data
while pte_pa points to little endian target data. This means the branch
at cpu_helper.c:1669 will be always satisfied and restart translation,
causing an endless translation loop.
Signed-off-by: Ziqiao Kong
---
target/riscv/cpu
Hi Cedric,
> Subject: Re: [PATCH v2 07/10] hw/arm/aspeed: Add support for loading
> vbootrom image via "-bios"
>
> On 4/10/25 04:38, Jamin Lin wrote:
> > Introduce "aspeed_load_vbootrom()" to support loading a virtual boot
> > ROM image into the vbootrom memory region, using the "-bios"
> command
Header file helper.h is specified for tcg mode, move this file to
directory tcg. And create new file helper.h to include header
file in tcg mode.
Signed-off-by: Bibo Mao
---
target/loongarch/helper.h | 720 +
target/loongarch/tcg/helper.h | 722 +++
Hi Cedric,
> Subject: Re: [PATCH v2 00/10] Support vbootrom for AST2700
>
> Hello Jamin
>
> On 4/10/25 04:38, Jamin Lin wrote:
> > v1:
> >Add initial support for AST27x0
> >The purpose of vbootrom here is to simulate the work of BootMCU SPL
> (riscv)
> >in AST2700, because QEMU does
Keep a record of mapped IOVA ranges per address space, using the
iova_tree implementation. Besides enabling optimizations like avoiding
unnecessary notifications, a record of existing mappings
makes it possible to determine if a specific IOVA is mapped by the guest
using a large page, and adjust t
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices. Attach it to the NPCM8XX.
Tested:
NPCM8XX PSPI driver probed successfully from dmesg log.
Signed-off-by: Tim Lee
---
hw/arm/npcm8xx.c | 11 ++-
include/hw/arm/npcm8xx.h | 2
Hi Cedric,
> Subject: Re: [PATCH v2 09/10] tests/functional/aspeed: Update AST2700
> functional test to use vbootrom
>
> On 4/10/25 04:38, Jamin Lin wrote:
> > Refactor the AST2700 functional test to boot using the vbootrom image
> > instead of manually loading boot components with -device loader
A guest must issue an INVALIDATE_DEVTAB_ENTRY command after changing a
Device Table entry (DTE) e.g. after attaching a device and setting up
its DTE. When intercepting this event, determine if the DTE has been
configured for paging or not, and toggle the appropriate memory regions
to allow DMA addr
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 3f9a
The current amdvi_page_walk() is designed to be called by the replay()
method. Rather than drastically altering it, introduce helpers to fetch
guest PTEs that will be used by a page walker implementation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 125
When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the
address and size of the invalidation and sync the guest page table state
with the host. This requires walking the guest page table and calling
notifiers registered for address spaces matching the domain ID encoded
in the command.
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 74 +
1 file changed, 74 insert
A replay() method is necessary to efficiently synchronize the host page
tables after VFIO registers a notifier for IOMMU events. It is called
to ensure that existing mappings from an IOMMU memory region are
"replayed" to a specified notifier, initializing or updating the shadow
page tables on the h
Enable the appropriate memory region for an address space depending on
the address translation mode selected for it. This is currently based on
a generic x86 IOMMMU property, and only done during the address space
initialization. Extract the code into a helper and toggle the regions
based on whethe
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error conditions.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 47
In order to enable device assignment with IOMMU protection and guest
DMA address translation, IOMMU notifier support is necessary to allow
users like VFIO to synchronize the shadow page tables i.e. to receive
notifications when the guest updates its IO page tables and replay the
mappings onto host
Make amdvi_get_pte_entry() return an error value (-1) in cases where the
memory read fails, versus the current return of 0 to indicate failure.
The reason is that 0 is also a valid PTE value, and it is useful to know
when a PTE points to memory that is zero i.e. the guest unmapped the
page.
Signed
This series adds support for guests using the AMD vIOMMU to enable DMA
remapping for VFIO devices. In addition to the currently supported
passthrough (PT) mode, guest kernels are now able to to provide DMA
address translation and access permission checking to VFs attached to
paging domains, using t
Do not emit an I/O page fault on amdvi_page_walk() when a valid mapping
is not found. The current role of amdvi_page_walk() is to be a helper
for the translate() method and ultimately the IOMMU replay()
functionality. These operations might be executed while the guest is
running, but do not necessa
When the kernel IOMMU driver issues an INVALIDATE_IOMMU_ALL, the address
translation and interrupt remapping information must be cleared for all
Device IDs and all domains. Introduce a helper to sync the shadow page
table for all the address spaces with registered notifiers, which
replays both MAP
Invalidating the entire address space (i.e. range of [0, ~0ULL]) is a
valid and required operation by vIOMMU implementations. However, such
invalidations currently trigger an assertion unless they originate from
device IOTLB invalidations.
Although in recent Linux guests this case is not exercised
Function loongarch_tlb_search() and loongarch_map_tlb_entry() works
only in TCG mode, move these functions to directory tcg.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 153 --
target/loongarch/internals.h | 14 ++-
target/loongarch/tcg/tlb_h
Get physical address from virtual address is important for qmp command to
dump memory content. In TCG mode, it searches TLB tables firstly and
then do page table walker. In KVM mode, there is no TLB tables and page
table walker is used directly.
Here TLB tables searching is moved to directory tcg,
Hi Vladimir,
Thank you for your review.
> The patch looks good to me. Still, could you also provide a test for a new
> option?
> Probably the simplest would be add a test-case to
> `tests/qemu-iotests/tests/copy-before-write`, where existing on-cbw-error
> option is tested. Or you can make a se
Function loongarch_get_addr_from_tlb() is added to get physical address
from TLB tables. TLB table only works in TCG mode, in future this
function will be moved to TCG directory.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 29 +++--
1 file changed, 23 inse
Function get_dir_base_width() is used by loongarch_page_table_walker(),
so it is used by KVM mode also, here move this function from directory
tcg to common directory.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 28
target/loongarch/tcg/tlb_helper
Function loongarch_map_address is to get physical address from virtual
address, it is used by qmp commands to dump memeory from virtual
address.
It is used by kvm mode also, here move function loongarch_map_address()
out of macro CONFIG_TCG. And it is common code, the similiar with
function loonga
This patch extends the blockdev-backup QMP command to allow users to specify
how to behave when IO errors occur during copy-before-write operations.
Previously, the behavior was fixed and could not be controlled by the user.
The new 'on-cbw-error' option can be set to one of two values:
- 'break-g
On big endian systems, pte and updated_pte holds big endian host data
while pte_pa points to little endiaon target data. This means the branch
at cpu_helper.c:1669 will never be satisfied and thus causes an endless
translation loop.
Signed-off-by: Ziqiao Kong
---
target/riscv/cpu_helper.c | 4 ++
On 4/10/25 15:34, Cédric Le Goater wrote:
> + Corvin
>
> On 4/9/25 19:18, Alex Williamson wrote:
>> On Wed, 26 Mar 2025 01:22:39 +0800
>> Tomita Moeko wrote:
>>
>>> So far, all Intel VGA adapters, including discrete GPUs like A770 and
>>> B580, were treated as IGD devices. While this had no fun
Hello! I'm Ziqiao Kong, the maintainer of Unicorn Engine, a fork of
QEMU. When I port Unicorn Engine to s390x, I notice there is a bug in
the implementation of RISCV MMU. It uses qemu_map_ram_ptr to get a
pointer and reads it directly, instead of bswap or address_space_ldl,
which causes an endless
On 4/11/25 00:40, Nicholas Piggin wrote:
On Sun Apr 6, 2025 at 12:00 AM AEST, Guenter Roeck wrote:
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel writes the high word first. This results in an
initialization failure.
This should probably be re
From: Arthur Sengileyev
In msys2 distribution objdump from gcc is using single tab character
prefix, but objdump from clang is using 4 white space characters instead.
The script will not identify any dll dependencies for a QEMU build
generated with clang. This in turn will fail the build, because
From: Stefan Weil via
Signed-off-by: Stefan Weil
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
docs/about/deprecated.rst | 4 ++--
docs/devel/codebase.rst| 6 +++---
docs/devel/qapi-domain.rst | 4 ++--
include/exec/memory.h | 4 ++--
qapi/qdev.json | 2
From: Richard Henderson
With acce728cbc6c we disallowed configuring 64-bit guests on
32-bit hosts, but forgot to document that in removed-features.
Signed-off-by: Richard Henderson
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
docs/about/removed-features.rst | 9 +
The following changes since commit 56c6e249b6988c1b6edc2dd34ebb0f1e570a1365:
Update version for v10.0.0-rc3 release (2025-04-09 04:33:10 -0400)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches
for you to fetch changes up to d08c08320a358010
On 4/10/25 01:18, Alex Williamson wrote:
> On Wed, 26 Mar 2025 01:22:39 +0800
> Tomita Moeko wrote:
>
>> So far, all Intel VGA adapters, including discrete GPUs like A770 and
>> B580, were treated as IGD devices. While this had no functional impact,
>> a error about "unsupported IGD device" will
The following changes since commit 56c6e249b6988c1b6edc2dd34ebb0f1e570a1365:
Update version for v10.0.0-rc3 release (2025-04-09 04:33:10 -0400)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches
for you to fetch changes up to b0b5af62ef9eaf25
From: Stefan Weil via
Signed-off-by: Stefan Weil
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
docs/about/deprecated.rst | 4 ++--
docs/devel/codebase.rst| 6 +++---
docs/devel/qapi-domain.rst | 4 ++--
include/exec/memory.h | 4 ++--
qapi/qdev.json | 2
From: Arthur Sengileyev
In msys2 distribution objdump from gcc is using single tab character
prefix, but objdump from clang is using 4 white space characters instead.
The script will not identify any dll dependencies for a QEMU build
generated with clang. This in turn will fail the build, because
Hi Christian,
> > > > Emscripten's fiber does not support submitting coroutines to other
> > > > threads. So this commit modifies hw/9pfs/coth.h to disable this
behavior
> > > > when compiled with Emscripten.
> > >
> > > The lack of being able to dispatch a coroutine to a worker thread is
one
> >
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