On Tue, Apr 8, 2025 at 2:14 PM Cindy Lu wrote:
>
> For VDPA devices, Allow configurations where both the hardware MAC address
> and QEMU command line MAC address are zero.
>
Let's explain why this can work.
Thanks
On Tue, Apr 8, 2025 at 2:13 PM Cindy Lu wrote:
>
> For VDPA devices, Allow configurations where the hardware MAC address
> is non-zero while the MAC address in the QEMU command line is zero.
>
> Signed-off-by: Cindy Lu
> ---
> hw/net/virtio-net.c | 14 ++
> 1 file changed, 14 inserti
On Tue, Apr 8, 2025 at 2:13 PM Cindy Lu wrote:
>
> When using a VDPA device, it is important to ensure that the MAC
> address is correctly set. The MAC address in the hardware should
> match the MAC address from the QEMU command line. This is a recommended
> configuration and will allow the system
On Tue, Apr 8, 2025 at 2:13 PM Cindy Lu wrote:
>
> When using a VDPA device, it's important to ensure that the MAC
> address is correctly set.
> Add a new parameter in qemu cmdline to enable this check, default value
> is false
>
> The usage is:
>
> -netdev
> type=vhost-vdpa,vhostdev=/dev/vh
On 4/7/2025 5:53 PM, Xiaoyao Li wrote:
> On 4/7/2025 3:49 PM, Chenyi Qiang wrote:
>> Modify memory_region_set_ram_discard_manager() to return false if a
>> RamDiscardManager is already set in the MemoryRegion.
>
> It doesn't return false, but -EBUSY.
Nice catch! Forgot to modify this commit m
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, March 26, 2025 1:34 AM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re:
For VDPA devices, Allow configurations where both the hardware MAC address
and QEMU command line MAC address are zero.
Signed-off-by: Cindy Lu
---
hw/net/virtio-net.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 45b63eb9de..6c6
On 4/2/2025 6:50 PM, Daniel P. Berrangé wrote:
CC libvirt / Jiri, for confirmation about whether the CPUID restrictions
listed below will have any possible impact on libvirt CPUID handling...
On Tue, Apr 01, 2025 at 09:02:05AM -0400, Xiaoyao Li wrote:
Add docs/system/i386/tdx.rst for TDX suppor
From: Fan Ni
With the change, if "mctp-msg-forward" property is turned on for
i2c_mctp_cxl device, we setup a QMP connection to the other VM identified
by the "qmp" property, and forward the MCTP requests to the VM for processing.
Note:
1. The VM with "mctp-msg-forward=on" acts as a FM VM.
2. Be
From: Fan Ni
Add a new QAPI "qmp-cxl-process-mctp-message" to process the MCTP
request cached in the shared buffer from FM VM.
Signed-off-by: Fan Ni
---
hw/mem/cxl_type3.c | 41
hw/mem/cxl_type3_stubs.c | 5 +
qapi/cxl.json| 18 ++
From: Fan Ni
The RFC provides a way for FM emulation in Qemu. The goal is to provide
a context where we can have more FM emulation discussions and share solutions
for a reasonable FM implementation in Qemu.
The basic idea is,
We have two VMs, one is the VM we want to test (named Target VM) and
On 4/2/2025 7:51 PM, Daniel P. Berrangé wrote:
On Tue, Apr 01, 2025 at 09:01:23AM -0400, Xiaoyao Li wrote:
From: Isaku Yamahata
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https://lore.ker
This implementation provides emulation for the Xiangshan Kunminghu
FPGA prototype platform, including support for UART, CLINT, IMSIC,
and APLIC devices. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Signed-off-by: qinshaoqing
Signed-off-by: Yang Wang
Signed-off-by: Yu H
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized based on four RISC-V specifications: Volume
On 4/5/25 07:43, Philippe Mathieu-Daudé wrote:
On 5/4/25 03:03, Pierrick Bouvier wrote:
On 4/4/25 14:54, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:21, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Extract PSCI definitions (which are not target specific)
to the new "t
On 2025/4/4 下午7:59, Igor Mammedov wrote:
On Fri, 21 Mar 2025 15:35:37 +0800
bibo mao wrote:
On 2025/3/21 下午3:21, Markus Armbruster wrote:
bibo mao writes:
+Igor
On 2025/3/21 下午2:47, Markus Armbruster wrote:
Bibo Mao writes:
In function virt_cpu_unplug(), it will send cpu unpl
On 4/3/2025 4:10 PM, Daniel P. Berrangé wrote:
On Thu, Apr 03, 2025 at 03:28:43PM +0800, Xiaoyao Li wrote:
On 4/2/2025 11:49 PM, Daniel P. Berrangé wrote:
On Wed, Apr 02, 2025 at 11:26:11PM +0800, Xiaoyao Li wrote:
I guess the raw mode was introduced due to the design was changed to let
guest
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 7, 2025 11:18 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PA
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 7, 2025 11:16 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PA
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Hi
Please resend the series with a cover letter
(https://www.qemu.org/docs/master/devel/submitting-a-patch.html#use-git-format-patch)
Some people prefer when the commit message has content too :)
At least, it would be useful if you point to a client that supports
the codec and allow us to test/u
On Mon, 7 Apr 2025 12:27:00 -0700 Brian Cain
wrote:
>
> Brian Cain (5):
> target/hexagon: handle .new values
> target/hexagon: Fix badva reference, delete CAUSE
> target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
> target/hexagon: s/pkt_has_store/pkt_has_scalar_store
> t
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..6803908718 100755
--- a/target/hexagon/hex_common.py
+++ b/target/he
On Mon, Apr 7, 2025 at 12:00 PM Kevin Wolf wrote:
>
> Originally, all failed SG_IO requests called scsi_handle_rw_error() to
> apply the configured error policy. However, commit f3126d65, which was
> supposed to be a mere refactoring for scsi-disk.c, broke this and
> accidentally completed the SCS
- Split `read()` DR case into `read_data_register()`
Signed-off-by: Rakesh Jeyasingh
---
rust/hw/char/pl011/src/device.rs | 39
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
ind
Thanks a lot for the response, I really appreciate your time.
On 07.04.2025 14:33, Markus Armbruster wrote:
Mario Fleischmann writes:
This patch series introduces support for the Multi-Core Debug (MCD) API, a
commonly used debug interface by emulators. The MCD API, defined through a
header f
Hi Ali,
On 3/10/25 5:23 PM, Alireza Sanaee via wrote:
> This patch addresses cache description in the `aarch64_max_tcg_initfn`
> function for cpu=max. It introduces three layers of caches and modifies
> the cache description registers accordingly.
>
> Signed-off-by: Alireza Sanaee
> Reviewed-by:
An L2 KVM guest fails to boot inside a pSeries LPAR when booted with a
memory more than 128 GB and PCI device passthrough. The L2 guest also
crashes when it is booted with a memory greater than 128 GB and a PCI
device is hotplugged later.
The issue arises from a conditional check for `levels > 1`
Hello!
I was messing around in Windows NT 4.0 and when i tried to back it up it
asked for a tape drive. After that i tried all sorts of stuff from
emulating a generic SCSI drive to modifying the registry of the OS but no
luck! I would like an easier way of emulating a tape drive without physical
d
Full Unit Access (FUA) is an optimization where a disk write with the
flag set will be persisted to disk immediately instead of potentially
remaining in the disk's write cache.
This commit address the todo task
for using pwritev2() with RWF_DSYNC in the thread pool section of
raw_co_prw(), if pwri
On Wed, Mar 26, 2025 at 2:53 PM Gerd Hoffman wrote:
>
> Hi,
>
> > > >2) The security posture of the system may be different between 2
> > > > validly
> > > > signed images. Think of Daniel's example of verbose kernel output.
> > > > Maybe I
> > > > consider verbose kernel output already in
From: Brian Cain
The BADVA reg is referred to with the wrong identifier. The
CAUSE reg field of SSR is not yet modeled.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 76
Changes since previous "misc hexagon patches" series (v1):
- removed not-yet-usable/necessary from_subtype()
- changed author to match MAINTAINERS
- dropped 'Add memory order definition' patch, now carried in Phil's
https://lore.kernel.org/qemu-devel/20250405161320.76854-1-phi...@linaro.org/
Brian
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6803908718..a2dcb0aa2e 100755
--- a/target/hexagon/hex_common.py
+++ b/target/
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..6803908718 100755
--- a/target/hexagon/hex_common
From: Brian Cain
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/insn.h | 4 ++--
target/hexagon/macros.h
From: Brian Cain
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/decode.c b/target/hexa
On Fri, Apr 04, 2025 at 10:31:53PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> Actualize documentation and synchronize it for commands which actually
> call the same functions internally.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> qapi/block-core.json | 59 +
On 3/13/25 06:40, Steven Lee wrote:
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA3
On Fri, Apr 04, 2025 at 10:31:54PM +0300, Vladimir Sementsov-Ogievskiy wrote:
In the subject line: s/derpecate/deprecate/
> For change, pause, resume, complete, dismiss and finalize actions
> corresponding job- and block-job commands are almost equal. The
> difference is in find_block_job_locked(
On Fri, Apr 04, 2025 at 02:14:02PM +0200, Markus Armbruster wrote:
> Markus Armbruster (11):
> docs/devel/qapi-code-gen: Tidy up whitespace
> qapi/rocker: Tidy up query-rocker-of-dpa-flows example
> docs/interop: Delete "QEMU Guest Agent Protocol Reference" TOC
> docs/interop: Sanitize QMP
Add GitLab CI job that builds QEMU using emscripten. The build runs in the
added Dockerfile that contains dependencies (glib, libffi, pixman, zlib)
compiled by emscripten.
Signed-off-by: Kohei Tokunaga
---
.gitlab-ci.d/buildtest-template.yml | 27
.gitlab-ci.d/buildtest.yml
Emscripten does not support couroutine methods currently used by QEMU but
provides a coroutine implementation called "fiber". This commit introduces a
coroutine backend using fiber. Note that fiber does not support submitting
coroutines to other threads.
Signed-off-by: Kohei Tokunaga
---
util/co
To enable 64-bit guest support in Wasm 32bit memory model today, it was
necessary to partially revert recent changes that removed support for
different pointer widths between the host and guest (e.g., commits
a70af12addd9060fdf8f3dbd42b42e3072c3914f and
bf455ec50b6fea15b4d2493059365bf94c706273) whe
On Fri, Apr 04, 2025 at 02:14:08PM +0200, Markus Armbruster wrote:
> Accept "... lorem ipsum ..." in addition to "...".
>
> Signed-off-by: Markus Armbruster
> ---
> @@ -1062,7 +1064,7 @@ For example::
># "device": "ide0-hd0",
># ...
># }
> - #
Signed-off-by: Kohei Tokunaga
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d54b5578f8..ea5fde475c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3903,6 +3903,17 @@ F: tcg/tci/
F: tcg/tci.c
F: disas/tci.c
+WebAssembly TCG targ
Signed-off-by: Kohei Tokunaga
---
util/mmap-alloc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/util/mmap-alloc.c b/util/mmap-alloc.c
index ed14f9c64d..91f33682e8 100644
--- a/util/mmap-alloc.c
+++ b/util/mmap-alloc.c
@@ -145,6 +145,7 @@ static bool map_noreserve_effec
Signed-off-by: Kohei Tokunaga
---
block/file-posix.c| 18 ++
include/qemu/cacheflush.h | 3 ++-
os-posix.c| 5 +
util/cacheflush.c | 3 ++-
4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.
Emscripten's fiber does not support submitting coroutines to other
threads. So this commit modifies hw/9pfs/coth.h to disable this behavior
when compiled with Emscripten.
Signed-off-by: Kohei Tokunaga
---
fsdev/file-op-9p.h | 3 +++
fsdev/meson.build | 2 +-
hw/9pfs/9p-util-stub.c | 4
has_int128_type is set to false on emscripten as of now to avoid errors by
libffi. And tests aren't integrated with Wasm execution environment as of
now so this commit disables tests.
Signed-off-by: Kohei Tokunaga
---
configs/meson/emscripten.txt | 6 ++
configure | 7
On 3/13/25 06:40, Steven Lee wrote:
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the TSP INTC and INTCIO controllers is simi
On Fri, Apr 04, 2025 at 02:14:04PM +0200, Markus Armbruster wrote:
> The command can return any number of RockerOfDpaFlow objects. The
> example shows it returning exactly two, with the second objecy's
object's
> members elided. Tweak it so it elides elements after the first
> instead.
>
--
On emscripten, function pointer casts can cause function call failure.
This commit fixes the function definition to match to the type of the
function call.
- qtest_set_command_cb passed to g_once should match to GThreadFunc
- object_class_cmp and cpreg_key_compare are passed to g_list_sort as
GC
On Mon, Apr 07, 2025 at 02:46:17PM +0530, prashant patil wrote:
> Thanks Eric.
[top-posting makes conversations harder to follow, so on this list we
typically reply inline]
> I have a few questions about the bitmap content shown by 'qemu-img map'.
> From below sample bitmap data:
> 1. Why only so
Please ignore this patchset as I missed to add version information in it. I'll
resend these patches shortly. Sorry for the noise.
Thanks,
Amit
On 2025/04/07 07:53 PM, Amit Machhiwal wrote:
> Introduce an Error ** parameter to vfio_spapr_create_window() to enable
> structured error reporting. This
An L2 KVM guest fails to boot inside a pSeries LPAR when booted with a
memory more than 128 GB and PCI device passthrough. The L2 guest also
crashes when it is booted with a memory greater than 128 GB and a PCI
device is hotplugged later.
The issue arises from a conditional check for `levels > 1`
Introduce an Error ** parameter to vfio_spapr_create_window() to enable
structured error reporting. This allows the function to propagate
detailed errors back to callers.
Suggested-by: Cédric Le Goater
Signed-off-by: Amit Machhiwal
---
hw/vfio/spapr.c | 23 ---
1 file change
On Fri, Apr 04, 2025 at 02:49:08PM +0200, Hanna Czenczek wrote:
> On 27.03.25 16:55, Stefan Hajnoczi wrote:
> > On Tue, Mar 25, 2025 at 05:06:54PM +0100, Hanna Czenczek wrote:
> > > FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
> > > (via open("/dev/fuse") + ioctl(FUSE_DEV
On 4/7/25 6:19 AM, Huang Borong wrote:
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized
On Sat, Apr 05, 2025 at 04:52:29PM -0700, Pinku Deb Nath wrote:
> Full Unit Access (FUA) is an optimization where a disk write with the
> flag set will be persisted to disk immediately instead of potentially
> remaining in the disk's write cache.
>
> This commit address the todo task
> for using p
This is the v4 series of the shared device assignment support.
Compared with v3 series, the main changes are:
- Introduced a new GenericStateManager parent class, so that the existing
RamDiscardManager and new PrivateSharedManager can be its child class
and manage different states.
- Changed
Hi Philippe,
On 4/3/25 10:40 PM, Philippe Mathieu-Daudé wrote:
> Citing Gustavo [*]:
>
> Gating IORT table generation entirely based on the presence
> of ITS looks wrong because IORT table has data beyond GIC ITS,
> like for SMMUv3 etc..
> [*]
> https://lore.kernel.org/qemu-devel/bae6e29a-7
On 4/4/25 5:00 AM, Gustavo Romero wrote:
> Hi Phil,
>
> On 4/3/25 17:40, Philippe Mathieu-Daudé wrote:
>> Add the use case reported as issue #2886 [*]. The test
>> passes while it shouldn't. We are going to fix that in
>> the following commits.
>
> I think this organization is not ideal. I like
Mario Fleischmann writes:
> This patch series introduces support for the Multi-Core Debug (MCD) API, a
> commonly used debug interface by emulators. The MCD API, defined through a
> header file, consists of 54 functions for implementing debug and trace.
> However, since it is a header-file-only i
> 2025年4月4日 05:15，Michael S. Tsirkin 写道：
>
> On Tue, Apr 01, 2025 at 11:18:17AM -0400, Haoqian He wrote:
>> Live migration should be terminated if the vhost-user backend crashes
>> before the migration completes.
>>
>> Specifically, since the vhost device will be stopped when VM is stopped
>>
On 4/3/25 10:40 PM, Philippe Mathieu-Daudé wrote:
> Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"),
> its_class_name() single implementation doesn't return NULL
> anymore. Update the prototype docstring, and remove the
> pointless checks.
>
> Reported-by: Gustavo Romero
> Signed-o
On 3/27/25 10:51, John Levon wrote:
On Wed, Mar 26, 2025 at 08:51:18AM +0100, Cédric Le Goater wrote:
Rename some routines to better reflect the namespace they belong to.
Signed-off-by: Cédric Le Goater
---
hw/vfio/listener.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(
Fabiano Rosas writes:
+Cc Markus
context:
This series was trying to stop savevm from crashing when arbitrary
migration capabilities are enabled. Daniel brought up the previous
discussion around unifying capabilities + parameters and passing it all
via the migrate (or snapshot in this case) comma
On 4/3/25 10:40 PM, Philippe Mathieu-Daudé wrote:
> GIC ITS is checked for the MADT and IORT tables.
> Factor the checks out to the its_enabled() helper.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Gustavo Romero
> Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Eric
>
Markus Armbruster writes:
> migrate_params_test_apply() neglects to apply tls_authz. Currently
> harmless, because migrate_params_check() doesn't care. Fix it anyway.
>
> Signed-off-by: Markus Armbruster
> ---
> migration/options.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a
On 4/3/25 10:40 PM, Philippe Mathieu-Daudé wrote:
> No need to strstr() check the class name when we can
> use kvm_irqchip_in_kernel().
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Eric
> ---
> hw/arm/virt.c | 12 +++-
> 1 file
Xiaoyao Li writes:
> From: Isaku Yamahata
>
> Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
> can be provided for TDX attestation. Detailed meaning of them can be
> found:
> https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0f...@intel.com/
>
> Allow u
Hi Philippe,
On 4/3/25 10:40 PM, Philippe Mathieu-Daudé wrote:
> VirtMachineState::tcg_its has the negated logic value of
> VirtMachineClass::no_tcg_its. Directly use the latter,
> removing the former.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Eric Auger
Eric
> ---
> include/hw/ar
Stefano Garzarella 于2025年4月1日周二 18:49写道：
>
> On Wed, Mar 26, 2025 at 04:25:37PM +0800, oen...@gmail.com wrote:
> >From: Huaitong Han
> >
> >The vring call fd is set even when the guest does not use msix (e.g., in the
> >case of virtio pmd), leading to unnecessary CPU overhead for processing
> >i
On 4/2/25 14:35, Avihai Horon wrote:
On 26/03/2025 9:51, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Routines of common.c :
vfio_devices_all_dirty_tracking_started
vfio_devices_all_device_dirty_tracking
vfio_devices_query_dirty_bitmap
vfio_get_dir
To manage the private and shared RAM states in confidential VMs,
introduce a new class of PrivateShareManager as a child of
GenericStateManager, which inherits the six interface callbacks. With a
different interface type, it can be distinguished from the
RamDiscardManager object and provide the fle
On 4/2/25 15:49, Avihai Horon wrote:
On 26/03/2025 9:51, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
File "common.c" has been emptied of most of its definitions by the
previous changes and the only definitions left are related to the VFIO
MemoryListener ha
> 2025年4月4日 15:30，Stefano Garzarella 写道：
>
> On Thu, Mar 27, 2025 at 02:53:24PM +0800, Haoqian He wrote:
>>
>>> 2025年3月25日 17:51，Stefano Garzarella 写道：
>>>
>>> On Tue, Mar 25, 2025 at 04:39:46PM +0800, Haoqian He wrote:
> 2025年3月24日 22:31，Stefano Garzarella 写道：
> On Thu, Mar 20, 202
On 2/19/25 09:22, Zhenzhong Duan wrote:
Currently we have realize() callback which is called before attachment.
But there are still some elements e.g., hwpt_id is not ready before
attachment. So we need a realize_late() callback to further initialize
them.
The relation between objects HostIOMMU
On 4/7/25 4:51 PM, Zhao Liu wrote:
On Tue, Apr 01, 2025 at 11:35:49AM +0800, Ewan Hai wrote:
Date: Tue, 1 Apr 2025 11:35:49 +0800
From: Ewan Hai
Subject: Re: [PATCH v2 08/10] target/i386/kvm: reset AMD PMU registers
during VM reset
[2] As mentioned in [1], QEMU always sets the vCPU's v
Signed-off-by: Dietmar Maurer
---
meson.build | 10 ++
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 5 -
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 41f68d3806..28ca37855a 100644
--- a/meso
The period of the stimecmp timer is the time until the next S-mode
timer IRQ. The value is calculated as "stimecmp - time". [1]
It is equal to "stimecmp - mtime" since the time CSR is a read-only
shadow of the memory-mapped mtime register.
Thus, changing mtime value will update the period of stimec
Hello Kane,
+ Markus (for ebc29e1beab0 implementation)
On 4/7/25 09:33, Kane Chen wrote:
Hi Cédric/Philippe,
OTP (One-Time Programmable) memory is a type of non-volatile memory
in which each bit can be programmed only once. It is typically used
to store critical and permanent information, such
OK, I will fix it in the v2 patchset.
Jim Shu
On Fri, Apr 4, 2025 at 2:03 PM Alistair Francis wrote:
>
> On Thu, Mar 20, 2025 at 5:24 AM Jim Shu wrote:
> >
> > Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
> > also need to update S/VS-mode Timer and S/VSTIP bits in $mi
On Thu, May 25, 2023 at 10:20:11PM +, T.J. Alumbaugh wrote:
> This is the device implementation for the proposed expanded balloon feature
> described here:
>
> https://lore.kernel.org/linux-mm/20230509185419.1088297-1-yuan...@google.com/
>
> This series has a fixed number of "bins" for the wo
On 3/31/25 14:07, Avihai Horon wrote:
On 26/03/2025 9:50, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
The migration core subsystem makes use of the VFIO migration API to
collect statistics on the number of bytes transferred. These services
are declared in
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized based on four RISC-V specifications: Volume
Thanks Eric.
I have a few questions about the bitmap content shown by 'qemu-img map'.
>From below sample bitmap data:
1. Why only some of the extents have start and offset values? And why are
they the same values?
2. What does the start value indicate? Is it logical offset or physical
offset of dat
On 3/26/25 08:50, Cédric Le Goater wrote:
Hello,
Several large extensions were merged in VFIO recently: migration
support with dirty tracking, support for different host IOMMU backend
devices, multifd support, etc. This adds up to the previous
extensions: vfio-platform, AP, CCW. The result is th
Hello,
On Monday, April 07, 2025 08:47 CEST, Prasad Pandit wrote:
> * If seeking is managed internally by pread(2)/pwrite(2) and co.
> functions, then that is independent of the
> 'QIO_CHANNEL_FEATURE_SEEKABLE' flag; This flag is QEMU specific, it is
> not available outside of QEMU/io/ system. p
On 3/27/25 10:50, John Levon wrote:
On Wed, Mar 26, 2025 at 08:51:21AM +0100, Cédric Le Goater wrote:
/* Returns 0 on success, or a negative errno. */
diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c
index
4fdb74e33c427595a9b0a4d28b2b5a70df951e4e..9000702aed960ccb69ca67ec052f1ebe11ee1919
100644
---
On 3/27/25 10:54, John Levon wrote:
On Wed, Mar 26, 2025 at 08:51:20AM +0100, Cédric Le Goater wrote:
"hw/vfio/vfio-common.h" has been emptied of most of its declarations
by the previous changes and the only declarations left are related to
VFIODevice. Rename it to "hw/vfio/vfio-device.h" and m
On 4/2/25 15:55, Avihai Horon wrote:
On 26/03/2025 9:51, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Rename some routines to better reflect the namespace they belong to.
Signed-off-by: Cédric Le Goater
Reviewed-by: Avihai Horon
Since lore didn't r
On 2025/4/5 5:17 PM, Daniel Henrique Barboza wrote:
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
1 f
On 2025/4/5 5:14 PM, Daniel Henrique Barboza wrote:
On 3/29/25 11:44 AM, Max Chou wrote:
Handle the overlap of source registers with different EEWs.
The vs1 EEW of vrgatherei16.vv is 16.
Co-authored-by: Anton Blanchard
Co-authored-by: Max Chou
Since you're marked as Author you don't need
On 4/2/25 15:36, Avihai Horon wrote:
On 26/03/2025 9:51, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
vfio_container_query_dirty_bitmap() is consistent the VFIO container
routine naming scheme and is now free to use.
Signed-off-by: Cédric Le Goater
Revi
On 2025/4/5 5:09 PM, Daniel Henrique Barboza wrote:
On 3/29/25 11:44 AM, Max Chou wrote:
According to the v spec, a vector register cannot be used to provide
source
operands with more than one EEW for a single instruction.
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.in
On 3/27/25 10:39, John Levon wrote:
On Wed, Mar 26, 2025 at 08:51:16AM +0100, Cédric Le Goater wrote:
vfio_container_query_dirty_bitmap() is consistent the VFIO container
routine naming scheme and is now free to use.
"consistent with" ?
"consistent" was intended. I rephrased to :
"Rename t
On Tue, Apr 01, 2025 at 11:35:49AM +0800, Ewan Hai wrote:
> Date: Tue, 1 Apr 2025 11:35:49 +0800
> From: Ewan Hai
> Subject: Re: [PATCH v2 08/10] target/i386/kvm: reset AMD PMU registers
> during VM reset
>
> > > [2] As mentioned in [1], QEMU always sets the vCPU's vendor to match the
> > > hos
On Sat, Apr 05, 2025 at 05:04:28PM +0900, Akihiko Odaki wrote:
> The goal of commit 7987d2be5a8b ("virtio-net: Copy received header to
> buffer") was to remove the need to patch the (const) input buffer with a
> recomputed UDP checksum by copying headers to a RW region and inject the
> checksum the
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