On Tue, 11 Mar 2025 at 21:44, wrote:
> From: Marc-André Lureau
>
> Fixes: https://issues.redhat.com/browse/RHEL-81894
> Signed-off-by: Marc-André Lureau
* No commit message? Same for patch 09/10.
---
- Prasad
On 2/19/25 15:48, John Levon wrote:
From: Jagannathan Raman
Instead of requesting region information on demand with
VFIO_DEVICE_GET_REGION_INFO, maintain a cache: this will become
necessary for performance for vfio-user, where this call becomes a
message over the control socket, so is of higher
On 19/3/25 19:22, Alex Bennée wrote:
For some of the helpers we need a temporary variable to copy from
although we could add some helpers to return pointers into env in
those cases if we wanted to.
Signed-off-by: Alex Bennée
---
target/arm/gdbstub64.c | 53 ++--
On 23/3/25 18:37, Richard Henderson wrote:
Prepare for offset_io being non-zero in do_stb.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c | 1 -
hw/arm/highbank.c | 1 -
hw/arm/mps3r.c | 1 -
hw/arm/smmuv3.c | 1 -
4 files changed, 4 deletions(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index b452470598b..04439364370 100644
--- a/hw/arm/exynos42
On Wed, 2 Apr 2025, Bernhard Beschow wrote:
Am 31. März 2025 09:18:05 UTC schrieb "Daniel P. Berrangé"
:
General conceptual question . I've never understood what the dividing
line is between use of 'qemu_log_mask' and trace points.
I *think* it's the perspective: If you want to see any i
Match the prototype of cpu_memory_rw_debug().
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 2 +-
target/sparc/cpu.h| 2 +-
target/sparc/mmu_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
in
Zhenzhong,
Hi!
Eric asked me to review this series.
Since it's rather late since you posted will summarize review feedback
below/bottom.
- Don
On 2/19/25 3:22 AM, Zhenzhong Duan wrote:
Hi,
Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 translation for em
The comments for segment_size and allocation_unit_size incorrectly
described them as 4KB. According to the UFS specification,
segment_size is expressed in units of 512 bytes.
Given segment_size = 0x2000 (8192), the actual size is 4MB.
Similarly, allocation_unit_size = 1 means 1 segment = 4MB.
This
If the dont-log flag is set in the 'timer use' field for the
'set watchdog' command, a watchdog timeout will not get logged as
a timer use expiration.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/ipmi/ipmi_
On 4/4/25 15:05, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:28, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_long_bits() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/
On 18/03/2025 09:54, Cédric Le Goater wrote:
> vfio_devices_query_dirty_bitmap() is only used in "dirty-tracking.c".
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> hw/vfio/dirty-tracking.h | 3 ---
> hw/vfio/dirty-tracking.c | 2 +-
> 2 files changed, 1 insertion(+), 4
On 4/4/25 15:00, Philippe Mathieu-Daudé wrote:
+Paolo
On 4/4/25 20:25, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Hardware accelerators depends on the host, not the guest.
While this is true, no we can't unpoison those define.
They are applied per target, and not
On 4/4/25 14:56, Philippe Mathieu-Daudé wrote:
+Paolo
On 4/4/25 20:23, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Currently hvf_enabled() is restricted to target-specific code.
By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
Instead, we can simply m
On 4/4/25 14:54, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:21, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target
On 4/4/25 14:53, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:20, Pierrick Bouvier wrote:
On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
While this change is correct, this is not strictly needed.
With the current approach, using a
On Fri, 4 Apr 2025, Alexey Kardashevskiy wrote:
On Tue, 1 Apr 2025, at 01:26, BALATON Zoltan wrote:
The FDT does not normally store name properties but reconstructs it
from path but each node in Open Firmware should at least have this
property. This is correctly handled in getprop but nextprop s
Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition,
have targets set the 'has_precise_smc' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
add a static 'tcg_target_has_precise_smc' variable, initialized
just after calling TCGCPUOps:
target_has_precise_smc() returns the value of the
TARGET_HAS_PRECISE_SMC definition at runtime.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-internal.h | 3 +++
accel/tcg/cpu-exec.c| 9 +
accel/tcg/tb-maint.c| 18 +-
accel/tcg/user-exec.c | 10 +-
This series is similar to the TARGET_SUPPORTS_MTTCG replacement
to a 'mttcg_supported' field in TCGCPUOps, but doing it for
TARGET_HAS_PRECISE_SMC, adding the 'has_precise_smc' field.
Based on tcg-next tree.
Philippe Mathieu-Daudé (2):
tcg: Introduce and use target_has_precise_smc() runtime hel
Hi Richard,
On 4/4/25 00:04, Philippe Mathieu-Daudé wrote:
By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierri
On 1/4/25 10:34, Nicholas Piggin wrote:
On Tue Apr 1, 2025 at 5:51 AM AEST, Richard Henderson wrote:
On 3/31/25 10:54, Nicholas Piggin wrote:
Add an option TARGET_HAS_LAZY_ICACHE that does not invalidate TBs upon
store, but instead tracks that the icache has become incoherent, and
provides a tb
On 3/21/25 10:26, Jamin Lin wrote:
The digest_addr is set to "src_addr + 0x100", where src_addr is the DRAM
base address. However, the value 0x100 (16MB) is too large because the
AST1030 does not support DRAM, and its SRAM size is only 768KB.
A range size of 0x1000 (64KB) is sufficient f
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0]. The HMAC key buffer address is also
On Wed, Apr 02, 2025 at 02:31:01AM -0700, Pinku Deb Nath wrote:
> Full Unit Access (FUA) is an optimization where a disk write with the
> flag set will be persisted to disk immediately instead of potentially
> remaining in the disk's write cache. This commit address the todo task
> for using pwrite
The CPU_RESOLVING_TYPE definition was added in commit
0dacec874fa ("cpu: add CPU_RESOLVING_TYPE macro"), but
then added again in commit d3ae32d4d20. Remove the
duplication.
Fixes: d3ae32d4d20 ("target/hppa: Implement cpu_list")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
On 4/4/25 08:27, Daniel Henrique Barboza wrote:
Using 'max' as
default CPU is done by other QEMU archs like aarch64 so we'll be more
compatible with everyone else.
This isn't true. qemu-system-aarch64 -M virt defaults to cortex-a15 (for hysterical
raisins), which is completely and totally use
It is safe to remove TARGET_AARCH64 #ifdef'ry for code
guarded by runtime check on aa64_sve ISA feature, which
is only available for Aarch64 CPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/arch_dump.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/arm/arch_dump.c b/ta
On 3/23/25 08:41, Philippe Mathieu-Daudé wrote:
On 21/3/25 18:31, Pierrick Bouvier wrote:
Adding proper functions definition instead of macros, and eliminating
ifdefs is not really boilerplate.
In another thread Richard said for these cases we should use _Generic()
more.
I was thinking abo
It is safe to remove TARGET_AARCH64 #ifdef'ry for code
guarded by runtime check on aa64_sve ISA feature, which
is only available for Aarch64 CPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/
The Aarch64 gdbstub code is guarded by checks on ARM_FEATURE_AARCH64
and isar_feature_aa64_sve(), only enabled for Aarch64 CPUs.
Remove TARGET_AARCH64 #ifdef'ry and build gdbstub64.c once.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 2 +-
target/arm/gdbstub.c | 4
t
"tcg/mte_helper.h" header name is a bit misleading, since it
isn't restricted to TCG helpers. Rename it as "tcg/mte.h"
which is a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/{mte_helper.h => mte.h} | 0
target/arm/gdbstub64.c | 2 +-
target/arm/tcg/
Move MTE declarations out of "internals.h" to TCG "mte.h".
Include "mte.h" when necessary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 121
target/arm/tcg/mte.h | 124
target/arm/tcg/sve_ldst_internal.h |
address_with_allocation_tag() is only used in mte_helper.c,
move it there.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 5 -
target/arm/tcg/mte_helper.c | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/in
Introduce the QOM arm_cpu_is_64bit() helper, which checks
whether a vCPU parent class is TYPE_AARCH64_CPU. Use it in
arm_cpu_initfn() to remove a TARGET_AARCH64 definition use.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 27 +--
1 file changed, 17 inserti
We want to build MTE code once, but on linux-user it calls
arm_set_mte_tcf0() which is only defined for Aarch64.
Expose the declaration on 32-bit ARM by renaming
aarch64/mte_user_helper.h -> arm/mte_user_helper.h, then
add a stub in arm/mte_user_helper.c.
Signed-off-by: Philippe Mathieu-Daudé
---
Some headers are indirectly pulled in. Make their inclusion
explicit, otherwise next commit triggers:
target/arm/tcg/mte_helper.c:188:26: error: call to undeclared function
'GETPC' [-Wimplicit-function-declaration]
188 | do_stg(env, ptr, xt, GETPC(), store_tag1);
|
We'd like to reduce the use on TARGET_$arch definitions.
This series convert few to runtime checks, mostly in
MTE and gdbstub.
Philippe Mathieu-Daudé (9):
target/arm: Remove uses of TARGET_AARCH64 in arch_dump.c
target/arm: Remove use of TARGET_AARCH64 in dump.c
target/arm: Remove use of TAR
On 4/4/25 20:20, Pierrick Bouvier wrote:
On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
While this change is correct, this is not strictly needed.
With the current approach, using a set of common files per architecture,
we can re
On 4/4/25 20:28, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_long_bits() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt.c | 32
1
On 4/4/25 20:21, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target specific
"cpu.h" header.
Including cpu.h is n
+Paolo
On 4/4/25 20:25, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Hardware accelerators depends on the host, not the guest.
While this is true, no we can't unpoison those define.
They are applied per target, and not in config-host. So unpoisoining
them opens the
+Paolo
On 4/4/25 20:23, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Currently hvf_enabled() is restricted to target-specific code.
By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
Instead, we can simply make hvf_enabled present for common and target
s
vfio_get_device_info() is a low level routine. Move it with the other
helpers.
Signed-off-by: Cédric Le Goater
---
hw/vfio/helpers.h | 1 +
include/hw/vfio/vfio-common.h | 1 -
hw/vfio/common.c | 24
hw/vfio/helpers.c | 24 +
> -Original Message-
> From: Sid Manning
> Sent: Thursday, March 20, 2025 3:26 PM
> To: ltaylorsimp...@gmail.com; 'Brian Cain'
> ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) ; a...@rev.ng; a...@rev.ng; Marco
> Liebel (QUIC) ;
On Thu, 27 Mar 2025 09:04:51 +0100, Markus wrote:
> zoudongjie writes:
>
> > On Wed, Mar 26, 2025 at 10:53:20 +0100, Markus wrote:
> >> zoudongjie via writes:
> >>
> >> > From: Zhu Yangyang
> >> >
> >> > Calling qmp_block_set_io_throttle() will be blocked for a long time
> >> > when a network
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e8abf1f8b5c..dc55594a7de 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -247,6 +247,7 @@ stati
We do not set CONFIG_SEMIHOSTING in
configs/targets/xtensa*-linux-user.mak.
Do not raise SIGILL for user-only unconditionally.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/xte
In order to use TCG with multiple targets, replace the
compile time use of TCG_GUEST_DEFAULT_MO by a runtime access
to TCGCPUOps::guest_default_memory_order via CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/internal-target.h | 9 -
1 file c
On Mär 18 2025, Daniel P. Berrangé wrote:
> Whereever practical, it is preferrable to check a discrete feature
> or behaviour in a functional way, rather than matching on "is it QEMU"
Do you know a way to detect support for CLONE_VFORK that isn't too
expensive?
--
Andreas Schwab, SUSE Labs, sch
Hi,
The soft(-float) requirement means that the program being loaded has no
FPU dependency at all (i.e. it has no FPU instructions).
https://elixir.bootlin.com/linux/v6.13.6/source/arch/mips/kernel/elf.c#L34
When -msoft-float is used, the processor does not use hardware
floating-point instruction
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
From: Chao Peng
TDVF(OVMF) needs to run at private memory for TD guest. TDX cannot
support pflash device since it doesn't support read-only private memory.
Thus load TDVF(OVMF) with -bios option for TDs.
Use memory_region_init_ram_guest_memfd() to allocate the MemoryRegion
for TDVF because it ne
On 2/4/25 23:03, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 3686bbc9380..30238e9a223 10064
On Tue, Apr 01, 2025 at 08:37:19AM +1000, Nicholas Piggin wrote:
> On Mon Mar 31, 2025 at 11:13 PM AEST, Corey Minyard wrote:
> > On Mon, Mar 31, 2025 at 10:57:22PM +1000, Nicholas Piggin wrote:
> >> If the dont-log flag is set in the 'timer use' field for the
> >> 'set watchdog' command, a watchdo
On 3/19/25 00:21, Philippe Mathieu-Daudé wrote:
On 19/3/25 01:33, Pierrick Bouvier wrote:
On 3/18/25 14:32, Richard Henderson wrote:
Split icount stuff from system/cpu-timers.h.
There are 17 files which only require icount.h, 7 that only
require cpu-timers.h, and 7 that require both.
Signed-of
On Wed, 19 Mar 2025 13:14:27 +0100
Christian Schoenebeck wrote:
> On Wednesday, March 19, 2025 11:08:58 AM CET Christian Schoenebeck wrote:
> > According to 'man 2 close' errors returned by close() should only be used
> > for either diagnostic purposes or for catching data loss due to a previous
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/s390x/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 1f75629ddc2..320ace67198 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -348,
On Mon, Mar 03, 2025 at 01:02:17PM -0500, yuanminghao wrote:
> > > Global used_memslots or used_shared_memslots is updated to 0 unexpectly
> >
> > it shouldn't be 0 in practice, as it comes from number of RAM regions VM
> > has.
> > It's likely a bug somewhere else.
> >
> > Please describe a way
Hi Kun,
On 3/3/25 23:55, Kun Qin wrote:
Hi Leif & Peter,
Thanks for the comments. I will address them in a v2 patch.
Please also Cc me in your v2 :)
Regards,
Phil.
Regards,
Kun
On Mon, Mar 3, 2025 at 12:44 PM Leif Lindholm
mailto:leif.lindh...@oss.qualcomm.com>>
wrote:
Doh! Add
Fabiano Rosas writes:
> Daniel P. Berrangé writes:
>
>> On Thu, Mar 27, 2025 at 11:39:31AM -0300, Fabiano Rosas wrote:
>>> It has always been possible to enable arbitrary migration capabilities
>>> and attempt to take a snapshot of the VM with the savevm/loadvm
>>> commands as well as their QMP
On Wed, 19 Mar 2025 at 12:53, Tanish Desai wrote:
>
> The issue started after commit
> https://github.com/qemu/qemu/commit/59f4d65584bd3372070e2484876436c8d02505e4
>
> Reproduction:
> 1. In the build directory on MacOS (haven't tried on other OS), run:
>../configure --enable-rust --targ
On Wed, Mar 19, 2025 at 4:29 PM Fiona Ebner wrote:
>
> Hi,
> If necessary, our management layer downstream could disable the hpet
> timer by default and make users explicitly enable it if
> desired/required. I just wanted to ask if the issue is known and if
> there are any other suggestions? Thank
On 3/20/2025 10:26 PM, Alejandro Jimenez wrote:
Hi Sairaj Kodilkar,
On 3/20/25 1:11 AM, Arun Kodilkar, Sairaj wrote:
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see
Table 8: V,
TV, and GV Fields in Device Table Entry), speci
This reverts commit 7987d2be5a8bc3a502f89ba8cf3ac3e09f64d1ce.
The goal was to remove the need to patch the (const) input buffer
with a recomputed UDP checksum by copying headers to a RW region and
inject the checksum there. The patch computed the checksum only from the
header fields (missing the r
On 3/19/25 00:03, Philippe Mathieu-Daudé wrote:
On 18/3/25 23:02, Pierrick Bouvier wrote:
On 3/18/25 11:50, Philippe Mathieu-Daudé wrote:
On 18/3/25 05:51, Pierrick Bouvier wrote:
This will affect zregs field for aarch32.
This field is used for MVE and SVE implementations. MVE implementation
i
On 20/03/2025 11:45, Avihai Horon wrote:
>
> On 20/03/2025 13:18, Joao Martins wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On 20/03/2025 11:13, Avihai Horon wrote:
>>> On 19/03/2025 14:21, Joao Martins wrote:
External email: Use caution opening links or attachm
On 4/3/25 22:33, Farhan Ali wrote:
On 4/3/2025 11:05 AM, Alex Williamson wrote:
On Thu, 3 Apr 2025 10:33:52 -0700
Farhan Ali wrote:
On 4/3/2025 9:27 AM, Alex Williamson wrote:
On Thu, 3 Apr 2025 11:44:42 -0400
Stefan Hajnoczi wrote:
On Thu, Apr 03, 2025 at 09:47:26AM +0200, Niklas Schnell
Pull in recent TDX updates, which are not backwards compatible.
It's just to make this series runnable. It will be updated by script
scripts/update-linux-headers.sh
once TDX support is upstreamed in linux kernel
Signed-off-by: Xiaoyao Li
---
linux-headers/asm-x86/kvm.h | 69 ++
On 3/23/25 15:13, BALATON Zoltan wrote:
On Sun, 23 Mar 2025, Philippe Mathieu-Daudé wrote:
On 23/3/25 20:07, Richard Henderson wrote:
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 28fbbb8d3c1..ed79cc1a6b7 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7490
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
---
include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/translator.c| 2 +-
3 files changed, 5 inserti
On 2/4/25 16:25, Philippe Mathieu-Daudé wrote:
On 23/3/25 19:08, Richard Henderson wrote:
On 3/21/25 08:59, Philippe Mathieu-Daudé wrote:
Multi-threaded TCG only concerns system emulation.
That's not really true. User emulation simply has no option to
run in a single-threaded context.
I rea
On 3/21/25 10:26, Jamin Lin wrote:
Introduced "trace_aspeed_hace_addr", "trace_aspeed_hace_sg",
"trace_aspeed_hace_read", and "trace_aspeed_hace_write" trace events.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 8
hw/misc/trace-events | 6 ++
2 files changed, 14 insert
Hi,
We've been working with Panasonic to expand the testing of VirtIO across
a range of hypervisors and VMMs. We've tackled this with two approaches:
- simple unikernel to verify features and basic functions common
- rootfs images to exercise the whole device
The unikernel utilizes rcore-o
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentially the same as Smai
Remove all uses of 32-bit temporaries in emit.c.inc. Remove uses
in translate.c outside the large multiplexed generator functions.
tmp3_i32 is not used anymore and can go away.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 43 +++
target/i386/tcg/emit.c.inc | 8
On 3/26/2025 7:42 AM, 'Anton Johansson' wrote:
On 25/03/25, Brian Cain wrote:
On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Anton Johansson
Sent: Wednesday, March 12, 2025 2:46 PM
To: qemu-devel@nongnu.org
Cc: a...@rev.ng; ltaylorsimp...@gmail.com; br
When the IOMMU is implemented as a PCI device, its BDF is created
locally in virt.c. However, the same BDF is also required in
virt-acpi-build.c to support ACPI. Therefore, make this information part
of the global RISCVVirtState structure so that it can be accessed
outside of virt.c as well.
Signe
On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
To avoid including the huge "cpu.h" for a simple definition,
move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu-param.h| 14 ++
target/arm/cpu.h | 14 --
For change, pause, resume, complete, dismiss and finalize actions
corresponding job- and block-job commands are almost equal. The
difference is in find_block_job_locked() vs find_job_locked()
functions. What's different?
1. find_block_job_locked() do check, is found job a block-job. This OK
whe
v2:
Update documentation: add patch 01
v1 was:
[PATCH] [for-10.1] qapi/block-core: derpecate some block-job- APIs
Supersedes: <20250401155730.103718-1-vsement...@yandex-team.ru>
Vladimir Sementsov-Ogievskiy (2):
qapi: synchronize jobs and block-jobs documentation
qapi/block-core: derpecate so
Actualize documentation and synchronize it for commands which actually
call the same functions internally.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/block-core.json | 59 +---
qapi/job.json| 29 --
2 files changed, 61
Prasad Pandit writes:
> From: Prasad Pandit
>
> The various logical migration channels don't have a
> standardized way of advertising themselves and their
> connections may be seen out of order by the migration
> destination. When a new connection arrives, the incoming
> migration currently make
On 3/19/25 1:00 PM, Eric Auger wrote:
Hi,
On 3/19/25 1:23 AM, Jason Gunthorpe wrote:
On Tue, Mar 18, 2025 at 05:22:51PM -0400, Donald Dutile wrote:
I agree with Eric that 'accel' isn't needed -- this should be
ascertained from the pSMMU that a physical device is attached to.
I seem to re
On Wed, Apr 02, 2025 at 11:50:26 +0100, Daniel P. Berrangé wrote:
> CC libvirt / Jiri, for confirmation about whether the CPUID restrictions
> listed below will have any possible impact on libvirt CPUID handling...
..
> > +Feature check
> > +~
> > +
> > +QEMU checks if the final (CPU) f
> > > +// Some C users of this device embed its state struct into their own
> > > +// structs, so the size of the Rust version must not be any larger
> > > +// than the size of the C one. If this assert triggers you need to
> > > +// expand the padding_for_rust[] array in the C PL011State struct.
>
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-Id: <20250325224310.8785-3-phi...@linaro.org>
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b84c6afb327..0887c103e4f 100644
--- a/hw/block/m25p80.c
+++
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 11:28 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
Fix copy/paste error writing to the ATU_UPPER_TARGET
register, we want to update the upper 32 bits.
Cc: qemu-sta...@nongnu.org
Reported-by: Joey
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861
Fixes: d64e5eabc4c ("pci: Add support for Designware IP block")
Signed-off-by: Philippe Mat
On 3/21/25 10:26, Jamin Lin wrote:
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0]
On Wed, Mar 19, 2025 at 5:08 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 3/18/25 1:42 PM, Peter Maydell wrote:
> > On Fri, 7 Mar 2025 at 12:46, Daniel Henrique Barboza
> > wrote:
> >>
> >> Coverity found the following issue:
> >>
> >>>>> CID 1593156: Integer handling issues (OVERFLOW_B
A few functions now end with a label. The next commit will clean them
up.
Signed-off-by: Markus Armbruster
---
include/system/os-win32.h | 1 -
target/ppc/kvm_ppc.h| 3 ---
accel/tcg/cpu-exec.c| 1 -
block/gluster.c | 4
blo
The FDT does not normally store name properties but reconstructs it
from path but each node in Open Firmware should at least have this
property. This is correctly handled in getprop but nextprop should
also return it even if not present as a property. This patch fixes
that and also skips phandle wh
Accept "... lorem ipsum ..." in addition to "...".
Signed-off-by: Markus Armbruster
---
docs/devel/qapi-code-gen.rst| 6 --
docs/sphinx/qmp_lexer.py| 2 +-
tests/qapi-schema/doc-good.json | 2 +-
tests/qapi-schema/doc-good.out | 2 +-
tests/qapi-schema/doc-good.txt | 2 +-
5 f
Adding Cindy and Eugenio
On Thu, Mar 20, 2025 at 12:34 AM Konstantin Shkolnyy wrote:
>
> I’m observing a problem while testing VDPA with Nvidia ConnectX-6 (mlx5)
> on s390.
>
> Upon start, virtio_net_device_realize() tries to set a new MAC address
> by VHOST_VDPA_SET_CONFIG which doesn’t do anyth
Overview
=
Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU.
Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving boot, and the second/crashkernel is booted fresh
like a normal system reset, instead of the crashed kernel
Keep MTTCG initialization code out of tcg_init_machine().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-all.c | 50 +
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/
This hides the MemoryListener implementation and makes the code common
to both IOMMU backends, legacy and IOMMUFD.
Signed-off-by: Cédric Le Goater
---
hw/vfio/dirty-tracking.h | 4 ++--
hw/vfio/container.c | 11 +++
hw/vfio/dirty-tracking.c | 21 -
hw/vfio/iommu
Move all VFIODevice related routines of helpers.c into a new "device.c"
file.
Signed-off-by: Cédric Le Goater
---
hw/vfio/device.c | 331 +++
hw/vfio/helpers.c| 303 ---
hw/vfio/meson.build | 1 +
hw/vfio/trac
On Tue, 18 Mar 2025 at 13:00, Aleksandar Rakic
wrote:
> The soft(-float) requirement means that the program being loaded has no
> FPU dependency at all (i.e. it has no FPU instructions).
> https://elixir.bootlin.com/linux/v6.13.6/source/arch/mips/kernel/elf.c#L34
Yes, I know. But the kernel loade
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