Re: [PATCH v5] [for-10.1] virtio: add VIRTQUEUE_ERROR QAPI event

Vladimir Sementsov-Ogievskiy writes: > For now we only log the vhost device error, when virtqueue is actually > stopped. Let's add a QAPI event, which makes possible: > > - collect statistics of such errors > - make immediate actions: take core dumps or do some other debugging > - inform the u

[PATCH-for-10.1 v2 39/43] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h'

qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/core/cpu.h | 9 - include/system/tc

Re: [PATCH] [for-10.1] qapi/block-core: derpecate some block-job- APIs

Vladimir Sementsov-Ogievskiy writes: > For change, pause, resume, complete, dismiss and finalize actions > corresponding job- and block-job commands are almost equal. The > difference is in find_block_job_locked() vs find_job_locked() > functions. What's different? > > 1. find_block_job_locked()

Re: [PATCH 0/1 v2] [RISC-V/RVV] use a single function to probe memory.

On Thu, Mar 13, 2025 at 10:40 PM Paolo Savini wrote: > > Previous version: > > - v1: > https://lore.kernel.org/all/20250221162036.61521-1-paolo.sav...@embecosm.com/ > > Add reviewer information and rebase on top of riscv-to-apply.next branch. > > Cc: Richard Handerson > Cc: Palmer Dabbelt > Cc:

Re: [PATCH 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

On Thu, Mar 20, 2025 at 5:24 AM Jim Shu wrote: > > Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we > also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. > > Signed-off-by: Jim Shu > --- > target/riscv/csr.c | 44 > tar

Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default

On Fri, Mar 28, 2025 at 2:16 AM Philippe Mathieu-Daudé wrote: > > On 27/3/25 14:02, Daniel Henrique Barboza wrote: > > Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and > > made it default for qemu-system-riscv32/64. It was the first RISC-V > > machine added in QEMU so settin

Re: [PATCH-for-10.0 v3 2/5] tests/functional: Add a decorator for skipping tests on particular OS

On 03/04/2025 22.32, Philippe Mathieu-Daudé wrote: Since tests might be failing on some operating systems, introduce the skipIfOperatingSystem() decorator. Acked-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- tests/functional/qemu_test/__init

[RFC PATCH-for-10.1 33/39] hw/core/machine: Allow dynamic registration of valid CPU types

Add MachineClass::valid_cpu_types_list, a dynamic list of strings. CPU types can be registered with machine_class_add_valid_cpu_type(). Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 8 hw/core/machine.c | 28 +

Re: [PATCH 3/3] hw/riscv/riscv_iommu: Remove the "bus" property

On Sun, Mar 2, 2025 at 7:13 PM Jason Chien wrote: > > This property was originally intended to set the bus number for non-root > endpoints. However, since the PCIe bus number is assigned and modified > at runtime, setting this property before software execution is incorrect. > Additionally, the pr

Re: [PATCH v2 2/4] docs, qapi: generate undocumented return sections

On Tue, Apr 1, 2025 at 2:07 AM Markus Armbruster wrote: > John Snow writes: > > > On Thu, Mar 27, 2025 at 5:11 AM Markus Armbruster > wrote: > > > >> John Snow writes: > >> > >> > This patch changes the qapidoc transmogrifier to generate Return value > >> > documentation for any command that h

[PATCH 3/6] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 242dee3731..85eabc9876 100755 --- a/target/hexagon/hex_common.py +++ b/target/

[PATCH 0/6] misc hexagon patches

While preparing the system emulation patches, these ones stuck out as not-strictly-related to sysemu. We can review and apply them independently of those. Brian Cain (6): target/hexagon: handle .new values target/hexagon: Fix badva reference, delete CAUSE target/hexagon: Add missing A_CALL

[PATCH-for-10.0 v3 0/5] hw/arm: Tests fixes for 10.0

Hi, I tried to gather all the hw/arm/-related patches for the GitLab issues tagged for 10.0: - trivial ones fixing / disabling broken tests - disable the VMapple machine (not sure about it) Regards, Phil. Since v2: - Reword skipIfOperatingSystem() decorator - Dropped ACPI patches Philippe Mat

[RFC PATCH-for-10.1 04/19] qemu: Convert target_words_bigendian() to TargetInfo API

Signed-off-by: Philippe Mathieu-Daudé --- include/exec/tswap.h| 13 + include/qemu/target_info-impl.h | 4 include/qemu/target_info.h | 11 +++ cpu-target.c| 6 -- hw/core/cpu-system.c| 2 +- hw/display/vga.c

[RFC PATCH-for-10.1 16/39] hw/arm: Remove unnecessary 'cpu.h' header

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/exynos4210.c | 1 - hw/arm/highbank.c | 1 - hw/arm/mps3r.c | 1 - hw/arm/smmuv3.c | 1 - 4 files changed, 4 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index b452470598b..044393643

Re: [PATCH 3/4] target/riscv: Fix VSTIP bit in sstc extension.

On Thu, Mar 20, 2025 at 5:24 AM Jim Shu wrote: > > VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will > revert it's defined behavior as if sstc extension is not implemented. > > Signed-off-by: Jim Shu Acked-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 9 +++

Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target

On Sat, Mar 22, 2025 at 1:09 AM Philippe Mathieu-Daudé wrote: > > Hi, > > On 6/1/22 22:00, Frédéric Pétrot wrote: > > This series of patches provides partial 128-bit support for the riscv > > target architecture, namely RVI and RVM, with minimal csr support. > > > > Frédéric Pétrot (18): > >ex

Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation

On Thu, Apr 3, 2025 at 12:41 AM Philippe Mathieu-Daudé wrote: > > On 2/4/25 16:25, Philippe Mathieu-Daudé wrote: > > On 23/3/25 19:08, Richard Henderson wrote: > >> On 3/21/25 08:59, Philippe Mathieu-Daudé wrote: > >>> Multi-threaded TCG only concerns system emulation. > >> > >> That's not really

[PATCH 0/2] fix deadlock with plugins reset/uninstall

We first fix the issue reported in [1]. We then add a test plugin making sure we don't regress in the future. [1] https://gitlab.com/qemu-project/qemu/-/issues/2901 Pierrick Bouvier (2): plugins/loader: fix deadlock when resetting/uninstalling a plugin tests/tcg/plugins: add plugin to test re

[PATCH 2/2] tests/tcg/plugins: add plugin to test reset and uninstall

We perform a plugin reset, uninstall, and make sure we went through those steps. Signed-off-by: Pierrick Bouvier --- tests/tcg/plugins/reset.c | 73 +++ tests/tcg/plugins/meson.build | 2 +- 2 files changed, 74 insertions(+), 1 deletion(-) create mode 100644

[PATCH 1/2] plugins/loader: fix deadlock when resetting/uninstalling a plugin

Reported and fixed by Dmitry Kurakin. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2901 Signed-off-by: Pierrick Bouvier --- plugins/loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugins/loader.c b/plugins/loader.c index 7523d554f03..0d6e082e170 100644 --- a

[PATCH-for-10.1 v3 06/19] exec: Restrict 'cpu_ldst.h' to accel/tcg/

Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- bsd-user/qemu.h | 2 +- include/{exec/

Re: [PATCH 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension

On Thu, Mar 20, 2025 at 5:24 AM Jim Shu wrote: > > When changing the mtime value, the period of [s|vs]timecmp timers > should also be updated like the period of mtimecmp timer. Why should they be updated? Alistair > > Signed-off-by: Jim Shu > --- > hw/intc/riscv_aclint.c | 5 + > 1 file c

Re: [PATCH-for-10.1 v3 7/9] hw/arm/virt-acpi: Always build IORT table (even with GIC ITS disabled)

Hi Phil, On 4/3/25 17:40, Philippe Mathieu-Daudé wrote: Citing Gustavo [*]: Gating IORT table generation entirely based on the presence of ITS looks wrong because IORT table has data beyond GIC ITS, like for SMMUv3 etc.. [*] https://lore.kernel.org/qemu-devel/bae6e29a-7290-47d2-8caf-

Re: [RFC PATCH] Hexagon (target/hexagon) analyze all reads before writes

On 3/24/2025 9:14 PM, Taylor Simpson wrote: I noticed that analyze_packet is marking the implicit pred reads after marking all the writes. However, the semantics of the instrucion and packet are to do all the reads, then do the operation, then do all the writes. Here is the old code static vo

Re: [PATCH 1/4] target/riscv: Add the checking into stimecmp write function.

On Thu, Mar 20, 2025 at 5:22 AM Jim Shu wrote: > > Preparation commit to let aclint timer to use stimecmp write function. > Aclint timer doesn't call sstc() predicate so we need to check inside > the stimecmp write function. > > Signed-off-by: Jim Shu Acked-by: Alistair Francis Alistair > ---

Re: [PATCH-for-10.1 v3 9/9] qtest/bios-tables-test: Update aarch64/virt 'its_off' variant blobs

Hi Phil, On 4/3/25 17:40, Philippe Mathieu-Daudé wrote: Commit the blobs generated by tests/data/acpi/rebuild-expected-aml.sh. In accordance with my comments in 5/9 and 6/9 about the blobs organization, after the fix, I think only APIC blob should be updated and removed from the "ignore list".

Re: [PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

On Fri, Mar 14, 2025 at 1:24 AM Paolo Savini wrote: > > Previous versions: > > - RFC v1: > https://lore.kernel.org/all/20241218170840.1090473-1-paolo.sav...@embecosm.com/ > - RFC v2: > https://lore.kernel.org/all/20241220153834.16302-1-paolo.sav...@embecosm.com/ > - RFC v3: > https://lore.kerne

Re: [PATCH v2 0/2] target/hexagon: Fix macOS build

On 4/2/2025 6:42 AM, Anton Johansson wrote: A default macOS build with xcode cli tools installed lacks the `indent` program needed by the idef-parser postprocess step. If `indent` is installed through homebrew it doesn't support the `-linux` flag. Conditionally run `indent` only on linux hosts.

Re: [PATCH-for-10.1 v3 5/9] qtest/bios-tables-test: Add test for -M virt,its=off

Hi Phil, On 4/3/25 17:40, Philippe Mathieu-Daudé wrote: Add the use case reported as issue #2886 [*]. The test passes while it shouldn't. We are going to fix that in the following commits. I think this organization is not ideal. I like better your first version, i.e., adding the correct blobs

Re: [PATCH v2] ppc/vof: Make nextprop behave more like Open Firmware

On Tue, 1 Apr 2025, at 01:26, BALATON Zoltan wrote: > The FDT does not normally store name properties but reconstructs it > from path but each node in Open Firmware should at least have this > property. This is correctly handled in getprop but nextprop should > also return it even if not present

Re: [PATCH-for-10.1 v3 3/9] hw/arm/virt: Simplify create_its()

Hi Phil, On 4/3/25 17:40, Philippe Mathieu-Daudé wrote: No need to strstr() check the class name when we can use kvm_irqchip_in_kernel(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/virt.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-

[PATCH 1/6] target/hexagon: handle .new values

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/hex_common.py | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 758e5fd12d..242dee3731 100755 --- a/target/hexagon/hex_c

[PATCH 5/6] target/hexagon: Remove unreachable

From: Brian Cain We should raise an exception in the event that we encounter a packet that can't be correctly decoded, not fault. Signed-off-by: Brian Cain --- target/hexagon/decode.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/hexagon/decode.c b/target/hexa

[PATCH 2/6] target/hexagon: Fix badva reference, delete CAUSE

From: Brian Cain The BADVA reg is referred to with the wrong identifier. The CAUSE reg field of SSR is not yet modeled. Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 76

[PATCH 6/6] target/hexagon: Add memory order definition

From: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/cpu-param.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 45ee7b4640..ccaf6a9d28 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23

[PATCH 4/6] target/hexagon: s/pkt_has_store/pkt_has_scalar_store

From: Brian Cain To remove any confusion with HVX or other potential store instructions, we'll qualify this context var with "scalar". Signed-off-by: Brian Cain --- target/hexagon/idef-parser/README.rst | 2 +- target/hexagon/insn.h | 4 ++-- target/hexagon/macros.h

Re: [PATCH v3 6/6] hw/riscv: microchip_pfsoc: Rework documentation

On Wed, Mar 19, 2025 at 4:14 PM Sebastian Huber wrote: > > Mention that running the HSS no longer works. Document the changed boot > options. Reorder documentation blocks. Update URLs. > > Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis Alistair > --- > docs/system/riscv/micr

Re: [PATCH v3 0/6] Improve Microchip Polarfire SoC customization

On Wed, Mar 19, 2025 at 4:13 PM Sebastian Huber wrote: > > Booting the microchip-icicle-kit machine using the latest PolarFire SoC > Hart Software Services (HSS) no longer works since Qemu lacks support > for several registers (clocks, DRAM controller). Also reading from the > SDCard does not work

[PULL 1/6] tcg: Allocate TEMP_VAL_MEM frame in temp_load()

From: Philippe Mathieu-Daudé Be sure to allocate the temp frame if it wasn't. In the resolved issues, incomplete dead code elimination left a load at the top of an unreachable loop. We simply need to allocate the stack slot to avoid crashing. Fixes: c896fe29d6c ("TCG code generator") Reported-

[RFC PATCH-for-10.1 12/39] target/arm/cpu-features: Include missing 'cpu.h' header

"target/arm/cpu-features.h" dereferences the ARMISARegisters structure, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: In file included from target/arm/internals.h:33: target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters'

[RFC PATCH-for-10.1 24/39] hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature()

Using arm_cpu_has_feature() instead of arm_feature() remove a dependency on (the indirectly included) "cpu.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/virt-acpi-build.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/vir

[RFC PATCH-for-10.1 07/39] hw/arm/raspi: Filter machine types for binary

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 4 hw/arm/raspi.c | 9 + hw/arm/raspi4b.c | 1 + 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 95e16806fa1..7dd81e8e0f9 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm

[RFC PATCH-for-10.1 04/39] hw/arm: Filter machine types for binary

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 1 + hw/arm/collie.c | 1 + hw/arm/exynos4_boards.c | 1 + hw/arm/fby35.c| 1 + hw/arm/highbank.c | 2 ++ hw/arm/microbit.c | 1 + hw/arm/mps2-tz.c | 4 hw/arm/mps2.c

Re: [PATCH 14/15] fuse: Implement multi-threading

On Wed, Apr 02, 2025 at 09:20:33AM -0400, Stefan Hajnoczi wrote: > > > Eric: Are you interested in implementing support for multiple IOThreads > > > in the NBD export? I remember some time ago we talked about NBD > > > multi-conn support, although maybe that was for the client rather than > > > the

Re: [PATCH v3 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

On Wed, Mar 19, 2025 at 4:13 PM Sebastian Huber wrote: > > This property enables the setting of the CLINT timebase frequency > through the command line, for example: > > -machine microchip-icicle-kit,clint-timebase-frequency=1000 > > Signed-off-by: Sebastian Huber > Reviewed-by: Philippe Ma

Re: [PATCH v3 4/6] hw/riscv: Allow direct start of kernel for MPFS

On Wed, Mar 19, 2025 at 4:13 PM Sebastian Huber wrote: > > Further customize the -bios and -kernel options behaviour for the > microchip-icicle-kit machine. If "-bios none -kernel filename" is > specified, then do not load a firmware and instead only load and start > the kernel image. > > For tes

Re: [PATCH v3 3/6] hw/riscv: Make FDT optional for MPFS

On Wed, Mar 19, 2025 at 4:13 PM Sebastian Huber wrote: > > Real-time kernels such as RTEMS or Zephyr may use a static device tree > built into the kernel image. Do not require to use the -dtb option if > -kernel is used for the microchip-icicle-kit machine. Issue a warning > if no device tree is

Re: [PATCH v3 1/6] hw/misc: Add MPFS system reset support

On Wed, Mar 19, 2025 at 4:13 PM Sebastian Huber wrote: > > Signed-off-by: Sebastian Huber Acked-by: Alistair Francis Alistair > --- > hw/misc/mchp_pfsoc_sysreg.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c > index

Re: [PATCH 0/1 v2] [RISCV/RVV] Generate strided vector loads/stores with tcg nodes.

On Thu, Mar 13, 2025 at 1:57 AM Paolo Savini wrote: > > Previous version: > > - PATCH v1: > https://lore.kernel.org/all/20250211182056.412867-1-paolo.sav...@embecosm.com/ > > Follwing the suggestion in the following review by Daniel Barboza: > > https://lore.kernel.org/all/9be2ecc4-fed3-4774-a921

[PULL 2/6] tests/functional/test_aarch64_rme_virt: fix sporadic failure

From: Pierrick Bouvier This test was randomly failing on our CI, and on dev machines, especially with QEMU debug builds. >From the information collected, it's related to an implementation choice in edk2 QEMU virt support. The workaround is to disable KASLR, to avoid accessing protected memory. N

Re: [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG

On 4/1/25 01:09, Philippe Mathieu-Daudé wrote: mmu_index() is specific to TCG SoftMMU, moveCPUClass::mmu_index() toTCGCPUOps::mmu_index(). Philippe Mathieu-Daudé (24): hw/core/cpu: UpdateCPUClass::mmu_index docstring accel/tcg: IntroduceTCGCPUOps::mmu_index() callback target/alpha: Rest

[PATCH-for-10.0 v3 4/5] tests/qtest: Skip Aarch64 VMapple machine

First, the VMapple machine only works with the ARM 'host' CPU type, which isn't accepted for QTest: $ qemu-system-aarch64 -M vmapple -accel qtest qemu-system-aarch64: The 'host' CPU type can only be used with KVM or HVF Second, the QTest framework expects machines to be createable without spe

Re: [PATCH v2 5/5] target/riscv: pmp: remove redundant check in pmp_is_locked

On Fri, Mar 14, 2025 at 5:35 AM Loïc Lefort wrote: > > Remove useless check in pmp_is_locked, the function will return 0 in either > case. > > Signed-off-by: Loïc Lefort > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmp.c | 5 - > 1 f

Re: [PATCH v2 0/5] target/riscv: Smepmp fixes to match specification

On Fri, Mar 14, 2025 at 5:33 AM Loïc Lefort wrote: > > These patches fix Smepmp implementation to make it compliant with the spec. > > First patch limits RLB to CSR changes since RLB should not affect privilege > evaluation. Patch 2 extracts some common code into a function (to be used in > patch

[PULL 5/6] tests/qtest: Skip Aarch64 VMapple machine

From: Philippe Mathieu-Daudé First, the VMapple machine only works with the ARM 'host' CPU type, which isn't accepted for QTest: $ qemu-system-aarch64 -M vmapple -accel qtest qemu-system-aarch64: The 'host' CPU type can only be used with KVM or HVF Second, the QTest framework expects machin

[PULL 0/6] tcg patch queue for 10.0-rc3

The following changes since commit 0adf626718bc0ca9c46550249a76047f8e45da15: Update version for v10.0.0-rc2 release (2025-04-01 13:15:45 -0400) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250403 for you to fetch changes up to

[RFC PATCH-for-10.1 13/19] accel: Replace CPU_RESOLVING_TYPE -> target_cpu_type()

Signed-off-by: Philippe Mathieu-Daudé --- accel/accel-target.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/accel/accel-target.c b/accel/accel-target.c index 33a539b4cbb..9e9e70be876 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -25,6 +25,7 @@ #in

[PULL 3/6] tests/functional: Add a decorator for skipping tests on particular OS

From: Philippe Mathieu-Daudé Since tests might be failing on some operating systems, introduce the skipIfOperatingSystem() decorator. Acked-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-ID: <20250403203241

[PULL 4/6] tests/functional: Skip aarch64_replay test on macOS

From: Philippe Mathieu-Daudé As of v10.0.0-rc2 this test is still failing on macos: $ make check-functional-aarch64 V=1 ... ERROR:../../replay/replay-internal.c:235:replay_mutex_unlock: assertion failed: (replay_mutex_locked()) Bail out! ERROR:../../replay/replay-internal.c:235:replay_m

[PULL 6/6] hw/arm: Do not build VMapple machine by default

From: Philippe Mathieu-Daudé Unfortunately as of v10.0.0-rc2 the VMapple machine is unusable: $ qemu-system-aarch64 -M vmapple [...] *** Terminating app due to uncaught exception 'NSInvalidArgumentException', reason: '-[PGIOSurfaceHostDeviceDescriptor setMapMemory:]: unrecognized sele

Re: [PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed

On Fri, Mar 14, 2025 at 5:33 AM Loïc Lefort wrote: > > Signed-off-by: Loïc Lefort > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmp.c | 22 +++--- > 1 file changed, 15 insertions(+), 7 deletions(-) > > diff --git a/target/

Re: [PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function

On Fri, Mar 14, 2025 at 5:33 AM Loïc Lefort wrote: > > Signed-off-by: Loïc Lefort > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmp.c | 22 -- > 1 file changed, 12 insertions(+), 10 deletions(-) > > diff --git a/target

Re: [PATCH v2 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges

On Fri, Mar 14, 2025 at 5:32 AM Loïc Lefort wrote: > > When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs > but should not affect interpretation of actual PMP rules. > > This is not the case with the current implementation where pmp_hart_has_privs > calls pmp_is_locked

[PATCH] hw/ipmi: Allow multiple BMC instances

Allow a system to have multiple BMC connections to the same BMC and multiple different BMCs. This can happen on real systems, and is useful for testing the IPMI driver on Linux. Signed-off-by: Corey Minyard --- I'm working on a fairly extensive test suite for IPMI, the Linux driver and qemu, and

Re: [PATCH v6 41/60] hw/i386: add option to forcibly report edge trigger in acpi tables

Sent from my iPhone

[RFC PATCH-for-10.1 35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()

Replace the target-specific TARGET_AARCH64 definition by a call to the generic target_long_bits() helper. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c i

Re: [PATCH-for-10.0 1/5] qtest/bios-tables-test: Add test for -M virt,its=off

Hi Phil, On 4/3/25 09:47, Philippe Mathieu-Daudé wrote: On 3/4/25 08:25, Gustavo Romero wrote: Hi Phil, On 4/2/25 07:30, Philippe Mathieu-Daudé wrote: On 2/4/25 08:41, Gustavo Romero wrote: Hi Phil, On 3/31/25 19:12, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé Pl

[RFC PATCH-for-10.1 29/39] hw/arm: Build sbsa-ref.c once

Since previous commit allowed the use of accelerator definitions in common code, we can now move sbsa-ref.c to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build

[RFC PATCH-for-10.1 26/39] system/hvf: Avoid including 'cpu.h'

"system/hvf.h" doesn't need to include a full "cpu.h", only "exec/vaddr.h" and "qemu/queue.h" are required. Signed-off-by: Philippe Mathieu-Daudé --- include/system/hvf.h | 3 ++- include/system/hvf_int.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/system/hv

[RFC PATCH-for-10.1 39/39] hw/arm/meson: Remove arm_ss[] source set

All units are now built as common objects. Signed-off-by: Philippe Mathieu-Daudé --- Yay! --- hw/arm/meson.build | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 61f145f901f..476e6048939 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@

Re: [PATCH 1/2] accel/tcg: add get_virtual_clock for TCG

On 4/3/25 04:38, Alex Bennée wrote: Rather than allowing cpus_get_virtual_clock() to fall through to cpu_get_clock() introduce a TCG handler so it can make a decision about what time it is. Initially this just calls cpu_get_clock() as before but this will change in later commits. Signed-off-by:

[RFC PATCH-for-10.1 07/19] target/hppa: Replace TARGET_LONG_BITS -> target_long_bits()

Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/mem_helper.c | 3 ++- target/hppa/translate.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 554d7bf4d14..03cd103f284 100644 --- a/target/hppa/mem_helper.c +++

[RFC PATCH-for-10.1 02/19] qemu: Convert target_name() to TargetInfo API

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 -- include/qemu/target_info-impl.h | 3 +++ include/qemu/target_info.h | 2 ++ cpu-target.c| 5 - hw/core/machine-qmp-cmds.c | 1 + plugins/loader.c| 2 +- system/vl.c

[RFC PATCH-for-10.1 25/39] hw/arm: Build virt-acpi-build.c once

Previous commits removed the target-specificities, we can now move virt-acpi-build.c to arm_common_ss[]. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f52034ff6a2..536

[RFC PATCH-for-10.1 15/19] accel: Include missing 'qemu/accel.h' header in accel-internal.h

In file included from ../../accel/accel-target.c:29: ../../accel/accel-internal.h:13:32: error: unknown type name 'AccelClass' 13 | void accel_init_ops_interfaces(AccelClass *ac); |^ Signed-off-by: Philippe Mathieu-Daudé --- accel/accel-internal.h | 2 ++

[RFC PATCH-for-10.1 14/19] accel: Implement accel_init_ops_interfaces() for both system/user mode

Signed-off-by: Philippe Mathieu-Daudé --- accel/{accel-system.h => accel-internal.h} | 8 accel/accel-system.c | 4 ++-- accel/accel-target.c | 10 ++ accel/accel-user.c | 6 ++ 4 files changed, 14 inserti

[RFC PATCH-for-10.1 38/39] hw/arm: Move xen files to arm_common_ss[]

Signed-off-by: Philippe Mathieu-Daudé --- XXX untested --- hw/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index c46e5036722..61f145f901f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -63,7 +63,7 @@ arm_c

[RFC PATCH-for-10.1 36/39] target/arm: Expose Aarch64 helpers indistinctly

At worst, for 32-bit arm binary, using these methods will now produce a link time error, instead of a compile time one. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 8657

[RFC PATCH-for-10.1 30/39] target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo

Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 01408e40a34..d6ac00be0f2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -25,6 +25,7

[RFC PATCH-for-10.1 37/39] hw/arm: Build virt.c once

Previous commits removed the TARGET_AARCH64 uses in virt.c, we can now move it to arm_common_ss[] and build it once. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 7eb4

[RFC PATCH-for-10.1 32/39] target/arm: Replace target_ulong -> vaddr for CPUWatchpoint

CPUWatchpoint::vaddr/len are of type vaddr. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 9 + target/arm/hyp_gdbstub.c | 8 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ce60aee41d8..8

[RFC PATCH-for-10.1 27/39] system/hvf: Expose hvf_enabled() to common code

Currently hvf_enabled() is restricted to target-specific code. By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + include/system/hvf.h| 14 +- accel/stubs/hvf-stub.c | 12 accel/stu

[RFC PATCH-for-10.1 19/19] system/vl: Filter machine list for binary using machine_binary_filter()

Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 24 1 file changed, 24 insertions(+) diff --git a/system/vl.c b/system/vl.c index d8a0fe713c9..554f5f2a467 100644 --- a/system/vl.c +++ b/system/vl.c @@ -27,6 +27,8 @@ #include "qemu/datadir.h" #include "qemu/unit

[RFC PATCH-for-10.1 31/39] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint

CPUARMState::pc is of type uint64_t. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 6 +++--- target/arm/hyp_gdbstub.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d6ac00be0f2..ce60aee41d8 1

[RFC PATCH-for-10.1 34/39] hw/arm/virt: Register valid CPU types dynamically

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index fe2dec9500f..e241e71e1c3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3129,32 +3129,30 @@ sta

[RFC PATCH-for-10.1 23/39] hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature()

By using arm_cpu_has_feature() instead of arm_feature() we don't need to include "cpu.h" anymore. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/realview.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/r

[RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

Extract PSCI definitions (which are not target specific) to the new "target/arm/psci.h", so code from hw/arm/ can use them without having to include the target specific "cpu.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/arm/boot.h | 3 ++- t

[RFC PATCH-for-10.1 22/39] target/arm: Add arm_cpu_has_feature() helper

arm_cpu_has_feature() is equivalent of arm_feature(), however while the latter uses CPUARMState so is target-specific, the former doesn't and can be called by target-agnostic code in hw/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/cpu_has_feature.h | 2 ++

[RFC PATCH-for-10.1 19/39] hw/arm: Include missing 'target/arm/gtimer.h' header

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/arm/aspeed_ast27x0.c| 1 + hw/arm/bcm2838.c | 1 + hw/arm/exynos4210.c| 1 + hw/arm/fsl-imx8mp.c| 1 + hw/arm/mps3r.c | 1 + hw/arm/npcm8xx.c | 1 + hw/vmapple/vmapple.c

[RFC PATCH-for-10.1 21/39] target/arm: Extract feature definitions to 'cpu_has_feature.h' header

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 54 +- target/arm/cpu_has_feature.h | 65 2 files changed, 66 insertions(+), 53 deletions(-) create mode 100644 target/arm/cpu_

[RFC PATCH-for-10.1 17/39] target/arm: Restrict inclusion of 'multiprocessing.h'

Only cpu.c requires "multiprocessing.h" definitions so far. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 1 - target/arm/cpu.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3705b34285b.

[RFC PATCH-for-10.1 18/39] target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h'

arm_build_mp_affinity() and affinity mask definitionss are related to multiprocessing. Move them to "multiprocessing.h", including this header when necessary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- target/arm/cpu.h | 17 - target/arm/

[RFC PATCH-for-10.1 13/39] target/arm/qmp: Include missing 'cpu.h' header

arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier 'ARM_MAX_VQ' 83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); | ^ Signed-off-

[RFC PATCH-for-10.1 14/39] target/arm/kvm: Include missing 'cpu-qom.h' header

ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU' 54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level); | ^ Signed-off-by: Philipp

[RFC PATCH-for-10.1 15/39] target/arm/hvf: Include missing 'cpu-qom.h' header

ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU' 23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); | ^ Signed-of

[RFC PATCH-for-10.1 08/39] hw/arm/raspi: Build objects once

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/meson.build | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index f76e7fb229f..f52034ff6a2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,8 +27,12 @@ arm_common_ss

[RFC PATCH-for-10.1 06/39] hw/arm/aspeed: Build objects once

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 09b1cfe5b57..f76e7fb229f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,15 +39,15 @@ arm_common_ss.ad

[RFC PATCH-for-10.1 10/39] hw/arm/boot: Include missing 'system/memory.h' header

default_reset_secondary() uses address_space_stl_notdirty(), itself declared in "system/memory.h". Include this header in order to avoid when refactoring headers: ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-

[RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS. Use the full path to "cpu.h": "target/arm/cpu.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/digic.h | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +-

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