On 26/03/2025 07.47, Thomas Huth wrote:
On 25/03/2025 23.42, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/audio/wm8750.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/audio/wm8750.c b/hw/audio/wm8750.c
index 8d381dbc658..6c1bb20fb75 100644
--- a/hw/au
On 25/03/2025 23.43, Philippe Mathieu-Daudé wrote:
A 'zpci' device encapsulate a PCI device to be usable
by System/Z. Categorize it as bridge.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/s390x/s390-pci-bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/s390x/s390-p
On 3/26/2025 11:36 AM, Xiaoyao Li wrote:
On 3/26/2025 2:46 AM, Daniel P. Berrangé wrote:
On Fri, Jan 24, 2025 at 08:20:48AM -0500, Xiaoyao Li wrote:
Add docs/system/i386/tdx.rst for TDX support, and add tdx in
confidential-guest-support.rst
Signed-off-by: Xiaoyao Li
---
---
docs/system/c
To address the limitation that this option is incompatible with
remote clients, this patch series adds an option to select a
preferred codec and also enable gl=on option for clients that
are connected via the network. In other words, with this option
enabled (and the below linked Spice series merge
On 25/03/2025 23.42, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/audio/wm8750.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/audio/wm8750.c b/hw/audio/wm8750.c
index 8d381dbc658..6c1bb20fb75 100644
--- a/hw/audio/wm8750.c
+++ b/hw/audio/wm8750.c
@@ -
Hi
On Wed, Mar 26, 2025 at 5:46 AM Qiang Yu wrote:
>
> On Mon, Mar 24, 2025 at 10:02 PM Marc-André Lureau
> wrote:
> >
> > On Mon, Mar 24, 2025 at 5:35 PM Qiang Yu wrote:
> > >
> > > On Mon, Mar 24, 2025 at 5:30 PM Marc-André Lureau
> > > wrote:
> > > >
> > > > Hi
> > > >
> > > > On Mon, Mar 2
John Snow writes:
> On Tue, Mar 25, 2025 at 3:53 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Update the python tests to also check qapi. No idea why I didn't do this
>> > before. I guess I was counting on moving it under python/ and then just
>> > forgot after that was NACKed. Oo
Hi bibo mao:
On 2025/3/26 上午10:51, lixianglai wrote:
Hi bibo mao:
Xianglai,
Thanks for your patch, some comments inline.
On 2025/3/19 下午4:32, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel,
the initrd is loaded in the ram. If the initrd size is too larg
On 2025/3/26 上午10:51, lixianglai wrote:
Hi bibo mao:
Xianglai,
Thanks for your patch, some comments inline.
On 2025/3/19 下午4:32, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel,
the initrd is loaded in the ram. If the initrd size is too large,
the loadin
John Snow writes:
> A few transitive dependencies were left floating; as a result, pip's
> dependency solver can pull in newer dependencies, which we don't
> want. Pin them down.
>
> Signed-off-by: John Snow
What problem exactly does this fix? Make target check-minreqs?
> ---
> python/tests/
John Snow writes:
> On Tue, Mar 25, 2025 at 3:36 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > This restores the linting baseline in qapidoc. The order of some imports
>> > have changed slightly due to configuring isort a little better: isort
>>
>> Changed since when / what?
>>
>
>
Hi Dmitry,
> Subject: Re: [PATCH v2 4/6] ui/console-gl: Add a helper to create a texture
> with linear memory layout
>
> On 3/26/25 02:39, Vivek Kasireddy wrote:
> > +void surface_gl_create_texture_from_fd(DisplaySurface *surface,
> > + int fd, GLuint *textur
Hanna Czenczek writes:
> When exports are created on the command line (with the storage daemon),
> errp is going to point to error_fatal. Without ERRP_GUARD, we would
> exit immediately when *errp is set, i.e. skip the clean-up code under
> the `fail` label. Use ERRP_GUARD so we always run that
Hanna Czenczek writes:
> FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs
> (via open("/dev/fuse") + ioctl(FUSE_DEV_IOC_CLONE)).
>
> We can use this to implement multi-threading.
>
> Note that the interface presented here differs from the multi-queue
> interface of virtio-b
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h | 3 ---
include/exec/exec-all.h | 1 +
include/exec/tlb-flags.h| 1 +
linux-user/sparc/target_syscall.h | 2
From: Thomas Huth
This test was using cloudinit and a "dnf install" command in the guest
to exercise the NIC with SMMU enabled. Since we don't have the cloudinit
stuff in the functional framework and we should not rely on having access
to external networks (once our ASSETs have been cached), we r
On Wed, Mar 26, 2025 at 1:50 AM Philippe Mathieu-Daudé
wrote:
>
> Replace the few ldtul_p() calls by a generic ldn_p() ones.
> No logical change.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/gdbstub.c | 8 +---
> 1 file changed, 5
On 3/26/2025 2:46 AM, Daniel P. Berrangé wrote:
On Fri, Jan 24, 2025 at 08:20:48AM -0500, Xiaoyao Li wrote:
Add docs/system/i386/tdx.rst for TDX support, and add tdx in
confidential-guest-support.rst
Signed-off-by: Xiaoyao Li
---
---
docs/system/confidential-guest-support.rst | 1 +
do
Thanks for the feedback!
You're right — I missed initializing csr_priv.
In this case, we only want to check for privilege M-mode CSRs along with
the smaia condition.
I’ll fix it by adding:
"int csr_priv = get_field(csrno, 0x300);"
Jay
On Wed, Mar 19, 2025 at 8:59 PM Daniel Henrique Barboza <
db
Hi bibo mao:
Xianglai,
Thanks for your patch, some comments inline.
On 2025/3/19 下午4:32, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel,
the initrd is loaded in the ram. If the initrd size is too large,
the loading fails, resulting in a VM startup failure.
On 3/26/25 02:39, Vivek Kasireddy wrote:
> +void surface_gl_create_texture_from_fd(DisplaySurface *surface,
> + int fd, GLuint *texture)
> +{
> +unsigned long size = surface_stride(surface) * surface_height(surface);
> +GLuint mem_obj;
> +
> +if (!e
From: Peter Maydell
Currently every board that uses the PL011 duplicates the logic that
selects the Rust implementation if Rust was enabled and the C
implementation if it does not. Factor this out into a separate
Kconfig stanza, so that boards can go back to simply doing "select
PL011" and get w
On 3/18/25 18:28, Richard Henderson wrote:
On 3/18/25 17:15, Pierrick Bouvier wrote:
@@ -329,7 +331,39 @@ static bool translator_ld(CPUArchState *env,
DisasContextBase *db,
host = db->host_addr[1];
}
- memcpy(dest, host + (pc - base), len);
+ do_read:
+ /*
+ * Assume
On Mon, Mar 24, 2025 at 10:02 PM Marc-André Lureau
wrote:
>
> On Mon, Mar 24, 2025 at 5:35 PM Qiang Yu wrote:
> >
> > On Mon, Mar 24, 2025 at 5:30 PM Marc-André Lureau
> > wrote:
> > >
> > > Hi
> > >
> > > On Mon, Mar 24, 2025 at 12:20 PM wrote:
> > > >
> > > > From: Qiang Yu
> > > >
> > > > S
On Tue, Mar 25, 2025 at 5:41 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This patch changes the qapidoc transmogrifier to generate Return value
> > documentation for any command that has a return value but hasn't
> > explicitly documented that return value.
> >
> > Signed-off-by: John
If i/o does not cover the entire first page, allocate a portion
of ram as an i/o device, so that the entire first page is i/o.
While memory_region_init_ram_device_ptr is happy to allocate
the RAMBlock, it does not register the ram for migration.
Do this by hand.
Signed-off-by: Richard Henderson
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-sta...@nongnu.org
Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling
From: Chao Liu
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1, write all elements
to 1.
After troubleshooting, it was found that
On 3/24/25 21:36, Michael Tokarev wrote:
23.03.2025 20:45, Cédric Le Goater wrote:
Jamin Lin (1):
hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
Steven Lee (1):
hw/intc/aspeed: Fix IRQ handler mask check
Troy Lee (1):
aspeed: Fix maximum number of spi con
On 25/3/25 21:00, Thomas Huth wrote:
From: Thomas Huth
Now that all Avocado tests have been converted to or been replaced by
other functional tests, we can delete the remainders of the Avocado
tests from the QEMU source tree.
Signed-off-by: Thomas Huth
---
MAINTAINERS
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/loongarch/cpu.h | 1 +
target/m68k/cpu.h | 1 +
target/microb
On 3/25/25 06:48, Richard Henderson wrote:
On 3/24/25 18:07, Pierrick Bouvier wrote:
A simple nit, maybe we could define constant for register names. This way, it
can be used
in the two switch for read/access.
Which constant?
- The absolute address (0x58-0x5f)
- The i/o port address
On 3/25/25 16:03, Philippe Mathieu-Daudé wrote:
On 25/3/25 23:43, Richard Henderson wrote:
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 1006
In cases where the scanout buffer is provided as a texture (e.g. Virgl)
we need to check to see if it has a linear memory layout or not. If
it doesn't have a linear layout, then blitting it onto the texture
associated with the display surface (which already has a linear layout)
seems to ensure that
There are cases where we do not want the memory layout of a texture to
be tiled as the component processing the texture would not know how to
de-tile either via software or hardware. Therefore, ensuring that the
memory backing the texture has a linear layout is absolutely necessary
in these situati
Giving users an option to choose a particular codec will enable
them to make an appropriate decision based on their hardware and
use-case.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Dmitry Osipenko
Cc: Frediano Ziglio
Cc: Dongwon Kim
Signed-off-by: Vivek Kasireddy
---
qemu-options.hx | 5
In the specific case where the display layer (virtio-gpu) is using
dmabuf, and if remote clients are enabled (-spice gl=on,port=),
it makes sense to limit the maximum (streaming) rate to 60 FPS
using the GUI timer. This matches the behavior of GTK UI where the
display updates are submitted at 6
Newer versions of Spice server should be able to accept dmabuf
fds from Qemu for clients that are connected via the network.
In other words, when this option is enabled, Qemu would share
a dmabuf fd with Spice which would encode and send the data
associated with the fd to a client that could be loc
Since most encoders/decoders (invoked by Spice) may not work with
tiled memory associated with a texture, we need to create another
texture that has linear memory layout and use that instead.
Note that, there does not seem to be a direct way to indicate to the
GL implementation that a texture's ba
On 3/25/25 16:13, Philippe Mathieu-Daudé wrote:
On 25/3/25 23:43, Richard Henderson wrote:
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembl
On Tue, 25 Mar 2025, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rtc/ds1338.c | 2 ++
hw/rtc/m41t80.c | 2 ++
hw/rtc/rs5c372.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c
index 8dd17fdc07c..56162917c1b 100644
--- a/hw/rtc
On 25/3/25 23:43, Richard Henderson wrote:
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-sta...@nongnu.org
Fixes: 9d8caa67a2
On 25/3/25 23:43, Richard Henderson wrote:
Do not unconditionally attempt to read 4 bytes, as there
may only be 2 bytes remaining in the translator cache.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/disas.c | 21 ++-
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf6b..ab7412772bc 100644
--- a/target/arm/cpu.h
On 25/3/25 23:43, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 10 ++
target/avr/helper.c | 36 ++--
2 files changed, 28 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 25/3/25 23:43, Richard Henderson wrote:
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
Do not unconditionally attempt to read 4 bytes, as there
may only be 2 bytes remaining in the translator cache.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/disas.c | 21 ++---
1 file changed, 14 insertions(+), 7 deleti
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 10 ++
target/avr/helper.c | 36 ++--
2 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index b49e7a7056..ebcdda20ac 100644
--- a/target/avr/cpu.h
On Tue, Mar 25, 2025 at 11:43:04PM +0100, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i2c/i2c_mux_pca954x.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Looks ok to me.
Acked-by: Corey Minyard
>
> diff --git a/hw/i2c/i2c_mux_pca954x.c b/
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into
the cpu registers with normal address space accesses.
We no longer need to trap accesses to the first page within
avr_cpu_tlb_fill but can wait until a write occurs.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 7 ++
tar
This device is part of SoC components thus can not
be created manually.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/xlnx-efuse.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index 29e7dd539ec..176e88fcd17 100644
--- a/hw/nvram/xlnx-ef
Few devices are user-creatable but miss a description,
and sometimes are not categorized (or mis-categorized).
Some, being qdev and not sysbus, are automatically
user-creatable, but are part of SoC.
Fix that.
Philippe Mathieu-Daudé (12):
hw/audio/wm8750: Categorize and add description
hw/blo
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
first release candidate for the QEMU 10.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-10.0.0-rc0.tar.xz
http://download.qem
Signed-off-by: Philippe Mathieu-Daudé
---
hw/dma/i82374.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c
index 9652d47adcd..0bf69ef399b 100644
--- a/hw/dma/i82374.c
+++ b/hw/dma/i82374.c
@@ -150,6 +150,8 @@ static void i82374_class_init(ObjectClass *klass,
Avoid direct use of address_space_memory.
Make use of the softmmu cache of the i/o page.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -44,8 +44,6 @@
/* Number of CPU registers
For single-binary, we would really like to have a common TARGET_PAGE_BITS_MIN.
AVR's use of TARGET_PAGE_BITS == 8 is unfortunately too small. This was due
to having mmio in the first 256 or 512 bytes and RAM starting immediately
afterward -- the softmmu page table mapping really doesn't like mixe
Match the prototype of cpu_memory_rw_debug().
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 2 +-
target/sparc/cpu.h| 2 +-
target/sparc/mmu_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletio
A 'zpci' device encapsulate a PCI device to be usable
by System/Z. Categorize it as bridge.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/s390x/s390-pci-bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
index 2591ee49c11..d
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b84c6afb327..0887c103e4f 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -1870,7 +1870,9 @@ static void m25p80_class_init(ObjectC
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i2c/i2c_mux_pca954x.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c
index 779cc4e66ed..100b8d86093 100644
--- a/hw/i2c/i2c_mux_pca954x.c
+++ b/hw/i2c/i2c_mux_pca954x.c
@@
All these devices are part of SoC components and can not
be created manually.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/bcm2835_cprman.c | 8
hw/misc/npcm_clk.c | 6 ++
hw/misc/stm32l4x5_rcc.c | 4
3 files changed, 18 insertions(+)
diff --git a/hw/misc/bcm2835_c
Now that we can handle the MCU allocating only a portion of the
first page to i/o, increase the page size. Choose 10 as larger
than the i/o on every MCU, just so that this path is tested.
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h | 8 +---
1 file changed, 1 insertion(+), 7
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rtc/ds1338.c | 2 ++
hw/rtc/m41t80.c | 2 ++
hw/rtc/rs5c372.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c
index 8dd17fdc07c..56162917c1b 100644
--- a/hw/rtc/ds1338.c
+++ b/hw/rtc/ds1338.c
@@ -230,6 +230,8
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sensor/dps310.c | 2 ++
hw/sensor/emc141x.c | 6 ++
hw/sensor/tmp105.c | 2 ++
hw/sensor/tmp421.c | 4
4 files changed, 14 insertions(+)
diff --git a/hw/sensor/dps310.c b/hw/sensor/dps310.c
index 6966a53248b..e1e6df6b60a 100644
--- a/hw/se
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/axp2xx.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/misc/axp2xx.c b/hw/misc/axp2xx.c
index af646878cd2..747af430479 100644
--- a/hw/misc/axp2xx.c
+++ b/hw/misc/axp2xx.c
@@ -232,6 +232,7 @@ static void axp2xx_class_init(ObjectClass
This define isn't really used.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 2 --
target/avr/helper.c | 3 +--
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index
Signed-off-by: Philippe Mathieu-Daudé
---
hw/gpio/pca9552.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/gpio/pca9552.c b/hw/gpio/pca9552.c
index 1ac0cf6c464..b152872f6c6 100644
--- a/hw/gpio/pca9552.c
+++ b/hw/gpio/pca9552.c
@@ -459,6 +459,8 @@ static void pca9552_class_init(ObjectCl
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 7d6954ec26..f23fa3e8ba 100644
--- a/target/
Signed-off-by: Philippe Mathieu-Daudé
---
hw/audio/wm8750.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/audio/wm8750.c b/hw/audio/wm8750.c
index 8d381dbc658..6c1bb20fb75 100644
--- a/hw/audio/wm8750.c
+++ b/hw/audio/wm8750.c
@@ -721,6 +721,8 @@ static void wm8750_class_init(ObjectCla
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/dm163.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
index 75a91f62bd3..f6f0ec0c632 100644
--- a/hw/display/dm163.c
+++ b/hw/display/dm163.c
@@ -330,7 +330,7 @@ static void dm163_cl
Quoting Michael Roth (2025-03-19 07:08:40)
> Hello,
>
> On behalf of the QEMU Team, I'd like to announce the availability of the
> first release candidate for the QEMU 10.0 release. This release is meant
> for testing purposes and should not be used in a production environment.
>
> http://downl
mips_cpu_is_64bit() returns whether the CPU is a
32-bit or a 64-bit one.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu-qom.h | 2 ++
target/mips/cpu.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 9acf647420c..52996
From: Suraj Shirvankar
Signed-off-by: Suraj Shirvankar
---
util/fdmon-io_uring.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/util/fdmon-io_uring.c b/util/fdmon-io_uring.c
index b0d68bdc44..235837abcb 100644
--- a/util/fdmon-io_uring.c
+++ b/util/fdmon-io_uring.c
@
Suggestion by Stefan Hajnoczi to improve io_uring performance
Suraj Shirvankar (1):
Add IOURING_SETUP_SINGLE_ISSUER flag to improve iouring performance
util/fdmon-io_uring.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
--
2.45.3
From: Thomas Huth
These tests are using the gdb-related library functions from the
Avocado framework which we don't have in the functional framework
yet. So for the time being, keep those imports and skip the test
if the Avocado framework is not installed on the host.
Signed-off-by: Thomas Huth
From: Thomas Huth
Reuse the test function from the big endian test to easily
convert the 32-bit little endian Wheezy mips test.
Signed-off-by: Thomas Huth
---
tests/avocado/linux_ssh_mips_malta.py | 8
tests/functional/meson.build | 1 +
tests/functional/test_mipsel_malta.p
From: Thomas Huth
The test checks some entries in /proc and the output of some commands ...
we put these checks into exportable functions now so that they can
be reused more easily.
Additionally the linux_ssh_mips_malta.py uses SSH to test the networking
of the guest. Since we don't have a SSH m
From: Thomas Huth
Now that all Avocado tests have been converted to or been replaced by
other functional tests, we can delete the remainders of the Avocado
tests from the QEMU source tree.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 8 +-
docs/about/build-platfor
From: Thomas Huth
All tests that used this class have been converted to the functional
framework, so we can remove the boot_linux_console.py file now.
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linux_console.py | 62 -
1 file changed, 62 deletions(-)
delete
From: Thomas Huth
test_x86_64_pc in tests/avocado/boot_linux_console.py only checks
whether the kernel parameters have correctly been passed to the
kernel in the guest by looking for them in the console output of the
guest. Let's move that to the functional test framework now, but
instead of doin
From: Thomas Huth
We are going to move the remaining Avocado tests step by step
into the functional test framework. Unfortunately, Avocado fails
with an error if it cannot determine a test to run, so disable
the tests here now to avoid failures in the Gitlab-CI during the
next steps.
Signed-off-
On 25/03/25 22:50, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
Implement Pnv11Chip, currently without chiptod, xive and phb.
Chiptod, XIVE, PHB are implemented in later patches.
Since Power11 core is same as Power10, the implementation of Pnv11Chip
is a duplicate of correspo
From: Thomas Huth
This way we can do a full boot in record-replay mode and
should get a similar test coverage compared to the old
replay test from tests/avocado/replay_linux.py. Thus remove
the x86 avocado replay_linux test now.
Signed-off-by: Thomas Huth
---
tests/avocado/replay_linux.py
From: Thomas Huth
This way we can do a full boot in record-replay mode and
should get a similar test coverage compared to the old
replay test from tests/avocado/replay_linux.py.
Since the aarch64 test was the last avocado test in the
tests/avocado/replay_linux.py file, we can remove this
file no
From: Thomas Huth
Since this was the last test in tests/avocado/replay_kernel.py,
we can remove that Avocado file now.
Signed-off-by: Thomas Huth
-#
-# This work is licensed under the terms of the GNU GPL, version 2 or
-# later. See the COPYING file in the top-level directory.
-
-import os
-im
From: Thomas Huth
Reuse the test function from the 32-bit big endian test to easily
convert the 64-bit little endian Wheezy mips test.
Signed-off-by: Thomas Huth
---
tests/avocado/linux_ssh_mips_malta.py | 8
tests/functional/meson.build| 1 +
tests/functional/test_mip
From: Thomas Huth
Reuse the test function from the 32-bit big endian test to easily
convert the 64-bit big endian Wheezy mips test.
Since this was the last test in tests/avocado/linux_ssh_mips_malta.py,
we can remove this avocado file now, too.
Signed-off-by: Thomas Huth
---
MAINTAINERS
From: Thomas Huth
These tests are based on the cloudinit functions from Avocado.
The cloudinit is very, very slow compared to our other tests,
so most of these Avocado tests have either been disabled by default
with a decorator, or have been marked to only run with KVM.
We won't include this slu
These patches convert the remaining Avocado tests bit by bit to the
functional framework, or replace them with a test that has similar
test coverage. This way we are finally able to get rid of the
test/avocado folder in the end, everything is then integrated with
the meson test runner. It should be
On 3/25/25 12:23, Aditya Gupta wrote:
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On Tue, Mar 25, 2025 at 07:08:29PM +0100, Eric Auger wrote:
> > +static int
> > +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev,
> > +uint32_t data_type, uint32_t data_len,
> > +void *data)
> > +{
> > +SMM
Hi Shameer, Nicolin,
On 3/25/25 7:26 PM, Nicolin Chen wrote:
> On Tue, Mar 25, 2025 at 03:43:29PM +, Shameerali Kolothum Thodi wrote:
>>> For the record I tested the series with host VFIO device and a
>>> virtio-blk-pci device put behind the same pxb-pcie/smmu protection and
>>> it works just
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> When nested translation is enabled, there are 2-stage translation
> occuring to two different address spaces: stage-1 in the iommu as,
> while stage-2 in the system as.
>
> If a device attached to the vSMMU doesn't enable stag
On Fri, Jan 24, 2025 at 08:20:48AM -0500, Xiaoyao Li wrote:
> Add docs/system/i386/tdx.rst for TDX support, and add tdx in
> confidential-guest-support.rst
>
> Signed-off-by: Xiaoyao Li
> ---
> ---
> docs/system/confidential-guest-support.rst | 1 +
> docs/system/i386/tdx.rst
On 3/25/25 08:49, Philippe Mathieu-Daudé wrote:
Replace the few ldtul_p() calls by a generic ldn_p() ones.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/gdbstub.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 3/25/25 08:45, Philippe Mathieu-Daudé wrote:
When TARGET_LONG_BITS == 64, ldtul_p() expand to ldq_p().
Directly use the expanded form for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richar
On Tue, Mar 25, 2025 at 03:43:29PM +, Shameerali Kolothum Thodi wrote:
> > For the record I tested the series with host VFIO device and a
> > virtio-blk-pci device put behind the same pxb-pcie/smmu protection and
> > it works just fine
> >
> > -+-[:0a]-+-01.0-[0b]00.0 Mellanox Technol
Hi,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Allocate and associate a vDEVICE object for the Guest device
> with the vIOMMU. This will help the kernel to do the
> vSID --> sid translation whenever required (eg: device specific
s/sid/SID
> invalidations).
>
> Signed-off
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