Based-on: <20250104-reuse-v18-0-c349eafd8...@daynix.com>
("[PATCH v18 00/14] hw/pci: SR-IOV related fixes and improvements")
Introduction
This series is based on the RFC series submitted by Yui Washizu[1].
See also [2] for the context.
This series enables SR-IOV emulation for virtio
On 14/03/2025 03.34, Nicholas Piggin wrote:
On Thu Mar 13, 2025 at 8:49 PM AEST, Philippe Mathieu-Daudé wrote:
On 13/3/25 07:13, Thomas Huth wrote:
On 13/03/2025 03.34, Stefan Hajnoczi wrote:
On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin
wrote:
The following changes since commit
825b96dbc
Signed-off-by: Akihiko Odaki
---
docs/system/sriov.rst | 3 ++-
include/hw/pci/pcie_sriov.h | 7 +--
hw/pci/pcie_sriov.c | 8 +++-
hw/virtio/virtio-pci.c | 16 ++--
4 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/docs/system/sriov.rst b/d
A device cannot be a SR-IOV PF and a VF at the same time.
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
index 1eb4358256de..109b2ebcccba 100644
--- a/hw/pci/pcie_sriov.c
+++ b/hw/pci/pcie_sr
Allow user to attach SR-IOV VF to a virtio-pci PF.
Signed-off-by: Akihiko Odaki
---
include/hw/virtio/virtio-pci.h | 1 +
hw/virtio/virtio-pci.c | 20 +++-
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/
A user can create a SR-IOV device by specifying the PF with the
sriov-pf property of the VFs. The VFs must be added before the PF.
A user-creatable VF must have PCIDeviceClass::sriov_vf_user_creatable
set. Such a VF cannot refer to the PF because it is created before the
PF.
A PF that user-creata
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
docs/system/index.rst | 1 +
docs/system/sriov.rst | 36
3 files changed, 38 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0e5db7a57449..4cde71687645 100644
--- a/MAINTAINERS
+++ b/M
A virtio-net device can be added as a SR-IOV VF to another virtio-pci
device that will be the PF.
Signed-off-by: Akihiko Odaki
---
hw/virtio/virtio-net-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/virtio/virtio-net-pci.c b/hw/virtio/virtio-net-pci.c
index e18953ad674b..430b727ea3
A SR-IOV VF cannot have a ROM BAR.
Co-developed-by: Yui Washizu
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 2844ec55560f..8460b6105338 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2522,6 +2522,14
RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to
communicate IOMMU information to the OS. Add support for creating this
table when the IOMMU is present. The specification is frozen and
available at [1].
[1] -
https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/download/v0.9
RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to
communicate IOMMU and topology information to the OS. Add support for
creating this table when the IOMMU is present. The specification is
frozen and available at [1].
[1] -
https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/
When the IOMMU is implemented as a PCI device, its BDF is created
locally in virt.c. However, the same BDF is also required in
virt-acpi-build.c to support ACPI. Therefore, make this information part
of the global RISCVVirtState structure so that it can be accessed
outside of virt.c as well.
Signe
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Add testcases for testing fadump with PSeries and PSeries+KVM
combinations
It tests if fadump is successfully detected and registered in the first
kernel boot. Then crashes the kernel, and verifies whether we have a
/proc/vmcore in the 2nd boot
Also introduce 'wait_for_regex_console_pattern' to c
Clang on LoongArch only accepts fp register names in the dollar-prefixed
form, while GCC allows omitting the dollar. Change registers in ASM
clobbers to the dollar-prefixed form to make user emulators buildable
with Clang on loongarch64. No functional change invovled.
Signed-off-by: Yao Zi
---
h
On 3/13/25 11:26, Philippe Mathieu-Daudé wrote:
On 13/3/25 19:05, Richard Henderson wrote:
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_m
On Thu Mar 13, 2025 at 8:49 PM AEST, Philippe Mathieu-Daudé wrote:
> On 13/3/25 07:13, Thomas Huth wrote:
>> On 13/03/2025 03.34, Stefan Hajnoczi wrote:
>>> On Tue, Mar 11, 2025 at 8:59 PM Nicholas Piggin
>>> wrote:
The following changes since commit
825b96dbcee23d134b691fc75618b5
On 2025/3/13 下午6:32, Markus Armbruster wrote:
Bibo Mao writes:
There is NULL pointer checking function error_propagate() already,
it is not necessary to add checking for function parameter. Here remove
NULL pointer checking with function parameter.
Signed-off-by: Bibo Mao
---
hw/loongar
On 3/13/25 02:58, Philippe Mathieu-Daudé wrote:
On 13/3/25 04:44, Richard Henderson wrote:
Split out mmap_lock, et al from page-protection.h
to a new header.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h | 1 +
include/exec/mmap-lock.h | 33 +
On 3/13/25 10:21, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc)
{
- uint64_t raw, tgt;
+ uint64_t val;
- if (translator_ld(env, db, &raw, pc, sizeof(raw))) {
- tgt = tswap64(raw);
On 3/13/25 10:14, Pierrick Bouvier wrote:
+#ifdef CONFIG_ATOMIC64
+ case 8:
+ if (QEMU_IS_ALIGNED(pc, 8)) {
+ uint64_t t = qatomic_read__nocheck((uint64_t *)host);
+ stl_he_p(dest, t);
Should it be stq_he_p?
Good eyes, thanks.
This would have only appeared as d
On 3/13/25 09:22, Alex Bennée wrote:
Richard Henderson writes:
These expand inline to the *_mmuidx_ra api with
a lookup of the target's cpu_mmu_index().
Signed-off-by: Richard Henderson
This is where my re-based bisect broke. Fixed by moving cpu.h
modified target/ppc/tcg-excp_helper.c
@
On 3/12/25 20:45, Richard Henderson wrote:
Some of the headers used require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
system/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/system/meson.build b/system/meson.build
index c83d80fa24..2aab3e97f4 1
When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs
but should not affect interpretation of actual PMP rules.
This is not the case with the current implementation where pmp_hart_has_privs
calls pmp_is_locked which implements mseccfg.RLB bypass.
This commit implements th
Richard Henderson writes:
> CONFIG_USER_ONLY == !CONFIG_SYSTEM_ONLY.
> Therefore it's cleaner to just add to user_ss.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On 11/03/25 10:48, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
When MPIPL is used, OPAL/Linux registers memory regions to be preserved
on a Memory-Preserving boot ('crashkernel boot').
The regions are added to two tables: MDST and MDDT (source and
destination tables)
The
On 3/13/25 11:17, Richard Henderson wrote:
On 3/13/25 10:33, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of t
Hello Stefan, Thomas,
Thanks for reporting this. I'll try to spend some time to figure out the
issue and perhaps propose a new image for this test, if needed.
Regards,
Niek
On Thu, Mar 13, 2025 at 8:39 AM Stefan Hajnoczi wrote:
> On Thu, Mar 13, 2025 at 1:48 PM Thomas Huth wrote:
> >
> > On 1
On 3/13/25 9:26 AM, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Wednesday, March 12, 2025 6:31 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; n
On 3/13/25 10:11, Pierrick Bouvier wrote:
-uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
- int mmu_idx, uintptr_t ra);
Not related to the change, but the naming _ra is very confusing, since it means the
opposite of what it seems. *NO* requirement al
On 3/12/25 20:44, Richard Henderson wrote:
While some of these files are built exactly once, due
to being in only libuser_ss or libsystem_ss, some of
the includes that they depend on require CONFIG_USER_ONLY.
So make use of the common infrastructure to allow that.
Signed-off-by: Richard Henderso
On 3/12/25 20:45, Richard Henderson wrote:
While setup_post and has_memory will not be used for
CONFIG_USER_ONLY, let the struct have constant layout.
Signed-off-by: Richard Henderson
---
include/qemu/accel.h | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/incl
These patches fix Smepmp implementation to make it compliant with the spec.
First patch limits RLB to CSR changes since RLB should not affect privilege
evaluation. Patch 2 extracts some common code into a function (to be used in
patch 3). Patch 3 fixes validation of pmpcfg CSR writes in order to m
On 3/12/25 20:45, Richard Henderson wrote:
While RISCVCPUConfig.satp_mode is unused for user-only,
this header is used from disas/riscv.h, whose users are
only built once. The savings of 4 bytes isn't worth it.
Signed-off-by: Richard Henderson
---
target/riscv/cpu_cfg.h | 2 --
1 file chang
On 3/12/25 20:45, Richard Henderson wrote:
Many of the headers used by these require CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
hw/core/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/core/meson.build b/hw/core/meson.build
index b5a545a0ed..
On 3/12/25 20:45, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/system/ram_addr.h | 2 +-
include/{exec => system}/ramblock.h | 9 -
hw/display/virtio-gpu-udmabuf.c | 2 +-
hw/hyperv/hv-balloon.c
Implement the register command of "ibm,configure-kernel-dump" RTAS call.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
We also store the passed fadump memory structure, which will later be
used for preser
On 3/12/25 20:45, Richard Henderson wrote:
This is include/system, so CONFIG_USER_ONLY will never be true.
Some build configurations have this symbol missing.
https://github.com/pbo-linaro/qemu-ci/actions/runs/13826820446
Signed-off-by: Richard Henderson
---
include/system/cpu-timers.h |
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/hw/s390x/css.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/s390x/css.h b/include/hw/s39
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them. The inlines
for user-only are unused.
Signed-off-by: Richard Henderson
---
include/hw/intc/armv7m_nvic.h | 14 --
1 file changed, 14 deleti
On 3/12/25 20:45, Richard Henderson wrote:
We were hiding a number of declarations from user-only,
although it hurts nothing to allow them.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/exec/cpu-common.h b/incl
On 3/12/25 20:45, Richard Henderson wrote:
The implementation of cpu_mmu_index was split between
cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY.
Unify within a new header and include only where needed.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 6 --
On 3/12/25 20:45, Richard Henderson wrote:
Uninline the user-only stubs from hw/core/cpu.h.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 23 ---
common-user/watchpoint-stub.c | 28
common-user/meson.build | 1 +
On 3/12/25 20:45, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
include/{exec => system}/ram_addr.h | 7 +++
accel/kvm/kvm-all.c | 2 +-
accel/tcg/cputlb.c | 2 +-
accel/tcg/translate-all.c
On 3/12/25 20:45, Richard Henderson wrote:
Semihosting is not enabled for user-only.
Avoid the test for that case.
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/xtensa/translate.c b/targ
On 3/12/25 20:45, Richard Henderson wrote:
Semihosting is not enabled for user-only.
Avoid the test for that case.
Signed-off-by: Richard Henderson
---
target/mips/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b207106d
On 3/12/25 20:45, Richard Henderson wrote:
Poison CONFIG_USER_ONLY and CONFIG_SOFTMMU unless
the compilation unit is in specific_ss, libuser_ss,
or libsystem_ss. This is intended to prevent files
being incorrectly added to common_ss.
Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks.
All
On 11/03/25 11:11, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Linux expect a "ibm,opal/dump" node to know whether MPIPL (aka fadump)
is supported on the hardware.
Export the "ibm,opal/dump" node in QEMU's device tree for Linux to know
that PowerNV supports MPIPL.
With t
On 3/13/25 11:05, Richard Henderson wrote:
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
For my person
On 3/13/25 10:48, Philippe Mathieu-Daudé wrote:
On 13/3/25 17:36, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered th
On Thu, Mar 13, 2025 at 06:13:24PM +0530, Prasad Pandit wrote:
> +int qemu_savevm_state_postcopy_prepare(QEMUFile *f)
> +{
> +int ret = 0;
> +SaveStateEntry *se;
> +
> +QTAILQ_FOREACH(se, &savevm_state.handlers, entry) {
> +if (strcmp(se->idstr, "ram")) {
> +continue
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c5f6cdaccb..845915e0c8 100644
--- a/target/riscv/pmp.c
+++ b/target/ris
Remove useless check in pmp_is_locked, the function will return 0 in either
case.
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 845915e0c8..c685f7f2c5 1
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
This leaves cases 3, 7, 9, 11, 13, 15 for
Signed-off-by: Loïc Lefort
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/pmp.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e1e5ca589e..7d65dc24a5 100644
--- a/target/riscv/pmp.c
+++ b/target/ri
Platform (ie. QEMU) is expected to pass few device tree properties for
details for fadump:
* "ibm,configure-kernel-dump-sizes": Space required to store dump data
for firmware provided dump sections (ie. CPU & HPTE regions)
* "ibm,configure-kernel-dump-version": Versions of fadump supported
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structure registered through the
ibm,configure-kernel-dump call, the platform must process each
registere
While the first kernel boots, it registers memory regions for fadump
such as:
* CPU state data (has to be populated by the platform)
* HPTE state data (has to be populated by the platform)
* Real Mode Regions (platform should copy it to requested
destination addresses)
* OS d
Overview
=
Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU.
Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving boot, and the second/crashkernel is booted fresh
like a normal system reset, instead of the crashed kernel
Add skeleton for handle "ibm,configure-kernel-dump" rtas call in QEMU.
Verify basic details mandated by the PAPR, such as number of
inputs/output, and add handling for the three fadump commands:
regiser/unregister/invalidate.
Currently fadump register will always return HARDWARE ERROR, since it's
On 11/03/25 10:53, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Add offsets for the processor state captured during MPIPL dump.
This is incomplete. And might be implemented in future if the effort to
implement MPIPL is resumed again.
Please use RFC prefix in next iterati
Use vaddr only for the newest api, because it has the least
number of uses and therefore is the easiest to audit.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 16 ++---
include/exec/cpu_ldst.h | 48 ++---
accel/tcg/cputlb.c
On 11/03/25 10:41, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Add the MDST, MDDT, MDRT tables offsets and structures as per current
skiboot upstream:
commit bc7b85db1e7e ("opal-ci: Remove centos7")
These structures will be later populated when preserving memory reg
On 3/13/25 11:47, ltaylorsimp...@gmail.com wrote:
What we are trying to model is an instance of a Hexagon that has a number of
threads and some resources that are shared. The shared resources include the
TLB and global S registers. The initial thought was to tie the shared
resources to the t
On Thu, Mar 13, 2025 at 2:30 PM Markus Armbruster wrote:
> John Snow writes:
>
> > On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster >
> >> > wrote:
> >> >
> >> >> John Snow writes:
> >> >>
> >>
Saanjh Sengupta writes:
> Hi,
>
> What we are trying to achieve is that the QEMU should run for a particular
> number of instructions, let's say for example
> 1 instructions and then pause it's emulation. After a resume trigger is
> received to the QEMU it must resume it's
> emulation and s
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, March 12, 2025 6:40 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; quic_mathb...@quicinc.com;
> a...@rev.ng; a...@rev.ng; quic_mlie...@quicinc.com;
> ltaylorsimp...@gmail.com; alex.be
On 11/03/25 10:20, Harsh Prateek Bora wrote:
<...snip...>
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -82,6 +82,8 @@
#define SBE_CONTROL_REG_S0 PPC_BIT(14)
#define SBE_CONTROL_REG_S1 PPC_BIT(15)
+static uint64_t mpipl_skiboot_base = 0x3000 /*default
S
On 11/03/25 10:15, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
<...snip...>
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
index 62c94a04a2df..a6bf13650f2d 100644
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -21,6 +21,8 @@
#include "qapi/error.h"
#include "qemu/
Hi Harsh,
Thank you for the reviews.
On 11/03/25 10:08, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger
MPIPL.
Currently QEMU treats it as "Unimplemented", handle the interrupts by
just logging that th
On Thu, 13 Mar 2025 at 07:16, Akihiko Odaki wrote:
>
> PMCNTENCLR_EL0 and PMINTENCLR_EL1 clears written bits so we need an
> alternative raw write functions, which will be used to copy KVM kernel
> coprocessor state into userspace.
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/helper.c | 6
On 3/13/25 10:46, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
Copy to libuser_ss and libsystem_ss.
This file uses semihosting/semihost.h, which has separate
implementations with and without CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
gdbstub/meson.build | 4
John Snow writes:
> On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster
>> > wrote:
>> >
>> >> John Snow writes:
>> >>
>> >> > On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster
>> >> > wrote:
>> >> >
>> >>
On 13/3/25 19:05, Richard Henderson wrote:
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
For my person
On 3/13/25 09:59, Pierrick Bouvier wrote:
+static inline int
+cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
For my personal culture, is that strictly equivalent to d
On Thu, Mar 13, 2025 at 06:38:44PM +0100, Jörg Rödel wrote:
> Hey Alex,
>
> On Thu, Mar 13, 2025 at 05:30:30PM +0100, Alexander Graf wrote:
> > I have a few concerns with IGVM:
> >
> > 1) Parsing is non-trivial. Parsing them in QEMU may open security issues.
>
> There is an IGVM parsing library
On 13/3/25 17:36, Pierrick Bouvier wrote:
On 3/12/25 20:44, Richard Henderson wrote:
All this is working toward building accel/tcg/translator.c once,
but it got late and I decided to stop at a convenient milestone.
In the process, I discovered that we have already added files to
common_ss which
On 3/12/25 20:44, Richard Henderson wrote:
Copy to libuser_ss and libsystem_ss.
This file uses semihosting/semihost.h, which has separate
implementations with and without CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
gdbstub/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 d
On 3/12/25 20:44, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/display/vga_int.h | 2 +-
include/hw/char/parallel-isa.h| 2 +-
include/hw/dma/i8257.h| 2 +-
include/hw/ide/ide-bus.h | 2 +-
i
Hey Alex,
On Thu, Mar 13, 2025 at 05:30:30PM +0100, Alexander Graf wrote:
> I have a few concerns with IGVM:
>
> 1) Parsing is non-trivial. Parsing them in QEMU may open security issues.
There is an IGVM parsing library under MIT license and written in Rust
with C-bindings. The currently propose
On 3/12/25 20:44, Richard Henderson wrote:
We already have two subdirectories for which we need
to build files twice, for user vs system modes.
Move this handling to the top level.
This cannot be combined with user_ss or system_ss,
because the formulation has not been extended to support
configu
On 3/12/25 20:44, Richard Henderson wrote:
Convert the existing includes with sed.
Signed-off-by: Richard Henderson
---
hw/net/i82596.h | 2 +-
hw/s390x/ipl.h| 2 +-
include/hw/misc/lasi.h| 2 +-
include/hw/nubus/nub
On 3/12/25 20:44, Richard Henderson wrote:
Convert the existing includes with
sed -i ,exec/memory.h,system/memory.h,g
Move the include within cpu-all.h into a !CONFIG_USER_ONLY block.
Signed-off-by: Richard Henderson
---
hw/arm/strongarm.h| 2 +-
hw/display/apple
On 3/12/25 20:44, Richard Henderson wrote:
Split out mmap_lock, et al from page-protection.h
to a new header.
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h| 1 +
include/exec/mmap-lock.h | 33 +
include/exec/page-protection.h | 2
On 3/12/25 20:44, Richard Henderson wrote:
Cache the mmu index in DisasContextBase.
Perform the read on host endianness, which lets us
share code with the translator_ld fast path.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 +
accel/tcg/translator.c| 57 ++
On 3/12/25 20:44, Richard Henderson wrote:
Add a new family of translator load functions which take
an absolute endianness value in the form of MO_BE/MO_LE.
Expand the other translator_ld* functions on top of this.
Remove exec/tswap.h from translator.c.
Is there a need further down the road to
On 3/12/25 20:44, Richard Henderson wrote:
The mmap_lock is user-only, whereas watchpoint.c
is only compiled for system mode.
Signed-off-by: Richard Henderson
---
accel/tcg/watchpoint.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
inde
Steve Sistare writes:
> Fix bugs where the realize method re-initializes some memory regions during
> CPR. See the individual commit messages for details.
>
> Steve Sistare (4):
> migration: cpr_is_incoming
> pflash: fix cpr
> hw/loader: fix roms during cpr
> hw/qxl: fix cpr
>
> hw/bloc
Richard Henderson writes:
> Convert the existing includes with sed.
>
> Signed-off-by: Richard Henderson
> ---
> include/{exec => system}/ram_addr.h | 7 +++
> accel/kvm/kvm-all.c | 2 +-
> accel/tcg/cputlb.c | 2 +-
> accel/tcg/translate-all.c | 2
On 3/12/25 20:44, Richard Henderson wrote:
Perform aligned atomic reads in translator_ld, if possible.
According to
https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim@sifive.com/
this is required for RISC-V Ziccif.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c |
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmu api with trivial
massaging of the arguments.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 163
accel/tcg/ldst_common.c.inc | 118 --
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmu api with a lookup of
the target's cpu_mmu_index() and ra == 0.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 31 +++
accel/tcg/cputlb.c | 28 -
On 3/13/25 09:39, Pierrick Bouvier wrote:
Only system/physmem.c and system/memory.c use those functions, so we can
move then to internal header.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 19 +++
include/exec/memory.h | 18 --
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_data_ra api with ra == 0.
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 123 ++--
accel/tcg/ldst_common.c.inc | 89 --
2 files changed, 104 i
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmuidx_ra api with
a lookup of the target's cpu_mmu_index().
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 144 +---
accel/tcg/ldst_common.c.inc | 108
The following changes since commit 825b96dbcee23d134b691fc75618b59c5f53da32:
Merge tag 'migration-20250310-pull-request' of
https://gitlab.com/farosas/qemu into staging (2025-03-11 09:32:07 +0800)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
f
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On 3/12/25 20:44, Richard Henderson wrote:
These expand inline to the *_mmu api with trivial
massaging of the arguments.
I hope they feel relaxed after that :).
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 163
accel/tcg/ldst_com
Only system/physmem.c and system/memory.c use those functions, so we can
move then to internal header.
Signed-off-by: Pierrick Bouvier
---
include/exec/memory-internal.h | 19 +++
include/exec/memory.h | 18 --
2 files changed, 19 insertions(+), 18 deleti
On Thu, Mar 13, 2025, 11:57 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Thu, Mar 13, 2025 at 10:41 AM Markus Armbruster
> > wrote:
> >
> >> John Snow writes:
> >>
> >> > On Thu, Mar 13, 2025 at 2:47 AM Markus Armbruster
> wrote:
> >> >
> >> >> John Snow writes:
> >> >>
> >> >> >
1 - 100 of 252 matches
Mail list logo
