Re: [PATCH v2] qapi: pluggable backend code generators

Markus Armbruster writes: > Daniel P. Berrangé writes: > >> The 'qapi.backend.QAPIBackend' class defines an API contract for code >> generators. The current generator is put into a new class >> 'qapi.backend.QAPICBackend' and made to be the default impl. >> >> A custom generator can be requested

Re: [PATCH 2/8] hw/hexagon: Add machine configs for sysemu

Brian Cain writes: > From: Brian Cain > > Co-authored-by: Mike Lambert > Co-authored-by: Sid Manning > Signed-off-by: Brian Cain [...] > diff --git a/qapi/machine.json b/qapi/machine.json > index a6b8795b09..a7070bad4d 100644 > --- a/qapi/machine.json > +++ b/qapi/machine.json > @@ -33,7 +3

Re: [PULL 3/6] python: add qapi static analysis tests

Stefan Hajnoczi writes: > Hi John, > Please take a look at this CI failure: > https://gitlab.com/qemu-project/qemu/-/jobs/9284725716#L150 > > If you cannot reproduce it locally there is a chance that other pull > requests on the staging branch caused the errors. If that's the case, > please wait

[PATCH v2 0/2] hw/loongarch/virt: Small enhancements with ACPI table

There are two small enhancements about ACPI table on LoongArch virt machine type. One is replacing RSDT table with XSDT table to support 64 bit address, the other is adding support to customize OEM ID and OEM table ID. Bibo Mao (2): hw/loongarch/virt: Replace RSDT with XSDT table hw/loongarch/

[PATCH v2 1/2] hw/loongarch/virt: Replace RSDT with XSDT table

XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit address in the table. There is LoongArch system support from ACPI Specification 6.4 and later, XSDT is supported by LoongArch system. Here replace RSDT with XSDT table. Signed-off-by: Bibo Mao --- hw/loongarch/virt-acpi-buil

[PATCH v2 2/2] hw/loongarch/virt: Allow user to customize OEM ID and OEM table ID

On LoongArch virt machine, the default OEM ID and OEM table ID is "BOCHS " and "BXPC". Here property x-oem-id and x-oem-table-id is added on virt machine to set customized OEM ID and OEM table ID. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 58 ++

Re: [PATCH v5 28/36] vfio/migration: Multifd device state transfer support - config loading support

@@ -728,6 +728,12 @@ static int vfio_load_state(QEMUFile *f, void *opaque, int version_id)   switch (data) {   case VFIO_MIG_FLAG_DEV_CONFIG_STATE:   { +    if (vfio_multifd_transfer_enabled(vbasedev)) { +    error_report("%s: got DEV_CONFIG_STATE but d

Re: [PATCH v5 0/6] Fix hw-strap for AST2700

On 3/4/25 07:47, Jamin Lin wrote: v1: This patch series is from https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/. To expedite the review process, I have separated the SCU fix patches a. Fix the hw-strap and revision ID for SCU and SCUI

Re: [PATCH v5 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700

On 3/4/25 07:47, Jamin Lin wrote: According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. In the "aspeed_ast2600_scu_rese

Re: [PATCH v5 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO

On 3/4/25 07:47, Jamin Lin wrote: There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1 register in the SCUIO (IO DIE). The values of these two registers should not be the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the SCU and sets the value in th

[PATCH v5 1/6] hw/misc/aspeed_scu: Skipping dram_init in u-boot

Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning is done, therefore skipping the u-boot-spl dram_init() process. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Reviewed-by: Cédric Le Goater --- hw/misc/aspeed_scu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a

Re: [PATCH v4 23/23] docs/specs: Add aspeed-intc

On 3/3/25 10:54, Jamin Lin wrote: Add AST2700 INTC design guidance and its block diagram. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks, C. --- docs/specs/aspeed-intc.rst | 136 + docs/specs/index.rst | 1 + 2 files change

Re: [PATCH v4 14/23] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling

On 3/3/25 10:54, Jamin Lin wrote: This update introduces support for handling multi-output IRQs in the AST2700 interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a specific IRQ. Implemented "a

Re: [PATCH v2 2/9] vfio/igd: Do not include GTT stolen size in etc/igd-bdsm-size

On Tue, 2025-03-04 at 01:52 +0800, Tomita Moeko wrote: > Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM) > in host address space, direct access to GSM is prohibited, and it is > not mapped to guest address space. Both host and guest accesses GSM > indirectly through the secon

Re: [PATCH v4 18/23] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

On 3/3/25 10:54, Jamin Lin wrote: The design of INTC controllers has significantly changed in AST2700 A1. There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the limitation of interrupt numbers of pro

Re: [PATCH v4 17/23] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping

On 3/3/25 10:54, Jamin Lin wrote: Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0. These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197. Updates the interrupt mapping to include support for AST2700 A1 by extending the existing mappings to the new GIC range. Sign

Re: [PATCH v4 15/23] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller

On 3/3/25 10:54, Jamin Lin wrote: Introduce a new ast2700 INTCIO class to support AST2700 INTCIO. Added new register definitions for INTCIO, including enable and status registers for IRQs GICINT192 through GICINT197. Created a dedicated IRQ array for INTCIO, supporting six input pins and six outp

[PATCH] docs/cxl: Add serial number for persistent-memdev

Add serial number parameter in the cxl persistent examples. Signed-off-by: Yuquan Wang --- docs/system/devices/cxl.rst | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 882b036f5e..e307caf3f8 100

[PATCH v5 3/6] hw/arm/aspeed Update HW Strap Default Values for AST2700

Separate HW Strap Registers for SCU and SCUIO. AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1. AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1. Additionally, both default values are updated based on the dump from the EVB. Signed-off-by: Jamin Lin Reviewed-by: Cédric

[PATCH v5 6/6] hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700

Currently, ASPEED_DEV_SPI_BOOT is set to "0x4", which is the DRAM start address, and the QEMU loader is used to load the U-Boot binary into this address. However, if users want to install FMC flash contents as a boot ROM, the DRAM address 0x4 would be overwritten with Boot ROM dat

Re: [PATCH v4 12/23] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address

On 3/3/25 10:54, Jamin Lin wrote: The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to derive the IRQ index numbers. However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ p

[PATCH v5 0/6] Fix hw-strap for AST2700

v1: This patch series is from https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/. To expedite the review process, I have separated the SCU fix patches a. Fix the hw-strap and revision ID for SCU and SCUIO b. ix boot issue for AST2700 v2: a

[PATCH v5 4/6] hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer for AST2700

There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1 register in the SCUIO (IO DIE). In the "ast2700_a0_resets" function, the hardcoded value "0x0800" is set in SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value "0x0504" is set in SCUIO hw-stra

[PATCH v5 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO

There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1 register in the SCUIO (IO DIE). The values of these two registers should not be the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the SCU hw-strap1 register, while hw-s

Re: [PATCH] docs/cxl: Add serial number for persistent-memdev

> > On Thu, Feb 20, 2025 at 04:12:13PM +, Jonathan Cameron wrote: > > On Mon, 17 Feb 2025 19:20:39 +0800 > > Yuquan Wang wrote: > > > > > Add serial number parameter in the cxl persistent examples. > > > > > > Signed-off-by: Yuquan Wang > > Looks good. I've queued it up on my gitlab stag

Re: [PATCH v2 02/10] target/i386: disable PERFCORE when "-pmu" is configured

On 3/4/2025 2:45 AM, dongli.zh...@oracle.com wrote: Hi Xiaoyao, On 3/2/25 5:59 PM, Xiaoyao Li wrote: On 3/3/2025 6:00 AM, Dongli Zhang wrote: Currently, AMD PMU support isn't determined based on CPUID, that is, the "-pmu" option does not fully disable KVM AMD PMU virtualization. To minimize A

Re: [PATCH v4 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700

On 3/4/25 03:11, Jamin Lin wrote: Hi Cedric, Subject: Re: [PATCH v4 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 On 3/3/25 08:35, Jamin Lin wrote: According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and

[PATCH 1/2] i386/cpu: Move adjustment of CPUID_EXT_PDCM before feature_dependencies[] check

There is one entry relates to CPUID_EXT_PDCM in feature_dependencies[]. So it needs to get correct value of CPUID_EXT_PDCM before using feature_dependencies[] to apply dependencies. Besides, it also ensures CPUID_EXT_PDCM value is tracked in env->features[FEAT_1_ECX]. Signed-off-by: Xiaoyao Li -

[PATCH 0/2] i386: Adjust CPUID_EXT_PDCM based on enable_pmu at realization

First, it's not a good practice that values in env->features[] cannot be directly used for guest CPUID in void cpu_x86_cpuid(), but require further adjustment there. env->features[] are supposed to be finalized at cpu realization, so that after it env->features[] is reliable. Second, there is one

[PATCH 2/2] i386/cpu: Warn about why CPUID_EXT_PDCM is not available

When user requests PDCM explicitly via "+pdcm" without PMU enabled, emit a warning to inform the user. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2bf6495140a0..2aa2bab12100 100644 --- a/target

RE: [PATCH v4 19/23] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1

Hi Cedric, > Subject: Re: [PATCH v4 19/23] hw/arm/aspeed: Add SoC and Machine Support > for AST2700 A1 > > On 3/3/25 10:54, Jamin Lin wrote: > > The memory map for AST2700 A1 remains compatible with AST2700 A0. > > However, the IRQ mapping has been updated for AST2700 A1, with GIC > > interrupts

Re: [PATCH] scripts/checkpatch: Fix a typo

On Mon, Mar 03, 2025 at 06:25:08PM +0100, Philippe Mathieu-Daudé wrote: > When running checkpatch.pl on a commit adding a file without > SPDX tag we get: > > Undefined subroutine &main::WARNING called at ./scripts/checkpatch.pl line > 1694. > > The WARNING level is reported by the WARN() metho

RE: [PATCH v4 21/23] tests/functional/aspeed: Update test ASPEED SDK v09.05

Hi Cedric, > Subject: Re: [PATCH v4 21/23] tests/functional/aspeed: Update test ASPEED > SDK v09.05 > > May be add a little comment about the new ast2700-a0-default OpenBMC > build in v09.05. > Thanks for your suggestion and review. I will add the following comments in commit log. Jamin In ASPE

RE: [PATCH v4 20/23] tests/functional/aspeed: Introduce start_ast2700_test API and update hwmon path

Hi Cedric, > Subject: Re: [PATCH v4 20/23] tests/functional/aspeed: Introduce > start_ast2700_test API and update hwmon path > > On 3/3/25 10:54, Jamin Lin wrote: > > Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" > > class and this method centralizes the logic for starting th

RE: [PATCH v4 06/23] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0

Hi Cedric, > Subject: Re: [PATCH v4 06/23] hw/arm/aspeed: Rename IRQ table and machine > name for AST2700 A0 > > On 3/3/25 10:54, Jamin Lin wrote: > > Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename > > its IRQ table and machine name. > > > > To follow the machine deprecat

Re: [PATCH v2 7/9] vfio/igd: Decouple common quirks from legacy mode

On Tue, 4 Mar 2025 01:52:17 +0800 Tomita Moeko wrote: > diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c > index a58d555934..b0620a0ae8 100644 > --- a/hw/vfio/pci.c > +++ b/hw/vfio/pci.c > @@ -3363,6 +3363,8 @@ static const Property vfio_pci_dev_properties[] = { > VFIO_FEATURE_ENA

RE: [PATCH v4 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700

Hi Cedric, > Subject: Re: [PATCH v4 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be > set in the SOC layer for AST2700 > > On 3/3/25 08:35, Jamin Lin wrote: > > According to the design of the AST2600, it has a Silicon Revision ID > > Register, specifically SCU004 and SCU014, to set the Rev

RE: [PATCH v4 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO

Hi Cedric, > Subject: Re: [PATCH v4 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap > Registers for SCU and SCUIO > > On 3/3/25 08:35, Jamin Lin wrote: > > There is one hw-strap1 register in the SCU (CPU DIE) and another > > hw-strap1 register in the SCUIO (IO DIE). The values of these two > > reg

Re: [PATCH 0/2] hw/ufs: Add temperature event support and test cases

On 2/25/2025 3:40 PM, Keoseong Park wrote: This patch series introduces temperature event notification support in the UFS emulation and adds corresponding test cases to validate the feature. The first patch enables the UFS emulation to generate temperature-related events, including high and lo

Re: [PATCH v17 04/11] hw/misc/pvpanic: Add MMIO interface

On Mon, 3 Mar 2025 at 18:54, Philippe Mathieu-Daudé wrote: > On 12/1/25 22:00, Phil Dennis-Jordan wrote: > > From: Alexander Graf > > > > In addition to the ISA and PCI variants of pvpanic, let's add an MMIO > > platform device that we can use in embedded arm environments. > > > > Signed-off-by:

Re: [PATCH 1/1] hw/arm/sbsa-ref: Adding TPM support for ARM SBSA-Ref machine

Hi Leif & Peter, Thanks for the comments. I will address them in a v2 patch. Regards, Kun On Mon, Mar 3, 2025 at 12:44 PM Leif Lindholm < leif.lindh...@oss.qualcomm.com> wrote: > Doh! Add the lists back in. (No idea how I dropped them off.) > > On Mon, 3 Mar 2025 at 17:02, Leif Lindholm > wrot

Re: [PATCH v5 30/36] vfio/migration: Multifd device state transfer support - send side

On 2.03.2025 15:41, Avihai Horon wrote: On 19/02/2025 22:34, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" Implement the multifd device state transfer via additional per-device thread inside save_live_complete_precopy_thread

Re: [PATCH v5 14/36] migration/multifd: Device state transfer support - send side

On 2.03.2025 13:46, Avihai Horon wrote: On 19/02/2025 22:33, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" A new function multifd_queue_device_state() is provided for device to queue its state for transmission via a multifd c

Re: [PATCH v5 27/36] vfio/migration: Multifd device state transfer support - load thread

On 2.03.2025 15:15, Avihai Horon wrote: On 19/02/2025 22:34, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" Maybe add a sentence talking about the load thread itself first? E.g.: Add a thread which loads the VFIO device stat

Re: [PATCH v5 27/36] vfio/migration: Multifd device state transfer support - load thread

On 2.03.2025 15:19, Avihai Horon wrote: On 26/02/2025 15:49, Cédric Le Goater wrote: External email: Use caution opening links or attachments On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Since it's important to finish loading device state transferred via the mai

Re: [PATCH v5 28/36] vfio/migration: Multifd device state transfer support - config loading support

On 2.03.2025 15:25, Avihai Horon wrote: On 19/02/2025 22:34, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" Load device config received via multifd using the existing machinery behind vfio_load_device_config_state(). Also, ma

Re: [PATCH v5 31/36] vfio/migration: Add x-migration-multifd-transfer VFIO property

On 2.03.2025 15:48, Avihai Horon wrote: On 19/02/2025 22:34, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" This property allows configuring at runtime whether to transfer the IIUC, in this patch it's not configurable at run

[RFC PATCH] meson.build: add -gsplit-dwarf to default cflags

This option is supported by both gcc (since 4.7) and clang (since 7.0). Not only does this make the linkers job easier by reducing the amount of ELF it needs to parse it also reduces the total build size quite considerably. In my case a default build went from 5.8G to 3.9G. Signed-off-by: Alex Ben

Re: [PATCH v5 26/36] vfio/migration: Multifd device state transfer support - received buffers queuing

On 2.03.2025 14:12, Avihai Horon wrote: On 19/02/2025 22:34, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" The multifd received data needs to be reassembled since device state packets sent via different multifd channels can a

Re: [PATCH v5 23/36] vfio/migration: Multifd device state transfer support - VFIOStateBuffer(s)

On 3.03.2025 07:42, Cédric Le Goater wrote: On 3/2/25 14:00, Avihai Horon wrote: On 19/02/2025 22:34, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" Add VFIOStateBuffer(s) types and the associated methods. These store receiv

Re: [PATCH v5 11/36] migration/multifd: Device state transfer support - receive side

On 2.03.2025 13:42, Avihai Horon wrote: Hi Maciej, Sorry for the long delay, I have been busy with other tasks. I got some small comments for the series. On 19/02/2025 22:33, Maciej S. Szmigiero wrote: External email: Use caution opening links or attachments From: "Maciej S. Szmigiero" Add

Re: [PATCH v5 36/36] vfio/migration: Update VFIO migration documentation

On 1.03.2025 00:38, Fabiano Rosas wrote: Cédric Le Goater writes: On 2/27/25 23:01, Maciej S. Szmigiero wrote: On 27.02.2025 07:59, Cédric Le Goater wrote: On 2/19/25 21:34, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Update the VFIO documentation at docs/devel/migration descri

Re: [PATCH v17 11/11] hw/vmapple/vmapple: Add vmapple machine type

On 3/3/25 21:36, Phil Dennis-Jordan wrote: On Mon, 3 Mar 2025 at 19:20, Philippe Mathieu-Daudé > wrote: On 12/1/25 22:00, Phil Dennis-Jordan wrote: > From: Alexander Graf mailto:g...@amazon.com>> > > Apple defines a new "vmapple" machine type as pa

Re: [PATCH v17 11/11] hw/vmapple/vmapple: Add vmapple machine type

On 12/1/25 22:00, Phil Dennis-Jordan wrote: From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device addi

[PATCH V1 0/6] fast qom tree get

Using qom-list and qom-get to get all the nodes and property values in a QOM tree can take multiple seconds because it requires 1000's of individual QOM requests. Some managers fetch the entire tree or a large subset of it when starting a new VM, and this cost is a substantial fraction of start up

[PATCH V1 6/6] tests/qtest/qom-test: unit test for qom-list-getv

Add a unit test for qom-list-getv. Signed-off-by: Steve Sistare --- tests/qtest/qom-test.c | 66 ++ 1 file changed, 66 insertions(+) diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c index c567c4c..8785ea3 100644 --- a/tests/qtest/qom-t

Re: [PATCH] accel/tcg: fix msan findings in translate-all

On 3/3/25 08:40, Peter Foley wrote: And interestingly enough, it appears that execution continues even with early return from get_page_addr_code_hostp: https://gitlab.com/qemu-project/qemu/-/blob/master/accel/tcg/translate-all.c? ref_type=heads#L308

[PATCH V1 3/6] python: use qom-tree-get

Use qom-tree-get to speed up the qom-tree command. Signed-off-by: Steve Sistare --- python/qemu/utils/qom.py| 36 ++--- python/qemu/utils/qom_common.py | 50 + 2 files changed, 68 insertions(+), 18 deletions(-) diff --git a

[PATCH V1 4/6] tests/qtest/qom-test: unit test for qom-tree-get

Add a unit test for qom-tree-get Signed-off-by: Steve Sistare --- tests/qtest/qom-test.c | 50 ++ 1 file changed, 50 insertions(+) diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c index 27d70bc..c567c4c 100644 --- a/tests/qtest/qom-tes

[PATCH V1 5/6] qom: qom-list-getv

Define the qom-list-getv command, which fetches all the properties and values for a list of paths. This is faster than qom-tree-get when fetching a subset of the QOM tree. See qom.json for details. Signed-off-by: Steve Sistare --- qapi/qom.json | 34 ++ qom

[PATCH V1 2/6] qom: qom-tree-get

Define the qom-tree-get QAPI command, which fetches an entire tree of properties and values with a single QAPI call. This is much faster than using qom-list plus qom-get for every node and property of the tree. See qom.json for details. Signed-off-by: Steve Sistare --- qapi/qom.json | 59

[PATCH V1 1/6] qom: qom_resolve_path

Factor out a helper to resolve the user's path and print error messages. No functional change. Signed-off-by: Steve Sistare --- qom/qom-qmp-cmds.c | 21 +++-- 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/qom/qom-qmp-cmds.c b/qom/qom-qmp-cmds.c index e866547..293

Re: [PATCH 1/1] hw/arm/sbsa-ref: Adding TPM support for ARM SBSA-Ref machine

Doh! Add the lists back in. (No idea how I dropped them off.) On Mon, 3 Mar 2025 at 17:02, Leif Lindholm wrote: > > Hi Kun, > > Apologies for delay in responding - I was out last week. > I agree with this addition, since a TPM is a requirement for servers. > > However, to help simplify review, co

Re: [PATCH v4 24/24] target/m68k: Implement FPIAR

On 3/3/25 10:39, Philippe Mathieu-Daudé wrote: Hi Richard, On 24/2/25 18:14, Richard Henderson wrote: So far, this is only read-as-written. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2497 Signed-off-by: Richard Henderson ---   target/m68k/cpu.h   |  1 +   target/m68k/cpu.c   

Re: [PATCH v17 11/11] hw/vmapple/vmapple: Add vmapple machine type

On Mon, 3 Mar 2025 at 19:20, Philippe Mathieu-Daudé wrote: > On 12/1/25 22:00, Phil Dennis-Jordan wrote: > > From: Alexander Graf > > > > Apple defines a new "vmapple" machine type as part of its proprietary > > macOS Virtualization.Framework vmm. This machine type is similar to the > > virt one

Re: Adding gamma support to QemuMacDrivers

On Mon, 3 Mar 2025, Hab Gallagher wrote: That driver is for a VGA device which I think does not support gamma in hardware. QEMU emulates the hardware so if it does not support gamma then there's no place to add it in QEMU. Therefore if you want to emulate gamma on VGA this should be done within t

Re: [PATCH v3 036/162] tcg: Convert muluh to TCGOutOpBinary

On 3/3/25 02:52, Philippe Mathieu-Daudé wrote: Hi Richard, On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson ---   tcg/aarch64/tcg-target-has.h |  2 --   tcg/arm/tcg-target-has.h |  1 -   tcg/i386/tcg-target-has.h    |  2 --   tcg/loongarch64/tcg-targe

Re: [PATCH] tests/functional: add boot error detection for RME tests

Pierrick Bouvier writes: > It was identified that those tests randomly fail with a synchronous > exception at boot (reported by EDK2). > While we solve this problem, report failure immediately so tests don't > timeout in CI. > > Signed-off-by: Pierrick Bouvier Queued to maintainer/for-10.0-soft

Re: [PATCH] scripts/checkpatch: Fix a typo

Philippe Mathieu-Daudé writes: > On 3/3/25 18:25, Philippe Mathieu-Daudé wrote: >> When running checkpatch.pl on a commit adding a file without >> SPDX tag we get: >>Undefined subroutine &main::WARNING called at ./scripts/checkpatch.pl >> line 1694. >> The WARNING level is reported by the WA

Re: [PATCH v17 11/11] hw/vmapple/vmapple: Add vmapple machine type

On 3/3/25 19:20, Philippe Mathieu-Daudé wrote: On 12/1/25 22:00, Phil Dennis-Jordan wrote: From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in

Re: [PATCH v2 0/8] riscv: AIA: kernel-irqchip=off support

On Mon, Feb 24, 2025 at 04:24:07PM +0800, Yong-Xuan Wang wrote: > This series introduces the user-space AIA MSI emulation when using KVM > acceleration. > > After this series, RISC-V QEMU virt machine with KVM acceleration has > 3 parameters to control the type of irqchip and its emulation method:

[PATCH] tests/functional: add boot error detection for RME tests

It was identified that those tests randomly fail with a synchronous exception at boot (reported by EDK2). While we solve this problem, report failure immediately so tests don't timeout in CI. Signed-off-by: Pierrick Bouvier --- tests/functional/test_aarch64_rme_sbsaref.py | 3 ++- tests/function

Re: [PATCH] tests/functional: add boot error detection for RME tests

On 3/3/25 19:57, Pierrick Bouvier wrote: It was identified that those tests randomly fail with a synchronous exception at boot (reported by EDK2). While we solve this problem, report failure immediately so tests don't timeout in CI. Signed-off-by: Pierrick Bouvier --- tests/functional/test_aa

Re: [PATCH v3 052/162] tcg: Convert shl to TCGOutOpBinary

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++-- tcg/aarch64/tcg-target.c.inc | 38 ++-- tcg/arm/tcg-target.c.inc | 25 + tcg/i386/tcg-target.c.inc| 60

Re: [PATCH] util/keyval: fix msan findings

On 3/3/25 17:32, Peter Foley wrote: The full output looks like: Uninitialized bytes in strlen at offset 0 inside [0xd1958110, 5) ==9780==WARNING: MemorySanitizer: use-of-uninitialized-value #0 0xc1c4b170 in tdb_hash third_party/qemu/qobject/qdict.c:46:31 #1 0xc1c4b4a4 in qd

Re: [PATCH v2 02/10] target/i386: disable PERFCORE when "-pmu" is configured

Hi Xiaoyao, On 3/2/25 5:59 PM, Xiaoyao Li wrote: > On 3/3/2025 6:00 AM, Dongli Zhang wrote: >> Currently, AMD PMU support isn't determined based on CPUID, that is, the >> "-pmu" option does not fully disable KVM AMD PMU virtualization. >> >> To minimize AMD PMU features, remove PERFCORE when "-pmu

Re: [PATCH v4 24/24] target/m68k: Implement FPIAR

Hi Richard, On 24/2/25 18:14, Richard Henderson wrote: So far, this is only read-as-written. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2497 Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 1 + target/m68k/cpu.c | 23 ++- target/m68k/h

Re: [PATCH v4 01/24] target/m68k: Add FPSR exception bit defines

On 24/2/25 18:14, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/m68k/cpu.h| 21 + target/m68k/fpu_helper.c | 22 +++--- 2 files changed, 32 insertions(+), 11 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v4 04/24] target/m68k: Update FPSR.EXC

On 24/2/25 18:14, Richard Henderson wrote: So far we've only been updating the AEXC byte. Update the EXC byte as well. Signed-off-by: Richard Henderson --- target/m68k/fpu_helper.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v17 11/11] hw/vmapple/vmapple: Add vmapple machine type

On 12/1/25 22:00, Phil Dennis-Jordan wrote: From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device addi

Re: [PATCH 1/1] vhost: do not reset used_memslots when destroying vhost dev

> > Global used_memslots or used_shared_memslots is updated to 0 unexpectly > > it shouldn't be 0 in practice, as it comes from number of RAM regions VM has. > It's likely a bug somewhere else. > > Please describe a way to reproduce the issue. > Hi, Igor Mammedov, Sorry for the late response,

Re: [PATCH 1/2] vfio: Make vfio-pci available on 64-bit host platforms only

I see PPC is defined in target/ppc/Kconfig so I think these mark the target not the host. Vfio-pci works with qemu-system-ppc Ah ! I am surprised. Which host and QEMU machine please ? I've seen people do this on x86_64 host with pegasos2, amigaone and mac99 running 32 bit guests (AmigaOS a

Re: [PATCH 2/2] vfio: Make vfio-platform available on Aarch64 platforms only

Hi, On 3/3/25 3:32 PM, Philippe Mathieu-Daudé wrote: > On 27/2/25 18:27, Alex Williamson wrote: >> On Thu, 27 Feb 2025 09:32:46 +0100 >> Eric Auger wrote: >> >>> Hi Cédric, >>> >>> On 2/26/25 9:47 AM, Cédric Le Goater wrote: VFIO Platforms was designed for Aarch64. Restrict availability to

Re: [PATCH v17 00/11] New vmapple machine type and xhci fixes

On 15/1/25 16:40, Michael S. Tsirkin wrote: On Wed, Jan 15, 2025 at 04:33:45PM +0100, Phil Dennis-Jordan wrote: On Wed, 15 Jan 2025 at 16:08, Michael S. Tsirkin wrote: On Sun, Jan 12, 2025 at 10:00:45PM +0100, Phil Dennis-Jordan wrote: > This patch set introduces a new ARM and macO

Re: [PATCH v17 04/11] hw/misc/pvpanic: Add MMIO interface

On 12/1/25 22:00, Phil Dennis-Jordan wrote: From: Alexander Graf In addition to the ISA and PCI variants of pvpanic, let's add an MMIO platform device that we can use in embedded arm environments. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-D

[PATCH v2 3/9] vfio/igd: Consolidate OpRegion initialization into a single function

Both x-igd-opregion option and legacy mode require identical steps to set up OpRegion for IGD devices. Consolidate these steps into a single vfio_pci_igd_setup_opregion function. The function call in pci.c is wrapped with ifdef temporarily to prevent build error for non-x86 archs, it will be remov

[PATCH v2 6/9] vfio/igd: Refactor vfio_probe_igd_bar4_quirk into pci config quirk

The actual IO BAR4 write quirk in vfio_probe_igd_bar4_quirk was removed in previous change, leaving the function not matching its name, so move it into the newly introduced vfio_config_quirk_setup. There is no functional change in this commit. For now, to align with current legacy mode behavior, i

[PATCH v2 5/9] vfio/pci: Add placeholder for device-specific config space quirks

IGD devices require device-specific quirk to be applied to their PCI config space. Currently, it is put in the BAR4 quirk that does nothing to BAR4 itself. Add a placeholder for PCI config space quirks to hold that quirk later. Signed-off-by: Tomita Moeko --- hw/vfio/pci-quirks.c | 5 + hw/v

[PATCH v2 8/9] vfio/igd: Handle x-igd-opregion option in config quirk

Both enable OpRegion option (x-igd-opregion) and legacy mode require setting up OpRegion copy for IGD devices. As the config quirk no longer depends on legacy mode, we can now handle x-igd-opregion option there instead of in vfio_realize. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 14 ++

[PATCH v2 4/9] vfio/igd: Move LPC bridge initialization to a separate function

A new option will soon be introduced to decouple the LPC bridge/Host bridge ID quirk from legacy mode. To prepare for this, move the LPC bridge initialization into a separate function. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 122 +- 1 file

[PATCH v2 7/9] vfio/igd: Decouple common quirks from legacy mode

So far, IGD-specific quirks all require enabling legacy mode, which is toggled by assigning IGD to 00:02.0. However, some quirks, like the BDSM and GGC register quirks, should be applied to all supported IGD devices. A new feature bit, VFIO_FEATURE_ENABLE_IGD_LEGACY_MODE, is introduced to control t

Re: Adding gamma support to QemuMacDrivers

> > That driver is for a VGA device which I think does not support gamma in > hardware. QEMU emulates the hardware so if it does not support gamma then > there's no place to add it in QEMU. Therefore if you want to emulate gamma > on VGA this should be done within the guest driver but that may be s

[PATCH v2 9/9] vfio/igd: Introduce x-igd-lpc option for LPC bridge ID quirk

The LPC bridge/Host bridge IDs quirk is also not dependent on legacy mode. Recent Windows driver no longer depends on these IDs, as well as Linux i915 driver, while UEFI GOP seems still needs them. Make it an option to allow users enabling and disabling it as needed. Signed-off-by: Tomita Moeko -

[PATCH v2 1/9] vfio/igd: Remove GTT write quirk in IO BAR 4

The IO BAR4 of IGD devices contains a pair of 32-bit address/data registers, MMIO_Index (0x0) and MMIO_Data (0x4), which provide access to the MMIO BAR0 (GTTMMADR) from IO space. These registers are probably only used by the VBIOS, and are not documented by intel. The observed layout of MMIO_Index

[PATCH v2 0/9] vfio/igd: Decoupling quirks with legacy mode

This patchset intends to decouple existing quirks from legacy mode. Currently all quirks depends on legacy mode (except x-igd-opregion), which includes following conditions: * Machine type is i440fx * IGD device is at guest BDF 00:02.0 * VBIOS in ROM BAR or file * VGA IO/MMIO ranges are claimed by

[PATCH v2 2/9] vfio/igd: Do not include GTT stolen size in etc/igd-bdsm-size

Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM) in host address space, direct access to GSM is prohibited, and it is not mapped to guest address space. Both host and guest accesses GSM indirectly through the second half of MMIO BAR0 (GTTMMADR). Guest firmware only need to re

Re: [PATCH v17 03/11] hw: Add vmapple subdir

On 12/1/25 22:00, Phil Dennis-Jordan wrote: From: Alexander Graf We will introduce a number of devices that are specific to the vmapple target machine. To keep them all tidily together, let's put them into a single target directory. Signed-off-by: Alexander Graf Signed-off-by: Phil Dennis-Jor

Re: [PATCH v4 19/23] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1

On 3/3/25 10:54, Jamin Lin wrote: The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1. Add "aspeed_soc_ast2700a1_class_init" to initializ

Re: [PATCH 1/2] vfio: Make vfio-pci available on 64-bit host platforms only

On 3/3/25 17:57, Peter Maydell wrote: On Mon, 3 Mar 2025 at 15:49, Cédric Le Goater wrote: Why are we keeping qemu-system-ppc and qemu-system-i386, and arm, since qemu-system-ppc64 and qemu-system-x86_64 should be able to run the same machines ? They're not identical -- for example "-cpu max"

Re: [PATCH] scripts/checkpatch: Fix a typo

On 3/3/25 18:25, Philippe Mathieu-Daudé wrote: When running checkpatch.pl on a commit adding a file without SPDX tag we get: Undefined subroutine &main::WARNING called at ./scripts/checkpatch.pl line 1694. The WARNING level is reported by the WARN() method. Fix the typo. Fixes: fa4d79c64da

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