Akihiko Odaki writes:
> On 2025/02/20 17:02, Philippe Mathieu-Daudé wrote:
>> Introduce a helper to get the default shared library
>> suffix used on the host.
>> Suggested-by: Pierrick Bouvier
>> Signed-off-by: Philippe Mathieu-Daudé
>> Reviewed-by: Pierrick Bouvier
>> ---
>> tests/functiona
The PPN field in a non-leaf PDT entry is positioned differently from that
in a leaf PDT entry. The original implementation incorrectly used the leaf
entry's PPN mask to extract the PPN from a non-leaf entry, leading to an
erroneous page table walk.
This commit introduces new macros to properly def
This commit renames the macros to accurately reflect the direction of
DMA operations.
EDU_DMA_TO_PCI now represents reading memory content into the EDU buffer,
while EDU_DMA_FROM_PCI represents writing EDU buffer content to memory.
The previous naming was misleading, as the definitions were rever
Em Thu, 27 Feb 2025 08:19:27 +0100
Mauro Carvalho Chehab escreveu:
> Em Wed, 26 Feb 2025 16:52:26 +0100
> Igor Mammedov escreveu:
>
> > On Fri, 21 Feb 2025 15:35:17 +0100
> > Mauro Carvalho Chehab wrote:
> >
>
> > > diff --git a/hw/acpi/generic_event_device.c
> > > b/hw/acpi/generic_event
On 2025/02/26 6:52, Alex Williamson wrote:
Switch callers directly initializing the PCI PM capability with
pci_add_capability() to use pci_pm_init().
Cc: Dmitry Fleytman
Cc: Akihiko Odaki
Cc: Jason Wang
Cc: Stefan Weil
Cc: Sriram Yagnaraman
Cc: Keith Busch
Cc: Klaus Jensen
Cc: Jesper Deva
Em Wed, 26 Feb 2025 16:52:26 +0100
Igor Mammedov escreveu:
> On Fri, 21 Feb 2025 15:35:17 +0100
> Mauro Carvalho Chehab wrote:
>
> > diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
> > index 5346cae573b7..14d8513a5440 100644
> > --- a/hw/acpi/generic_event_device.c
On 2/27/2025 2:25 PM, Zhao Liu wrote:
From: Qian Wen
According to SDM, CPUID.0x4:EAX[31:26] indicates the Maximum number of
addressable IDs for processor cores in the physical package. If we
launch over 64 cores VM, the 6-bit field will overflow, and the wrong
core_id number will be reported.
On 2/27/2025 2:25 PM, Zhao Liu wrote:
From: Qian Wen
The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
Vol2:
Bits 23-16: Maximum number of addressable IDs for logical processors in
this physical package.
When threads_per_socket > 255, it will 1) overwrite bits[31:24] whic
On Wed, Feb 26, 2025 at 10:53:01AM +0100, David Hildenbrand wrote:
> > > As commented offline, maybe one would want the option to enable the
> > > alternative mode, where such updates (in the SHM region) are not sent to
> > > vhost-user devices. In such a configuration, the MEM_READ / MEM_WRITE
> >
On 2025/02/21 0:46, Michael S. Tsirkin wrote:
On Sat, Feb 08, 2025 at 04:51:10PM +0900, Akihiko Odaki wrote:
Some features are not always available with vhost. Legacy features are
not available with vp_vdpa in particular. virtio devices used to disable
them when not available even if the corresp
On 27/02/25 09:03, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
With all support in place, enable fadump by exporting the
"ibm,configure-kernel-dump" RTAS call in the device tree.
Presence of "ibm,configure-kernel-dump" tells the kernel that the
platform (QEM
On 2025/02/20 17:02, Philippe Mathieu-Daudé wrote:
Introduce a helper to get the default shared library
suffix used on the host.
Suggested-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
tests/functional/qemu_test/__init__.py | 2 +-
tests/funct
On Wed, Feb 26, 2025 at 09:53:53AM +, Daniel P. Berrangé wrote:
> On Wed, Feb 26, 2025 at 10:38:56AM +0100, Thomas Huth wrote:
> > On 26/02/2025 10.15, Daniel P. Berrangé wrote:
> > > On Wed, Feb 26, 2025 at 09:50:15AM +0100, Thomas Huth wrote:
> > > > When compiling QEMU with --enable-trace-ba
John Snow writes:
> On Wed, Feb 26, 2025 at 2:28 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > The pylint config is being left in place because the settings differ
>> > enough from the python/ directory settings that we need a chit-chat on
>> > how to merge them O:-)
>> >
>> > Ever
On 27/02/25 08:58, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
<...snip...>
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f3a4b4235d43..3602e5b5d18d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -897,9 +897,27 @@ static int spapr_dt_rng(void *fdt)
On 27/02/25 08:57, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
<...snip...>
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 9b29cadab2c9..0aca4270aee8 100644
<...snip...>
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -413,9 +416,174 @@ s
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Update the VFIO documentation at docs/devel/migration describing the
changes brought by the multifd device state transfer.
Signed-off-by: Maciej S. Szmigiero
---
docs/devel/migration/vfio.rst | 80 +
On 27/02/25 08:44, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structur
Hi Nick,
On 27/02/25 08:37, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
Implement the handler for "ibm,configure-kernel-dump" rtas call in QEMU.
Currently the handler just does basic checks and handles
register/unregister/invalidate requests from kernel.
Fa
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Allow capping the maximum count of in-flight VFIO device state buffers
queued at the destination, otherwise a malicious QEMU source could
theoretically cause the target QEMU to allocate unlimited amounts of memory
for buff
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This property allows configuring at runtime whether to transfer the
particular device state via multifd channels when live migrating that
device.
It defaults to AUTO, which means that VFIO device state transfer via
multif
Hi Nick,
On 27/02/25 09:07, Nicholas Piggin wrote:
On Mon Feb 17, 2025 at 5:19 PM AEST, Aditya Gupta wrote:
Overview
=
Implemented MPIPL (Memory Preserving IPL, aka fadump) on PowerNV machine
in QEMU.
Wow, that's a lot of effort.
Thanks Nick.
Note: It's okay if this isn't merged
On 2025/02/18 15:27, Dmitry Osipenko wrote:
On 2/13/25 07:32, Akihiko Odaki wrote:
On 2025/02/10 6:03, Dmitry Osipenko wrote:
On 2/6/25 08:41, Akihiko Odaki wrote:
On 2025/02/06 2:40, Dmitry Osipenko wrote:
On 2/3/25 08:31, Akihiko Odaki wrote:
...
Requirements don't vary much. For example v
25.02.2025 15:39, Konstantin Shkolnyy wrote:
On 2/25/2025 03:30, Michael Tokarev wrote:
This looks like a qemu-stable material.
Please let me know if it is not.
It won't help without my other "[PATCH v2] vdpa: Allow vDPA to work on big-endian
machine". With both patches, VDPA works on a big
On Wed, Feb 26, 2025 at 02:28:35PM -0600, Moger, Babu wrote:
> Date: Wed, 26 Feb 2025 14:28:35 -0600
> From: "Moger, Babu"
> Subject: Re: [PATCH v5 1/6] target/i386: Update EPYC CPU model for Cache
> property, RAS, SVM feature bits
>
> Hi John,
>
> On 2/25/25 11:01, John Allen wrote:
> > On Thu
From: Qian Wen
According to SDM, CPUID.0x4:EAX[31:26] indicates the Maximum number of
addressable IDs for processor cores in the physical package. If we
launch over 64 cores VM, the 6-bit field will overflow, and the wrong
core_id number will be reported.
Since the HW reports 0x3f when the intel
From: Chuang Xu
When QEMU is started with:
-cpu host,migratable=on,host-cache-info=on,l3-cache=off
-smp 180,sockets=2,dies=1,cores=45,threads=2
On Intel platform:
CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for
logical processors in the physical package".
When executing "c
Hi,
This series collects and organizes several topology-related cleanups and
fixes, based on b69801dd6b1e ("Merge tag 'for_upstream' of
https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging").
Patch 1 is picked from Chuang's v6 [1].
Patch 2-3 are picked from Qian's v4 [2], though it had
From: Qian Wen
The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM
Vol2:
Bits 23-16: Maximum number of addressable IDs for logical processors in
this physical package.
When threads_per_socket > 255, it will 1) overwrite bits[31:24] which is
apic_id, 2) bits [23:16] get trunca
CPUID.801DH:EAX[25:14] is "NumSharingCache", and the number of
logical processors sharing this cache is the value of this field
incremented by 1. Because of its width limitation, the maximum value
currently supported is 4095.
Though at present Q35 supports up to 4096 CPUs, to prevent potential
On Mon Feb 17, 2025 at 5:19 PM AEST, Aditya Gupta wrote:
> Overview
> =
>
> Implemented MPIPL (Memory Preserving IPL, aka fadump) on PowerNV machine
> in QEMU.
Wow, that's a lot of effort.
> Note: It's okay if this isn't merged as there might be less users. Sending
> for archieval purpose
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
> Kernel expects CPU states/register states in the format mentioned in
> "Register Save Area" in PAPR.
>
> The platform (in our case, QEMU) saves each CPU register in the form of
> an array of "register entries", the start and end of this arr
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
> With all support in place, enable fadump by exporting the
> "ibm,configure-kernel-dump" RTAS call in the device tree.
>
> Presence of "ibm,configure-kernel-dump" tells the kernel that the
> platform (QEMU) supports fadump.
>
> Pass "fadump=
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
> Platform (ie. QEMU) is expected to pass few device tree properties for
> details for fadump:
>
> * "ibm,configure-kernel-dump": RTAS call for fadump
> * "ibm,configure-kernel-dump-sizes": Space required to store dump data
> for firm
On 2/26/2025 8:43 PM, Chenyi Qiang wrote:
>
>
> On 2/25/2025 5:41 PM, David Hildenbrand wrote:
>> On 25.02.25 03:00, Chenyi Qiang wrote:
>>>
>>>
>>> On 2/21/2025 6:04 PM, Chenyi Qiang wrote:
On 2/21/2025 4:09 PM, David Hildenbrand wrote:
> On 21.02.25 03:25, Chenyi Qiang wro
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
> According to PAPR:
>
> R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
> on a system reset without an ibm,nmi-interlock RTAS call, if the
> platform has a dump structure registered through the
> ibm,conf
On Mon Feb 17, 2025 at 5:17 PM AEST, Aditya Gupta wrote:
> Implement the handler for "ibm,configure-kernel-dump" rtas call in QEMU.
>
> Currently the handler just does basic checks and handles
> register/unregister/invalidate requests from kernel.
>
> Fadump will be enabled in a later patch.
>
> Si
On Thu, 27 Feb 2025, Nicholas Piggin wrote:
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
Initialise empty NVRAM with default values. This also enables IDE UDMA
mode in AmigaOS that is faster but has to be enabled in environment
due to problems with real hardware but that does not a
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
> There is a possibility that SPI controller can get into loop due to indefinite
> RDR match failures. Hence put a limit to failures and stop the sequencer.
>
> Signed-off-by: Chalapathi V
> ---
> hw/ssi/pnv_spi.c | 11 +++
> 1 file
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
> Create a spi buses with distict names on each socket so that responders
> are attached to correct SPI controllers.
>
> QOM tree on a 2 socket machine:
> (qemu) info qom-tree
> /machine (powernv10-machine)
> /chip[0] (power10_v2.0-pnv-chip)
On Thu, 27 Feb 2025, Nicholas Piggin wrote:
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
The board has a battery backed NVRAM where U-Boot environment is
stored which is also accessed by AmigaOS and e.g. C:NVGetVar command
crashes without it having at least a valid checksum.
Signe
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
> Use a local variable seq_index instead of repeatedly calling
> get_seq_index() method and open-code next_sequencer_fsm().
Oh... one other thing, this is no longer a fix for CID
1558827, right? Just need to change the subject to remove
that.
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
> Use a local variable seq_index instead of repeatedly calling
> get_seq_index() method and open-code next_sequencer_fsm().
>
> Signed-off-by: Chalapathi V
> ---
> hw/ssi/pnv_spi.c | 93 +---
> 1 f
On Sat Jan 4, 2025 at 2:18 AM AEST, Chalapathi V wrote:
> In PnvXferBuffer dynamically allocating and freeing is a
> process overhead. Hence used an existing Fifo8 buffer with
> capacity of 16 bytes.
>
> Signed-off-by: Chalapathi V
> ---
> include/hw/ssi/pnv_spi.h | 3 +
> hw/ssi/pnv_spi.c
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
> Add support for -kernel, -initrd and -append command line options.
Looks okay. Any test case could be added to test_ppc_amiga.py?
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/ppc/amigaone.c | 113 +++
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
> Initialise empty NVRAM with default values. This also enables IDE UDMA
> mode in AmigaOS that is faster but has to be enabled in environment
> due to problems with real hardware but that does not affect emulation
> so we can use faster de
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
> The board has a battery backed NVRAM where U-Boot environment is
> stored which is also accessed by AmigaOS and e.g. C:NVGetVar command
> crashes without it having at least a valid checksum.
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/
On Wed Feb 26, 2025 at 4:46 AM AEST, Alex Bennée wrote:
> The vCPU parent already triggers a tb_flush so this is un-needed:
>
> #0 tlb_flush_other_cpu (cpu=0x56df8630) at ../../accel/tcg/cputlb.c:419
> #1 0x55ee38c9 in tcg_cpu_reset_hold (cpu=0x56df8630) at
> ../../accel/tcg/
On Sun Feb 23, 2025 at 3:52 AM AEST, BALATON Zoltan wrote:
> There's no need to do shift in a loop, doing it in one instruction
> works just as well, only the result is used.
>
> Signed-off-by: BALATON Zoltan
Resulting asm looks right to me.
Reviewed-by: Nicholas Piggin
> ---
> hw/ppc/amigaon
On Tue Jan 28, 2025 at 4:43 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> target/ppc/excp_helper.c | 6 ++
>> 1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/ppc/excp_hel
On 26/02/2025 23:51, Peter Xu wrote:
> On Wed, Feb 26, 2025 at 02:30:42PM +0800, Li Zhijian wrote:
>> control_save_page() is for RDMA only, unfold it to make the code more
>> clear.
>> In addition:
>> - Similar to other branches style in ram_save_target_page(), involve RDMA
>> only if the c
On Mon, Feb 24, 2025 at 2:46 PM wrote:
>
> From: Quan Zhou
>
> When the Sscofpmf/Svade/Svadu/Smnpm/Ssnpm exts is available
> expose it to the guest so that guest can use it.
>
> Signed-off-by: Quan Zhou
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 5 +
On Tue, Feb 25, 2025 at 11:49 AM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> Since C always implies Zca, Zca is always enabled when 16-bit
> insructions are supported. we can only check ext_zca to allow
> 16-bit aligned PC addresses.
>
> Signed-off-by: Yu-Ming Chang
Reviewed-by: Alistair Francis
On 26/2/25 15:03, Alex Bennée wrote:
Requiring TARGET_PAGE_MASK to be defined gets in the way of building
this unit once. qemu_target_page_mask() will tell us what it is.
Signed-off-by: Alex Bennée
Message-Id: <20250225110844.3296991-2-alex.ben...@linaro.org>
---
v2
- use the proper qemu_ta
On 26/2/25 11:48, Thomas Huth wrote:
The kernel that is used in the sx1 test prints the usual Linux log
onto the serial console, but this test currently ignores it. To
make sure that the serial device is working properly, let's check
for some strings in the output here.
While we're at it, also a
On 17/2/25 00:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-has.h| 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h| 2 --
On 17/2/25 00:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-has.h| 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h| 2 --
On 17/2/25 00:07, Richard Henderson wrote:
At the same time, drop all backend support for immediate
operands, as we now transform orc to or during optimize.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i3
On 2/26/25 13:51, Philippe Mathieu-Daudé wrote:
On 22/2/25 18:41, Richard Henderson wrote:
On 2/20/25 14:17, Philippe Mathieu-Daudé wrote:
@@ -1794,23 +1715,19 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1,
int64_t arg2)
case -1:
tcg_gen_mov_i64(ret, arg1);
ret
On 22/2/25 18:41, Richard Henderson wrote:
On 2/20/25 14:17, Philippe Mathieu-Daudé wrote:
@@ -1794,23 +1715,19 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64
arg1, int64_t arg2)
case -1:
tcg_gen_mov_i64(ret, arg1);
return;
- case 0xff:
- /* Don't recurse wi
On 17/2/25 00:07, Richard Henderson wrote:
At the same time, drop all backend support for immediate
operands, as we now transform andc to and during optimize.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/
On 17/2/25 00:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-has.h| 2 --
tcg/loongarch64/tcg-target-has.h | 2 --
tcg/mips/tcg-target-has.h| 2 --
Currently s390x does not support ISM passthrough without zPCI
interpretation. This is already fenced, but the current message will
not provide adequate information to explain to the end-user why ISM
passthrough is not allowed. Add a proper message.
Suggested-by: Thomas Huth
Signed-off-by: Matth
On 26.02.2025 17:43, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Implement the multifd device state transfer via additional per-device
thread inside save_live_complete_precopy_thread handler.
Switch between doing the data transfer in the ne
On Mon, Feb 24, 2025 at 11:39:46AM +1000, Alistair Francis wrote:
> On Tue, Jan 28, 2025 at 4:29 AM Andrea Bolognani wrote:
> > Right now information regarding the family each CPU type belongs
> > to is recorded in two places: the large data table at the top of
> > the script, and the qemu_host_fa
On 26.02.2025 18:59, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
DEFINE_PROP_ON_OFF_AUTO() property isn't runtime-mutable so using it
would mean that the source VM would need to decide upfront at startup
time whether it wants to do a multifd
On 26.02.2025 14:49, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Since it's important to finish loading device state transferred via the
main migration channel (via save_live_iterate SaveVMHandler) before
starting loading the data asynchrono
On 26.02.2025 14:52, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Load device config received via multifd using the existing machinery
behind vfio_load_device_config_state().
Also, make sure to process the relevant main migration channel fla
On 26.02.2025 11:43, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different multifd channels can arrive out-of-order.
Therefore, each VFIO device state pac
In the unlikely event that we must fail hotplug of a PCI passthrough
device, ensure appropriate clean up of the associated zPCI device is
performed.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git
Thomas previously requested a more meaningful message when plug of a
passthrough ISM device fails (interpretation facility required). In
the process of creating that patch, I noticed that devices that fail
s390_pcihost_plug during a hotplug scneario can potentially crash QEMU
because remnants of
Specifying this bit in the guest CLP response indicates that the guest
can optionally choose to skip translation and instead use
identity-mapped operations.
Tested-by: Niklas Schnelle
Reviewed-by: Niklas Schnelle
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c| 5 -
incl
This series introduces the concept of the relaxed translation requirement
for s390x guests in order to allow bypass of the guest IOMMU for more
efficient PCI passthrough.
With this series, QEMU can indicate to the guest that an IOMMU is not
strictly required for a zPCI device. This would subseque
When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T
bit set, treat this as a request to perform direct mapping instead of
address translation. In order to facilitate this, pin the entirety of
guest memory into the host iommu.
Pinning for the direct mapping case is handled via
(edited cc list since it's moved away from a discussion of this
particular patch and on to a testing/ci coverage issue)
On Wed, 26 Feb 2025 at 19:03, Pierrick Bouvier
wrote:
>
> On 2/26/25 03:50, Peter Maydell wrote:
> > On Tue, 25 Feb 2025 at 20:57, Pierrick Bouvier
> > wrote:
> >>
> >> On 2/25
Hi John,
On 2/25/25 11:01, John Allen wrote:
> On Thu, Feb 20, 2025 at 06:59:34PM +0800, Zhao Liu wrote:
>> And one more thing :-) ...
>>
>>> static const CPUCaches epyc_rome_cache_info = {
>>> .l1d_cache = &(CPUCacheInfo) {
>>> .type = DATA_CACHE,
>>> @@ -5207,6 +5261,25 @@ static
On 2/26/25 03:50, Peter Maydell wrote:
On Tue, 25 Feb 2025 at 20:57, Pierrick Bouvier
wrote:
On 2/25/25 05:41, Peter Maydell wrote:
(Looking more closely at the cold_reset_values handling
in npcm_gcr.c, that looks not quite right in a different
way; I'll send a reply to that patch email about
Richard Henderson writes:
> On 2/26/25 06:03, Alex Bennée wrote:
>> 'aarch64_virt' : 720,
>> + 'aarch64_virt_gpu' : 720,
>
> Does the split mean that we can reduce the timeout?
My run with all 4 tests takes ~100s but when people --enable-debug and
santisers that expands quickly.
>
>
> r~
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add a hw_compat entry for recently added x-migration-multifd-transfer VFIO
property.
Signed-off-by: Maciej S. Szmigiero
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/core/machine.c | 1 +
1 file changed, 1
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
DEFINE_PROP_ON_OFF_AUTO() property isn't runtime-mutable so using it
would mean that the source VM would need to decide upfront at startup
time whether it wants to do a multifd device state transfer at some
point.
Source
On 2/26/25 06:29, Alex Bennée wrote:
I guess we want something like:
/* tlb_reset() - reset the TLB when the CPU is not running
* cs: the cpu
*
* Only to be used when the CPU is definitely not running
*/
void tlb_reset(CPUState *cs) {
g_assert(cs->cpu_stopped);
for (i = 0;
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
On 2/26/25 15:12, BALATON Zoltan wrote:
On Wed, 26 Feb 2025, Cédric Le Goater wrote:
VFIO PCI never worked on PPC32 nor ARM, S390x is 64-bit, it might have
worked on i386 long ago but we have no plans to further support VFIO
on any 32-bit host platfo
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data structure that will contain most of the
receive-side data together with its init/cleanup methods.
Signed-off-by: Maciej S. Szmigiero
---
hw/vfio/migration-multifd.c | 33 +
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data structure that will contain most of the
receive-side data together with its init/cleanup methods.
Signed-off-by: Maciej S. Szmigiero
---
hw/vfio/migration-multifd.c | 33 +
On 2/26/25 06:03, Alex Bennée wrote:
+++ b/linux-user/plugin-api.c
@@ -0,0 +1,14 @@
+/*
+ * QEMU Plugin API - linux-user-mode only implementations
+ *
+ * Common user-mode only APIs are in plugins/api-user. These helpers
+ * are only specific to linux-user.
+ *
+ * Copyright (C) 2017, Emilio G. C
On 26.02.2025 18:22, Cédric Le Goater wrote:
On 2/26/25 11:14, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data structure that will contain most of the
receive-side data together with its init/cleanup methods.
S
On 2/26/25 06:03, Alex Bennée wrote:
Requiring TARGET_PAGE_MASK to be defined gets in the way of building
this unit once. qemu_target_page_mask() will tell us what it is.
Signed-off-by: Alex Bennée
Message-Id:<20250225110844.3296991-2-alex.ben...@linaro.org>
---
v2
- use the proper qemu_targ
On 2/26/25 06:03, Alex Bennée wrote:
Clang complains:
clang -O2 -m64 -mcx16
/home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c -o test-i386-adcox
-static
/home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c:32:26: error:
invalid input constraint '0' in asm
: "r" (
On 2/26/25 06:03, Alex Bennée wrote:
We allow things like:
tests/tcg/i386/test-i386-bmi2.c:124:35: warning: shifting a negative signed
value is undefined [-Wshift-negative-value]
assert(result == (mask & ~(-1 << 30)));
in the main code, so allow it for the test.
Signed-off-by: Alex
On 2/26/25 11:14, Cédric Le Goater wrote:
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Add support for VFIOMultifd data structure that will contain most of the
receive-side data together with its init/cleanup methods.
Signed-off-by: Maciej S. Szmigiero
---
hw/vf
On 2/26/25 06:03, Alex Bennée wrote:
'aarch64_virt' : 720,
+ 'aarch64_virt_gpu' : 720,
Does the split mean that we can reduce the timeout?
r~
On 2/26/25 09:03, Aleksandar Rakic wrote:
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -399,7 +399,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
if (ase_msa_available(env)) {
-if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
+if ((
From: Aleksandar Rakic
Aleksandar Rakic (3):
Add support for emulation of CRC32 instructions
Skip NaN mode check for soft-float
target/mips: Enable MSA ASE using a CLI flag
linux-user/mips/cpu_loop.c| 6 +-
target/mips/cpu-defs.c.inc| 10 +-
targ
Hi,
This patch series adds support for emulation of CRC32 instructions for
the Mips target in QEMU, enables CRC for mips64r6, skips NaN mode check
for soft-float, and adds a CLI flag for enabling an MSA feature.
The CRC32 instructions are available in MD00087 Revision 6.06.
Since the disassembly
From: Aleksandar Rakic
Enable MSA ASE using a CLI flag -cpu ,msa=on.
Signed-off-by: Aleksandar Rakic
---
target/mips/cpu.c | 16
target/mips/cpu.h | 1 +
target/mips/internal.h | 2 +-
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c
From: Aleksandar Rakic
Skip NaN mode check for soft-float since NaN mode is irrelevant if an ELF
binary's FPU mode is soft-float, i.e. it doesn't utilize a FPU.
Cherry-picked 63492a56485f6b755fccf7ad623f7a189bfc79b6
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Faraz Shahbazker
Sig
From: Aleksandar Rakic
Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().
Enable CRC for mips64r6.
Cherry-picked 4cc974938aee1588f852590509004e340c072940
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Yongbok Kim
Signed-off-b
On Wed, Feb 19, 2025 at 09:33:59PM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> This SaveVMHandler helps device provide its own asynchronous transmission
> of the remaining data at the end of a precopy phase via multifd channels,
> in parallel with the transfer done by save
On 2/19/25 21:34, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Implement the multifd device state transfer via additional per-device
thread inside save_live_complete_precopy_thread handler.
Switch between doing the data transfer in the new handler and doing it
in the old save_state h
Hello,
On 2/26/25 10:04, Daniel P. Berrangé wrote:
On Wed, Feb 26, 2025 at 08:01:09AM +0100, Thomas Huth wrote:
On 26/02/2025 07.54, Cédric Le Goater wrote:
The tests are using a now archived Fedora29 release. Switch to the
most recent Fedora41 release.
Signed-off-by: Cédric Le Goater
---
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