Hello Zhenzhong,
On 2/21/25 07:12, Duan, Zhenzhong wrote:
-Original Message-
From: Alex Williamson
Subject: [PATCH 4/5] pcie, virtio: Remove redundant pm_cap
The pm_cap on the PCIExpressDevice object can be distilled down
to the new instance on the PCIDevice object.
Cc: Michael S.
As shown in the PL011 device, the orphan rules required a manual
implementation of ClassInitImpl for anything not in the qemu_api crate;
this gets in the way of moving system emulation-specific code (including
DeviceClass, which as a blanket ClassInitImpl implementation)
into its own crate.
Make C
From: Khem Raj
glibc 2.41+ has added [1] definitions for sched_setattr and
sched_getattr functions and struct sched_attr. Therefore, it needs
to be checked for here as well before defining sched_attr, to avoid
a compilation failure.
Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0
On Fri, 21 Feb 2025 at 14:41, Philippe Mathieu-Daudé wrote:
>
> On 17/2/25 13:50, Peter Maydell wrote:
>
> > (1) floatx80 behaviours
> >
> > Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
> > use in the xsrqpxp round-to-80-bit-precision operation, and the
> > Linux-user NWFPE
On 2/20/25 06:11, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v3 00/28] Support AST2700 A1
Hello Jamin,
On 2/13/25 04:35, Jamin Lin wrote:
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Am 21. Februar 2025 07:34:44 UTC schrieb Ilya Chichkov :
>Add PCF8563 a real-time clock with calendar and I2C interface.
Nice! I'd like to use it myself.
>This commit adds support for interfacing with it and implements
>functionality of setting timer, alarm, reading and writing time.
>
>Datash
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 6
rust/qemu-api/src/qdev.rs | 68 ---
rust/qemu-api/src/vmstate.rs | 2 +-
3 files changed, 49 insertions(+), 27 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/s
From: Mikael Szreder
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even register numbers
and
On 2/20/25 16:19, Philippe Mathieu-Daudé wrote:
Hmm what about keeping a MAC_PVG_COMMON instead:
-- >8 --
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -141,15 +141,17 @@ config XLNX_DISPLAYPORT
config DM163
bool
-config MAC_PVG
+config MAC_PVG_COMMON
bool
- default y
+
On 2/20/25 10:54, Peter Maydell wrote:
On Thu, 20 Feb 2025 at 18:39, Richard Henderson
wrote:
On 2/20/25 09:12, Peter Maydell wrote:
That suggests that we are correctly implementing the x87
required behaviour in QEMU, and so that the TODO comment
I add in this patch isn't right. But then I'm
The DSDT table will also be affected by such change.
Signed-off-by: Mauro Carvalho Chehab
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8
On Fri, Feb 21, 2025 at 04:53:26PM +, Peter Maydell wrote:
> On Fri, 21 Feb 2025 at 14:02, Wei Liu wrote:
> >
> > Hi,
> >
> > Microsoft's Linux Systems Group developed a Linux driver for the Microsoft
> > Hypervisor (MSHV for short). The driver is being upstreamed. The first
> > supported VMM
The softfloat (i.e. TCG) specific handling for the FPCR
and FPSR is abstracted behind five functions:
arm_set_default_fp_behaviours
arm_set_ah_fp_behaviours
vfp_get_fpsr_from_host
vfp_clear_float_status_exc_flags
vfp_set_fpsr_to_host
Currently we rely on the first two calling softfloat functi
On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
> This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the
> pasid entry and track PASID usage and future PASID tagged DMA address
> translation support in vIOMMU.
>
> VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/memory.rs | 30 --
2 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs
index b791ca6d87f..26cc8de0cf2
Currently the helper_vfp_get_fpscr() and helper_vfp_set_fpscr()
functions do the actual work of updating the FPSCR, and we have
wrappers vfp_get_fpscr() and vfp_set_fpscr() which we use for calls
from other QEMU C code.
Flip these around so that it is vfp_get_fpscr() and vfp_set_fpscr()
which do t
The vfp_helper.c in the target/arm directory now only has
code for handling FPSCR/FPCR/FPSR in it, and no helper
functions. Rename it to vfp_fpscr.c; this helps keep it
distinct from tcg/vfp_helper.c.
Signed-off-by: Peter Maydell
---
target/arm/{vfp_helper.c => vfp_fpscr.c} | 2 +-
target/arm/me
Most of the target/arm/vfp_helper.c file is purely TCG helper code,
guarded by #ifdef CONFIG_TCG. Move this into a new file in
target/arm/tcg/.
This leaves only the code relating to getting and setting the
FPCR/FPSR/FPSCR in the original file. (Some of this also is
TCG-only, but that needs more c
target/arm/vfp_helper.c is almost entirely TCG-specific code,
guarded by #ifdef CONFIG_TCG. The only parts that aren't
TCG-specific are the handling of the FPSCR/FPSR/FPCR registers.
(I noticed this while I was working on the FEAT_AFP code, and
it felt a bit awkward but I left it as-is at the time.
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Signed-off-by: Konstantin Shkolnyy
---
Changes in V
On Fri, Feb 21, 2025 at 05:36:39PM +0100, Paolo Bonzini wrote:
> On 2/21/25 09:36, Wei Liu wrote:
> > This patch series attempts to make the instruction emulator in HVF a common
> > component for the i386 target. It removes HVF specific code by either using
> > a
> > set of hooks or moving it to b
On Fri, Feb 21, 2025 at 1:42 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Wed, Feb 19, 2025 at 8:22 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > "The text handler you add looks just like the existing latex handler.
> Does
> >> > LaTeX output lack "little hea
On 2/11/25 3:20 PM, Paolo Savini wrote:
This commit improves the performance of QEMU when emulating strided vector
loads and stores by substituting the call for the helper function with the
generation of equivalend TCG operations.
s/equivalend/equivalent
Signed-off-by: Paolo Savini
---
On Fri, 21 Feb 2025 at 18:02, Alex Bennée wrote:
>
> Peter Maydell writes:
>
> > When we added Secure EL2 support, we missed that this needs an update
> > to the access code for the EL3 physical timer registers. These are
> > supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
> >
> >
Add a derive macro that makes it easy to peel off all the layers of
specialness (UnsafeCell, MaybeUninit, etc.) and just get a pointer
to the wrapped type; and likewise add them back starting from a
*mut.
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst | 8 ++--
rust/qemu-api-m
From: Volker Rümelin
Windows only:
The libSDL2 Windows message loop needs the libSDL2 Windows low
level keyboard hook procedure to grab the left and right Windows
keys correctly. Reenable the SDL2 Windows keyboard hook procedure.
Since SDL2 2.30.4 the SDL2 keyboard hook procedure also filters
o
From: Peter Maydell
The SMC91C111 includes an MMU Command register which permits
the guest to remove entries from the RX FIFO. The datasheet
does not specify what happens if the guest tries to do this
when the FIFO is already empty; there are no status registers
containing error bits which might
Peter Maydell writes:
> When we added Secure EL2 support, we missed that this needs an update
> to the access code for the EL3 physical timer registers. These are
> supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
>
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Peter Maydell
> ---
Update the code in net/slirp.c to be compatible with
libslirp 4.9.0, which deprecated slirp_pollfds_fill()
and started using slirp_os_socket type for sockets
(which is a 64-bit integer on win64) for all callbacks
starting with version 6 of the interface.
Signed-off-by: Michael Tokarev
Reviewed-by
From: Paolo Bonzini
Without it, recent bindgen will give an error
error: extern block cannot be declared unsafe
if rustc is not new enough to support the "unsafe extern" construct.
Cc: qemu-r...@nongnu.org
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
Message-ID: <20250206111514.
On 2/21/25 09:36, Wei Liu wrote:
This patch series attempts to make the instruction emulator in HVF a common
component for the i386 target. It removes HVF specific code by either using a
set of hooks or moving it to better locations. The new incoming MSHV
accelerator will implement the hooks, and
On 2/21/25 17:14, Alex Bennée wrote:
The following organisations appear on the US sanctions list:
Yadro: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=41125
ISPRAS: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=50890
As a result maintainers interacting with such entities
From: Thomas Huth
The FreeBSD job started to fail since the 14-1 image disappeared
from the cloud. Update the job to v14.2 to fix it.
Message-ID: <20250211120817.35050-1-th...@redhat.com>
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
(cherry picked from commit 66a1b4991c32e370a4e0
From: Peter Krempa
Commit 7452162adec25c10 introduced 'qom-path' argument to BLOCK_IO_ERROR
event but when the event is instantiated in 'send_qmp_error_event()' the
arguments for 'device' and 'qom_path' in
qapi_event_send_block_io_error() were reversed :
Generated code for sending event:
void
From: Fabiano Rosas
ASAN detected a leak when running the ahci-test
/ahci/io/dma/lba28/retry:
Direct leak of 35 byte(s) in 1 object(s) allocated from:
#0 in malloc
#1 in __vasprintf_internal
#2 in vasprintf
#3 in g_vasprintf
#4 in g_strdup_vprintf
#5 in g_strdup_printf
From: Mikael Szreder
A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.
Cc: qemu-sta...@nongnu.org
Fixes: 0bba7572d40d ("target/sparc: Perform
From: Fabiano Rosas
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix by aligning the sta
From: Michael Roth
The current logic scans qemu.git/subprojects/ from *.wrap files to
determine whether or not to include the associated directories in the
release tarballs. However, the script assumes that it is being run from
the top-level of the source directory, which may not always be the ca
From: Zhenzhong Duan
When iommufd_cdev_ram_block_discard_disable() fails for whatever reason,
errp should be set or else SIGSEV is triggered in vfio_realize() when
error_prepend() is called.
By this chance, use the same error message for both legacy and iommufd
backend.
Fixes: 5ee3dc7af785 ("vf
From: Laurent Vivier
Add VHOST_USER_PROTOCOL_F_SHARED_OBJECT and
VHOST_USER_PROTOCOL_F_DEVICE_STATE protocol feature maps to
the virtio introspection.
Cc: jonah.pal...@oracle.com
Fixes: 160947666276 ("vhost-user: add shared_object msg")
Cc: aest...@redhat.com
Fixes: cda83adc62b6 ("vhost-user: In
The following patches are queued for QEMU stable v9.2.2:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-02-23, and the release is planned for 2025-02-24:
https://wiki.qemu.org/Planning/9.2
This is a short-cycle release to fix issues with the uploaded 9.2.1
t
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/chardev.rs | 8 ++--
rust/qemu-api/src/qdev.rs | 1 +
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/rust/qemu-api/src/bindings.rs b/rust/qemu-api/src/bindings.rs
index 26cc8de0cf2..
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/irq.rs| 15 ++-
rust/qemu-api/src/sysbus.rs | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/rust/qemu-api/src/irq.rs b/rust/qemu-api/src/irq.rs
index d1c9dc96eff..aec2825b2f9 100644
--- a/rust/qemu-api/src/
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/hpet.rs | 2 +-
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/sysbus.rs| 25 ++---
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src
Inspired by the same-named type in Linux. This type provides the compiler
with a correct view of what goes on with FFI types. In addition, it
separates the glue code from the bindgen-generated code, allowing
traits such as Send, Sync or Zeroable to be specified independently
for C and Rust struct
Signed-off-by: Paolo Bonzini
---
meson.build| 7 ---
rust/qemu-api/src/timer.rs | 24 +---
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/meson.build b/meson.build
index 8ed10b6624e..16c76c493f3 100644
--- a/meson.build
+++ b/meson.build
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 3 ---
rust/qemu-api/src/memory.rs | 2 +-
rust/qemu-api/src/qdev.rs | 6 +++---
rust/qemu-api/src/qom.rs | 35 ++-
4 files changed, 26 insertions(+), 20 deletions(-)
diff --git a/rust/
On 21/2/25 17:01, Alex Bennée wrote:
While running the new GPU tests it was noted that the proprietary
nVidia driver barfed when run under the sanitiser:
2025-02-20 11:13:08,226: [11:13:07.782] Output 'headless' attempts
EOTF mode SDR and colorimetry mode default.
2025-02-20 11:13:08,22
Send and Sync are now implemented on the opaque wrappers. Remove them
from the bindings module, unless the structs are pure data containers
and/or have no C functions defined on them.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 8 ++--
1 file changed, 2 insertions(+), 6
Outside the qemu_api crate, orphan rules make the usage of ClassInitImpl
unwieldy. Now that it is optional, do not use it.
For PL011Class, this makes it easier to provide a PL011Impl trait similar
to the ones in the qemu_api crate. The device id consts are moved there.
Signed-off-by: Paolo Bonz
The only function, right now, is to ensure that anything with a
SysBusDeviceClass class is a SysBusDevice.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 5 -
rust/hw/timer/hpet/src/hpet.rs | 4 +++-
rust/qemu-api/src/sysbus.rs | 8 +---
3 files changed, 12 in
Complete the conversion from the ClassInitImpl trait to class_init() methods.
This will provide more freedom to split the qemu_api crate in separate parts.
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 6 +-
rust/hw/timer/hpet/src/hpet.rs | 4 +-
rust/qemu-api/src/qde
Check that the right bounds are provided to the qom_isa! macro
whenever the class is defined to implement a certain class.
This removes the need to add IsA<> bounds together with the
*Impl trait bounds.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/qdev.rs | 2 +-
rust/qemu-api/src/qom.rs
This series is logically split in two parts. The first one is more
strictly tied to the objective of splitting qemu_api into multiple crates,
as it breaks the QOM bindings free of the constraints imposed by Rust
orphan rules. The second one instead completes another task that was on
my todo list,
On Fri, 21 Feb 2025 at 14:02, Wei Liu wrote:
>
> Hi,
>
> Microsoft's Linux Systems Group developed a Linux driver for the Microsoft
> Hypervisor (MSHV for short). The driver is being upstreamed. The first
> supported VMM is Cloud Hypervisor. QEMU will be the second supported
> VMM.
>
> The plan is
This patch originates from the last comment of the following review:
https://lore.kernel.org/all/2df9ae98-afb8-4647-be80-12540a1c4...@ventanamicro.com/
We call probe_pages to probe the memory before doing a memory operations or
probe_access_flags to do the same while also obtaining probe flags an
This commit expands the probe_pages helper function in
target/riscv/vector_helper.c to handle also the cases in which we need access to
the flags raised while probing the memory and the host address.
This is done in order to provide a unified interface to probe_access and
probe_access_flags.
The ne
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_decode.c | 3 ---
target/i386/hvf/x86_emu.c| 4
2 files changed, 7 deletions(-)
diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c
index 31285952ad..ffece4773b 100644
--- a/target/i386/hvf/x86_decode.c
+++ b/target/i38
On 21/2/25 16:19, Peter Maydell wrote:
On Fri, 21 Feb 2025 at 14:41, Philippe Mathieu-Daudé wrote:
On 17/2/25 13:50, Peter Maydell wrote:
(1) floatx80 behaviours
Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
use in the xsrqpxp round-to-80-bit-precision operation, and
The following organisations appear on the US sanctions list:
Yadro: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=41125
ISPRAS: https://sanctionssearch.ofac.treas.gov/Details.aspx?id=50890
As a result maintainers interacting with such entities would face
legal risk in a number of jur
Fault-only-first loads in the RISC-V vector extension need to update
the vl with the element index that causes an exception.
In order to ensure this the emulation of this instruction used to probe the
memory covered by the load operation with a loop that iterated over each element
so that when a fl
While running the new GPU tests it was noted that the proprietary
nVidia driver barfed when run under the sanitiser:
2025-02-20 11:13:08,226: [11:13:07.782] Output 'headless' attempts
EOTF mode SDR and colorimetry mode default.
2025-02-20 11:13:08,227: [11:13:07.784] Output 'headless' using
Add support for reporting Hostwide state counters for nested KVM pseries
guests running with 'cap-nested-papr' on Qemu-TCG acting as
L0-hypervisor. The Hostwide state counters are statistics about state that
L0-hypervisor maintains for the L2-guests and represent the state of all
L2-guests, not jus
This version of the patch addresses the comments from the following review:
https://lore.kernel.org/all/2df9ae98-afb8-4647-be80-12540a1c4...@ventanamicro.com/
Previous version:
- v1:
https://lore.kernel.org/all/20250129144435.82451-1-paolo.sav...@embecosm.com/
The new version:
- fixes the "br
Ok, this one definitely caught my eye. :)
On 2/17/25 00:09, Richard Henderson wrote:
+tcg_gen_add_i32(t0, a, b);
+tcg_gen_setcond_i32(TCG_COND_LTU, t1, t0, a);
Compare against b instead? If there's an immediate (which could even be
zero) it is there.
+tcg_gen_add_i32
Expose ziccrse, zabha and svvptc.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 23ce779359..471fd554b3 100644
--- a/target/riscv
Update headers to retrieve the latest KVM caps for RISC-V.
Signed-off-by: Daniel Henrique Barboza
---
include/standard-headers/linux/ethtool.h | 4 +
include/standard-headers/linux/fuse.h | 76 ++-
.../linux/input-event-codes.h | 1 +
include/standa
Hi,
In this series we made changes in the commit msg in patch 2 to make it
less ambiguious what the KVM driver will do with ziccrse.
No other changes made. Patches based on alistair/riscv_to_apply.next.
Changes from v2:
- patch 2:
- reworded commit message
- v2 link:
https://lore.kernel.org/
At this moment ziccrse is a TCG always enabled named feature for
priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
the KVM driver turn ziccrse off if the extension isn't available in the
host, and we'll need an ext_ziccrse flag in the CPU state for that.
Create an exclusive
Thomas Huth writes:
> On 21/02/2025 15.06, Peter Maydell wrote:
>> On my local machine, for a debug build, sbsaref_alpine takes
>> nearly 900s:
>> $ (cd build/x86 && ./pyvenv/bin/meson test --setup thorough --suite
>> func-thorough func-aarch64-aarch64_sbsaref_alpine
>> )
>> 1/1 qemu:func-thoroug
On Fri, Feb 14, 2025 at 1:52 PM Clément Chigot wrote:
>
> Hi Alistair,
>
> I've an issue following this patch. When the system is reset (e.g
> using HTIF syscalls), the fifo might not be empty and thus some
> characters are lost.
> I discovered it on a Windows host. But by extending
> "TX_INTERRUP
On 2/20/25 06:45, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v3 01/28] hw/intc/aspeed: Support setting different
memory and register size
Hello Jamin,
On 2/13/25 04:35, Jamin Lin wrote:
According to the AST2700 datasheet, the INTC(CPU DIE) controller has
16KB
(0x4000) of register space,
On Fri, 21 Feb 2025 at 14:42, Philippe Mathieu-Daudé wrote:
>
> On 17/2/25 13:50, Peter Maydell wrote:
> > Currently we hardcode at compile time whether the floatx80 default
> > Infinity value has the explicit integer bit set or not (x86 sets it;
> > m68k does not). To be able to compile softfloa
On Fri, Feb 21, 2025 at 11:18:33AM -0300, Daniel Henrique Barboza wrote:
> At this moment ziccrse is a TCG always enabled named feature for
> priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
> the KVM driver update ziccrse as well, turning it on/off depending on
> host setti
Em Fri, 21 Feb 2025 13:23:06 +0100
Mauro Carvalho Chehab escreveu:
> Em Fri, 21 Feb 2025 10:21:27 +
> Jonathan Cameron escreveu:
>
> > On Fri, 21 Feb 2025 07:38:23 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Em Mon, 3 Feb 2025 16:22:36 +0100
> > > Igor Mammedov escreveu:
> > >
On 17/2/25 13:50, Peter Maydell wrote:
Currently we hardcode at compile time whether the floatx80 default
Infinity value has the explicit integer bit set or not (x86 sets it;
m68k does not). To be able to compile softfloat once for all targets
we'd like to move this setting to runtime.
Define a
--- a/DSDT.dsl2025-01-28 09:38:15.155347858 +0100
+++ b/DSDT.dsl2025-01-28 09:39:01.684836954 +0100
@@ -9,9 +9,9 @@
*
* Original Table Header:
* Signature"DSDT"
- * Length 0x1516 (5398)
+ * Length 0x1542 (5442)
* Revision
The MMIO region size required to support virtualized environments with
large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO
(currentl
On 21/2/25 09:36, Wei Liu wrote:
The prefix x68 is wrong. Change it to x86.
Signed-off-by: Wei Liu
---
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86.c | 4 ++--
target/i386/hvf/x86.h | 8
target/i386/hvf/x86_descr.c | 8
target/i386/hvf/x86_desc
The current code is actually dependent on having just one error
structure with a single source, as any change there would cause
migration issues.
As the number of sources should be arch-dependent, as it will depend on
what kind of notifications will exist, and how many errors can be
reported at th
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the ack.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table and the type of the
HEST error block st
On 17/2/25 13:50, Peter Maydell wrote:
(1) floatx80 behaviours
Two QEMU targets implement floatx80: x86 and m68k. (PPC also has one
use in the xsrqpxp round-to-80-bit-precision operation, and the
Linux-user NWFPE emulation nominally supports it, but these are
minor.) x86 and m68k disagree about
Use the newly defined emul_ops. This allows the module to be reused
by other accelerator in the future.
No functional change intended.
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_decode.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/target/i386/hvf
No functional change.
Signed-off-by: Wei Liu
---
target/i386/hvf/x86_emu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index d0a8e221ea..f1244640e6 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hv
Now that the ghes preparation patches were merged, let's add support
for error injection.
On this series, the first 6 patches chang to the math used to calculate offsets
at HEST
table and hardware_error firmware file, together with its migration code.
Migration tested
with both latest QEMU relea
Add a new ags flag to change the way HEST offsets are calculated.
Currently, offsets needed to store ACPI HEST offsets and read ack
are calculated based on a previous knowledge from the logic
which creates the HEST table.
Such logic is not generic, not allowing to easily add more HEST
entries nor
Store HEST table address at GPA, placing its the start of the table at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 22 --
include/hw/acpi/ghes.h | 7 ++-
2 files chang
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
Using the QMP GHESv2 API requires preparing a raw data array
containing a CPER record.
Add a helper script with subcommands to prepare such data.
Currently, only ARM Processor error CPER record is supported, by
using:
$ ghes_inject.py arm
which produces those warnings on Linux:
[ 705.0
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 5 -
include/hw/acpi/ghes.h | 3 +++
2 files
The GHES migration logic should now support HEST table location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/gener
Creates a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU a
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 10.0 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
Instead of having a function to check if ACPI is enabled
(acpi_ghes_present), change its logic to be more generic,
returing a pointed to AcpiGhesState.
Such change allows cleanup the ghes GED state code, avoiding
to read it multiple times, and simplifying the code.
Signed-off-by: Mauro Carvalho C
On 21/02/2025 15.06, Peter Maydell wrote:
On my local machine, for a debug build, sbsaref_alpine takes
nearly 900s:
$ (cd build/x86 && ./pyvenv/bin/meson test --setup thorough --suite
func-thorough func-aarch64-aarch64_sbsaref_alpine
)
1/1 qemu:func-thorough+func-aarch64-thorough+thorough /
f
On 2/21/25 1:49 PM, Eric Auger wrote:
> Hi Zhenzhong,
>
>
> On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>> When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
>> is passed to host to construct nested page table. We need to check
>> compatibility of some critical IOMMU capabi
Expose ziccrse, zabha and svvptc.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 23ce779359..471fd554b3 100644
--- a/target/riscv
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