Re: [PATCH v3 057/162] tcg: Merge INDEX_op_sar_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 ++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 12 docs/devel/t

Re: [PATCH v3 055/162] tcg: Merge INDEX_op_shr_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 +++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 11 +++ docs/dev

Re: [PATCH v3 053/162] tcg: Merge INDEX_op_shl_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 13 - docs/devel/tc

Re: [PATCH v3 051/162] tcg: Merge INDEX_op_remu_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 5 + tcg/optimize.c | 9 + tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst

Re: [PATCH v3 047/162] tcg: Merge INDEX_op_divu2_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.rst | 10 ++ 4 files changed, 21 insertions(+), 14 deletions(-)

Re: [PATCH v3 043/162] tcg: Merge INDEX_op_divu_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 9 + tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel

Re: [PATCH v3 039/162] tcg: Merge INDEX_op_mulsh_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 8 tcg/tcg.c | 14 -- docs/devel/tcg-ops.rst | 2 +- 5 files changed, 15 in

Re: [PATCH v3 035/162] tcg: Merge INDEX_op_mul_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 4 ++-- tcg/tcg-op.c | 12 ++-- tcg/tcg.c| 14 ++ tcg/tci.c| 5 ++--- docs/devel/

Re: [PATCH 3/5] target/rx: Reset the CPU at qemu reset time

+Peter/Igor On 15/2/25 03:16, Keith Packard via wrote: This ensure that the CPU gets reset every time QEMU resets. Signed-off-by: Keith Packard --- target/rx/cpu.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 37a6fdd

Re: [PATCH 09/11] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page

On 12/2/25 19:21, Richard Henderson wrote: On 2/11/25 23:22, Philippe Mathieu-Daudé wrote: On 5/2/25 05:03, Richard Henderson wrote: The declarations use vaddr for size. Which seems dubious, since TARGET_PAGE_SIZE is int IIUC. This parameter must handle guest huge pages.  Most often this is

Re: [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before IOMMU reset

Hi Zhenzhong, On 2/17/25 4:02 AM, Duan, Zhenzhong wrote: > Hi Eric, > >> -Original Message- >> From: Eric Auger >> Subject: [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before >> IOMMU reset >> >> From: Peter Xu >> >> No bug report for this, but logically tearing down of ex

Re: [PATCH v9 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)

Hi, On 16/2/25 23:11, dan tan wrote: Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Signed-off-by: dan tan --- v3: - moved variable tis_addr from

Re: [PATCH] hw/i386/amd_iommu: Don't leak memory in amdvi_update_iotlb()

On 31/7/24 19:00, Peter Maydell wrote: In amdvi_update_iotlb() we will only put a new entry in the hash table if to_cache.perm is not IOMMU_NONE. However we allocate the memory for the new AMDVIIOTLBEntry and for the hash table key regardless. This means that in the IOMMU_NONE case we will leak

[PATCH 7/7] hw/ppc: Implement MPIPL in PowerNV

Linux expect a "ibm,opal/dump" node to know whether MPIPL (aka fadump) is supported on the hardware. Export the "ibm,opal/dump" node in QEMU's device tree for Linux to know that PowerNV supports MPIPL. With the commit, kernel boots thinking fadump is supported, and reserves memory regions for fad

[PATCH 1/7] hw/ppc: Log S0/S1 Interrupt triggers by OPAL

During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger MPIPL. Currently QEMU treats it as "Unimplemented", handle the interrupts by just logging that the interrupt happened. Signed-off-by: Aditya Gupta --- hw/ppc/pnv_sbe.c | 13 + 1 file changed, 13 insertions(+)

[PATCH 6/7] hw/ppc: [WIP] Add Processor Dump Area offsets in Pnv SBE

Add offsets for the processor state captured during MPIPL dump. This is incomplete. And might be implemented in future if the effort to implement MPIPL is resumed again. Signed-off-by: Aditya Gupta --- hw/ppc/pnv_sbe.c | 27 +++ 1 file changed, 27 insertions(+) diff --g

[PATCH 5/7] hw/ppc: Preserve Memory Regions as per MDST/MDDT tables

When MPIPL is used, OPAL/Linux registers memory regions to be preserved on a Memory-Preserving boot ('crashkernel boot'). The regions are added to two tables: MDST and MDDT (source and destination tables) The MDST contains the start address of the region, and size of region The MDDT contains the

[PATCH 4/7] hw/ppc: Add MDST/MDDT/MDRT table structures and offsets

Add the MDST, MDDT, MDRT tables offsets and structures as per current skiboot upstream: commit bc7b85db1e7e ("opal-ci: Remove centos7") These structures will be later populated when preserving memory regions for MPIPL Signed-off-by: Aditya Gupta --- hw/ppc/pnv_sbe.c | 113 +

[PATCH 2/7] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset

SBE's implementation of S0 seems to be basically "stop all clocks" and then "host reset" Nearest equivalent to the stop clocks seems to be 'pause_all_vcpus' in QEMU, Then reset the host, which is 'SHUTDOWN_CAUSE_GUEST_RESET' in QEMU. Implement the S0 interrupt as pause_vcpus + guest_reset See '

[PATCH 3/7] hw/ppc: Handle stash command in PowerNV SBE

Earlier since the SBE_CMD_STASH_MPIPL_CONFIG command was not handled, so skiboot used to not get any response from SBE: [ 106.350742821,3] SBE: Message timeout [chip id = 0], cmd = d7, subcmd = 7 [ 106.352067746,3] SBE: Failed to send stash MPIPL config [chip id = 0x0, rc = 254] Fix th

[PATCH 0/7] Implement MPIPL for PowerNV

Overview = Implemented MPIPL (Memory Preserving IPL, aka fadump) on PowerNV machine in QEMU. Note: It's okay if this isn't merged as there might be less users. Sending for archieval purpose, as the patches can be referred for how fadump/mpipl can be implemented in baremetal/PowerNV/any ot

[PATCH 3/6] hw/ppc: Preserve memory regions registered for fadump

While the first kernel boots, it registers memory regions for fadump such as: * CPU state data (has to be populated by the platform) * HPTE state data (has to be populated by the platform) * Real Mode Regions (platform should copy it to requested destination addresses) * OS d

[PATCH 4/6] hw/ppc: Implement saving CPU state in Fadump

Kernel expects CPU states/register states in the format mentioned in "Register Save Area" in PAPR. The platform (in our case, QEMU) saves each CPU register in the form of an array of "register entries", the start and end of this array is signified by "CPUSTRT" and "CPUEND" register entries respect

[PATCH 1/6] hw/ppc: Implement skeleton code for fadump in PSeries

Implement the handler for "ibm,configure-kernel-dump" rtas call in QEMU. Currently the handler just does basic checks and handles register/unregister/invalidate requests from kernel. Fadump will be enabled in a later patch. Signed-off-by: Aditya Gupta --- hw/ppc/spapr_rtas.c| 99 ++

[PATCH 0/6] Implement Firmware Assisted Dump for PSeries

Overview = Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU. Fadump is an alternative dump mechanism to kdump, in which we the firmware does a memory preserving boot, and the second/crashkernel is booted fresh like a normal system reset, instead of the crashed kernel

[PATCH 6/6] hw/ppc: Enable Fadump for PSeries

With all support in place, enable fadump by exporting the "ibm,configure-kernel-dump" RTAS call in the device tree. Presence of "ibm,configure-kernel-dump" tells the kernel that the platform (QEMU) supports fadump. Pass "fadump=on" to enable Linux to use firmware assisted dump. Logs of a linux b

[PATCH 2/6] hw/ppc: Trigger Fadump boot if fadump is registered

According to PAPR: R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or on a system reset without an ibm,nmi-interlock RTAS call, if the platform has a dump structure registered through the ibm,configure-kernel-dump call, the platform must process each registere

[PATCH 5/6] hw/ppc: Pass device tree properties for Fadump

Platform (ie. QEMU) is expected to pass few device tree properties for details for fadump: * "ibm,configure-kernel-dump": RTAS call for fadump * "ibm,configure-kernel-dump-sizes": Space required to store dump data for firmware provided dump sections (ie. CPU & HPTE regions) * "ibm,config

Re: [PATCH v2] hpet: do not overwrite properties on post_load

> @@ -347,14 +330,13 @@ static const VMStateDescription vmstate_hpet = { > .version_id = 2, > .minimum_version_id = 1, > .pre_save = hpet_pre_save, > -.pre_load = hpet_pre_load, > .post_load = hpet_post_load, > .fields = (const VMStateField[]) { > VMSTATE_UINT6

Re: [PATCH v3 06/19] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL

On Thu, Feb 13, 2025 at 7:37 AM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 2 +- > target/riscv/cpu.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-)

Re: [PATCH v7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

On Wed, Feb 12, 2025 at 8:20 PM Rajnesh Kanwal wrote: > > CTR entries are accessed using ctrsource, ctrtarget and ctrdata > registers using smcsrind/sscsrind extension. This commits extends > the csrind extension to support CTR registers. > > ctrsource is accessible through xireg CSR, ctrtarget is

Re: [PATCH v2] target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled

On Fri, Feb 14, 2025 at 12:57 AM Clément Léger wrote: > > As raised by Richard Henderson, these warnings are displayed in user > only as well. Since they aren't really useful for the end-user, remove > them and add a "TODO" note in the leading comments. > > Signed-off-by: Clément Léger Thanks!

Re: [PATCH v3 07/19] target/riscv: Convert misa_mxl_max using GLib macros

On Thu, Feb 13, 2025 at 7:34 AM Philippe Mathieu-Daudé wrote: > > Use GLib conversion macros to pass misa_mxl_max as > riscv_cpu_class_init() class data. > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cp

Re: [PATCH v2] target/sparc: Fix gdbstub incorrectly handling registers f32-f62

This patch should be applicable to the stable releases as well, as the issue has existed since a while back. Best regards Mikael Szreder On February 15, 2025 8:58:09 PM GMT+01:00, Richard Henderson wrote: >On 2/13/25 23:03, Mikael Szreder wrote: >> The gdbstub implementation for the Sparc arch

[PATCH 4/8] target/loongarch: Add paravirt ipi feature detection

Paravirt ipi feature is OnOffAuto type, feature detection is added to check whether it is supported by KVM host. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 2 ++ target/loongarch/kvm/kvm.c | 36 +++- 2 files changed, 37 insertions(+), 1 deletion(-)

[PATCH 6/8] target/loongarch: Add CPU property for kvm steal time feature

Property kvm-steal-time is added for kvm steal time feature, it is specially for kvm mode. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 1 + target/loongarch/kvm/kvm.c | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/

[PATCH 1/8] target/loongarch: Add post init function for kvm mode

Some features such as LBT and PMU are implemented in kvm mode, With para-virt features in future, post init function is added for kvm mode, so that property for these features will be created in kvm post init function. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 2 +- targ

[PATCH 0/8] target/loongarch: Add paravirt feature property and enabling

Paravirt features is enabled by default if it is supported by KVM host, such as KVM_FEATURE_IPI and KVM_FEATURE_STEAL_TIME, however paravirt feature KVM_FEATURE_VIRT_EXTIOI is controlled from qemu VMM rather KVM host. >From qemu VMM side, all paravirt features should be controlled. Here property o

[PATCH 2/8] target/loongarch: Mov kvm specified vcpu property to kvm directory

LBT and PMU feature is supported only in kvm mode, move property about these two features to function kvm_loongarch_cpu_post_init(). Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 40 ++ target/loongarch/kvm/kvm.c | 35 +++

[PATCH 8/8] target/loongarch: Add virtual extioi feature enabling

Feature virtual extioi is loongArch virt machine property rather than vCPU property in qemu side. However it is vCPU property in KVM kernel side, here add loongArch virt machine property checking and enable virt extioi feature when vCPU is created. Signed-off-by: Bibo Mao --- target/loongarch/kv

Re: [PATCH 0/4] target/arm: Improvement on memory error handling

On 2/14/25 10:59 PM, Mauro Carvalho Chehab wrote: Em Fri, 14 Feb 2025 14:16:31 +1000 Gavin Shan escreveu: Currently, there is only one CPER buffer (entry), meaning only one memory error can be reported. In extreme case, multiple memory errors can be raised on different vCPUs. For example, a si

[PATCH 3/8] target/loongarch: Add CPU property for paravirt ipi feature

Property kvm-pv-ipi is added to paravirt ipi feature, it is specially for kvm mode. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 1 + target/loongarch/kvm/kvm.c | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h i

[PATCH 7/8] target/loongarch: Add kvm steal time feature detection

Paravirt steal time feature is OnOffAuto type, feature detection is added to check whether it is supported on KVM host. Signed-off-by: Bibo Mao --- target/loongarch/cpu.h | 1 + target/loongarch/kvm/kvm.c | 20 2 files changed, 21 insertions(+) diff --git a/target/loon

[PATCH 5/8] target/loongarch: Add paravirt ipi feature enabling

The similiar with cpucfg register, paravirt ipi feature is set in function kvm_arch_put_registers(). Instead the paravirt feature can be enabled only once, it cannot be changed dynamically. Signed-off-by: Bibo Mao --- target/loongarch/kvm/kvm.c | 36 1 file c

Re: [PATCH 0/4] target/arm: Improvement on memory error handling

On 2/14/25 8:12 PM, Jonathan Cameron wrote: On Fri, 14 Feb 2025 14:16:31 +1000 Gavin Shan wrote: Currently, there is only one CPER buffer (entry), meaning only one memory error can be reported. In extreme case, multiple memory errors can be raised on different vCPUs. For example, a singile mem

RE: [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before IOMMU reset

Hi Eric, >-Original Message- >From: Eric Auger >Subject: [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before >IOMMU reset > >From: Peter Xu > >No bug report for this, but logically tearing down of existing address >space should happen before reset of IOMMU state / registers,

[PATCH 1/1] target/loongarch: fix 'make check-functional failed'

For LoongArch th min tlb_ps is 12(4KB), for TLB code, the tlb_ps may be 0,this may case UndefinedBehavior Add a check-tlb_ps fuction to check tlb_ps, when use csrwr insn to write CRMD PG=1, check the tlb_ps, and when use csrwr insn to write STLBPS, check the tlb_ps value. Signed-off-by: Song Gao

Re: hw/net/can: PCI MSI suport for SJA1000 based addon card Was: [PATCH] hw/net/can: ... to meson build.

Hello Deniz, On Saturday 15 of February 2025 14:30:58 Deniz Eren wrote: > I have implemented support for PCI MSI capability CANbus card support; > fully tested using QNX operating system guest image. How can I go about > contributing this to the main repo: > > https://github.com/Deniz-Eren/qemu/bl

Re: [PATCH 2/2] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64

On Sun, Feb 16, 2025 at 12:49 PM Richard Henderson wrote: > > These defines never should have been added as they were > never used. Only 32-bit hosts may have these opcodes and > they have them unconditionally. > > Signed-off-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- >

Re: [PATCH 0/4] target/arm: Improvement on memory error handling

On 2/14/25 7:53 PM, Jonathan Cameron wrote: On Fri, 14 Feb 2025 14:16:31 +1000 Gavin Shan wrote: Currently, there is only one CPER buffer (entry), meaning only one memory error can be reported. In extreme case, multiple memory errors can be raised on different vCPUs. For example, a singile mem

[PATCH v3 155/162] tcg: Convert st to TCGOutOpStore

Signed-off-by: Richard Henderson --- tcg/tcg.c| 37 ++ tcg/aarch64/tcg-target.c.inc | 52 +++--- tcg/arm/tcg-target.c.inc | 72 +-- tcg/i386/tcg-target.c.inc| 114 ++- tcg/loongarch64/tcg-ta

[PATCH v3 129/162] target/sh4: Use tcg_gen_addcio_i32 for addc

Signed-off-by: Richard Henderson --- target/sh4/translate.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 2ef48b1d17..e8029c0c7a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -694,14 +694,

[PATCH v3 074/162] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64}

All targets now provide negsetcond, so remove the conditional. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h

[PATCH v3 050/162] tcg: Convert remu to TCGOutOpBinary

For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/loongarch64/tcg-target-con-set.h | 1 - tcg/lo

[PATCH v3 099/162] tcg: Convert extrh_i64_i32 to TCGOutOpUnary

At the same time, make extrh_i64_i32 mandatory. This closes a hole in which move arguments could be cast between TCGv_i32 and TCGv_i64. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 7 +-- tcg/tcg.c| 5 +++-- tcg/aarch64/tcg-target.c.inc

[PATCH v3 120/162] tcg/i386: Remove support for add2/sub2

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 1 - tcg/i386/tcg-target-has.h | 8 tcg/i386/tcg-target.c.inc | 31 --- 3 files changed, 4 insertions(+), 36 deletions(-) diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-

[PATCH v3 125/162] target/microblaze: Use tcg_gen_addcio_i32

Use this in gen_addc and gen_rsubc, both of which need add with carry-in and carry-out. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c

[PATCH v3 092/162] tcg: Convert extract to TCGOutOpExtract

Signed-off-by: Richard Henderson --- tcg/tcg.c| 20 + tcg/aarch64/tcg-target.c.inc | 28 +++- tcg/arm/tcg-target.c.inc | 23 +- tcg/i386/tcg-target.c.inc| 77 +--- tcg/loongarch64/tcg-target.c.inc | 33

[PATCH v3 159/162] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}

Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two inputs or outputs are required. This simplifies the processing of i64/i128 depending on host word size. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 16 ++- tcg/optimize.c | 15 ++--

[PATCH v3 098/162] tcg: Convert extrl_i64_i32 to TCGOutOpUnary

Drop the cast from TCGv_i64 to TCGv_i32 in tcg_gen_extrl_i64_i32 an emit extrl_i64_i32 unconditionally. Move that special case to tcg_gen_code when we find out if the output is live or dead. In this way even hosts that canonicalize truncations can make use of a store directly from the 64-bit host

[PATCH v3 133/162] tcg/aarch64: Remove support for add2/sub2

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 1 - tcg/aarch64/tcg-target-has.h | 8 ++-- tcg/aarch64/tcg-target.c.inc | 75 3 files changed, 4 insertions(+), 80 deletions(-) diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/

[PATCH v3 158/162] tcg: Remove INDEX_op_qemu_st8_*

The i386 backend can now check TCGOP_FLAGS to select the correct set of constraints. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 tcg/aarch64/tcg-target-has.h | 1 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-con-str.h| 2 +- tcg/i386/t

[PATCH v3 140/162] tcg/s390x: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 + tcg/s390x/tcg-target.c.inc | 103 - 2 files changed, 92 insertions(+), 13 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index f5d3878070..0

[PATCH v3 085/162] tcg: Convert setcond2_i32 to TCGOutOpSetcond2

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 2 +- tcg/tcg.c | 19 ++ tcg/arm/tcg-target.c.inc | 25 ++-- tcg/i386/tcg-target.c.inc | 71 +-- tcg/mips/tcg-target.c.inc | 20 ++ tcg/pp

[PATCH v3 067/162] tcg: Convert muls2 to TCGOutOpMul2

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 -- tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-target-has.h| 2 -- tcg/ppc/tcg-target-has.h | 2 -- tcg/riscv

[PATCH v3 104/162] tcg: Merge INDEX_op_extract2_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 5 + tcg/optimize.c | 10 +- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.rst | 4 ++-- target/i386/tcg/emit.c.inc | 12 +--- 6 f

[PATCH v3 097/162] tcg: Convert extu_i32_i64 to TCGOutOpUnary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 15 --- tcg/aarch64/tcg-target.c.inc | 2 -- tcg/i386/tcg-target.c.inc| 2 -- tcg/loongarch64/tcg-target.c.inc | 2 -- tcg/mips/tcg-target.c.inc| 2 -- tcg/ppc/tcg-target.c.inc | 2

[PATCH v3 145/162] tcg/sparc64: Remove support for add2/sub2

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target-con-set.h | 6 +- tcg/sparc64/tcg-target-has.h | 8 +- tcg/sparc64/tcg-target.c.inc | 169 +++ 3 files changed, 19 insertions(+), 164 deletions(-) diff --git a/tcg/sparc64/tcg-target-con-set.h b/t

[PATCH v3 148/162] tcg: Remove add2/sub2 opcodes

All uses have been replaced by add/sub carry opcodes. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 5 -- tcg/aarch64/tcg-target-has.h | 5 -- tcg/arm/tcg-target-has.h | 4 -- tcg/i386/tcg-target-has.h| 5 -- tcg/loongarch64/tcg-target-has.h | 4

[PATCH v3 100/162] tcg: Convert deposit to TCGOutOpDeposit

Signed-off-by: Richard Henderson --- tcg/tcg.c| 33 ++ tcg/tci.c| 8 ++-- tcg/aarch64/tcg-target.c.inc | 30 + tcg/arm/tcg-target.c.inc | 29 ++-- tcg/i386/tcg-target.c.inc| 76 ---

[PATCH v3 049/162] tcg: Merge INDEX_op_rem_{i32,i64}

Rename to INDEX_op_rems to emphasize signed inputs, and mirroring INDEX_op_remu_*. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 +++- tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c

[PATCH v3 045/162] tcg: Merge INDEX_op_div2_{i32,i64}

Rename to INDEX_op_divs2 to emphasize signed inputs, and mirroring INDEX_op_divu2_*. Document the opcode. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.rst | 9 +

[PATCH v3 113/162] tcg: Add TCGOutOp structures for add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/tcg.c| 61 +++- tcg/aarch64/tcg-target.c.inc | 34 ++ tcg/arm/tcg-target.c.inc | 34 ++ tcg/i386/tcg-target.c.inc| 34 ++ tcg/loongarch6

[PATCH v3 042/162] tcg: Convert divu to TCGOutOpBinary

For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 -- tcg/arm/tcg-target-has.h | 1 - tcg/loongarch64/tcg-target-has.h | 2 -- tcg/mips/tcg-targ

[PATCH v3 083/162] tcg/ppc: Expand arguments to tcg_out_cmp2

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 +++-- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 1782d05290..669c5eae4a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.

[PATCH v3 144/162] tcg/sparc64: Implement add/sub carry opcodes

Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target-con-set.h | 3 + tcg/sparc64/tcg-target.c.inc | 244 ++- 2 files changed, 239 insertions(+), 8 deletions(-) diff --git a/tcg/sparc64/tcg-target-con-set.h b/tcg/sparc64/tcg-target-con-set.h index 8cec396

[PATCH v3 110/162] tcg: Move i into each for loop in liveness_pass_1

Use per-loop variables instead of one 'i' for the function. Signed-off-by: Richard Henderson --- tcg/tcg.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index c54fe90309..74911962a4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3

[PATCH v3 152/162] tcg: Assign TCGOP_TYPE in liveness_pass_2

Here we cannot rely on the default copied from tcg_op_insert_{after,before}, because the relevant op could be typeless, such as INDEX_op_call. Fixes: ... Signed-off-by: Richard Henderson --- tcg/tcg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index c66a262259..

[PATCH v3 029/162] tcg: Merge INDEX_op_sub_{i32,i64}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 4 ++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 10 +++--- tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst | 2 +- tcg

[PATCH v3 084/162] tcg: Convert brcond2_i32 to TCGOutOpBrcond2

Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 2 +- tcg/tcg.c | 30 + tcg/arm/tcg-target.c.inc | 20 +++ tcg/i386/tcg-target.c.inc | 62 ++- tcg/mips/tcg-target.c.inc | 19 ++-

[PATCH v3 130/162] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bfe63649db..392b51196a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -395,8 +395,

[PATCH v3 139/162] tcg/s390: Add TCG_CT_CONST_N32

We were using S32 | U32 for add2/sub2. But the ALGFI and SLGFI insns that implement this both have uint32_t immediates. This makes the composite range balanced and enables use of -0x ... -0x8001. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 +- tcg/s390x/t

[PATCH v3 106/162] tcg: Expand fallback sub2 with 32-bit operations

No need to expand to i64 to perform the subtract. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8b1356c526..127338b994 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1123

[PATCH v3 082/162] tcg/arm: Expand arguments to tcg_out_cmp2

Pass explicit arguments instead of arrays. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index a5c1325805..993564d424 100644 --- a/tcg/arm/t

[PATCH v3 118/162] tcg/i386: Honor carry_live in tcg_out_movi

Do not clobber flags if they're live. Required in order to perform register allocation on add/sub carry opcodes. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.i

[PATCH v3 141/162] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 2b31ea1c3e..36293d0f42 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/t

Re: [PATCH V1 16/26] vfio: return mr from vfio_get_xlat_addr

On Tue, Feb 04, 2025 at 12:42:20PM -0500, Steven Sistare wrote: > !---| > CAUTION: External Email > > |---! > > On 2/4/2025 10:47 AM, Cédric Le Goater wrote: > > + Joh

[PATCH v3 076/162] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}`

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 6 ++ target/sh4/translate.c | 6 +++--- tcg/optimize.c | 32 tcg/tcg-op.c | 8 tcg/tcg.c| 30 ++

[PATCH v3 057/162] tcg: Merge INDEX_op_sar_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 ++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 12 docs/devel/tcg-ops.rst | 4 ++-- tcg/tci/tcg-target.c.inc |

[PATCH v3 096/162] tcg: Convert ext_i32_i64 to TCGOutOpUnary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 22 +++--- tcg/aarch64/tcg-target.c.inc | 2 -- tcg/i386/tcg-target.c.inc| 2 -- tcg/loongarch64/tcg-target.c.inc | 2 -- tcg/mips/tcg-target.c.inc| 2 -- tcg/ppc/tcg-target.c.inc

[PATCH v3 127/162] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF

Signed-off-by: Richard Henderson --- target/ppc/translate.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 80638ab535..a31ff0c5b7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1717,11 +17

[PATCH v3 135/162] tcg/arm: Remove support for add2/sub2

We have replaced this with support for add/sub carry. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 2 -- tcg/arm/tcg-target-has.h | 4 +-- tcg/arm/tcg-target.c.inc | 47 3 files changed, 2 insertions(+), 51 deletions(-) diff

[PATCH v3 052/162] tcg: Convert shl to TCGOutOpBinary

Signed-off-by: Richard Henderson --- tcg/tcg.c| 6 ++-- tcg/aarch64/tcg-target.c.inc | 38 ++-- tcg/arm/tcg-target.c.inc | 25 + tcg/i386/tcg-target.c.inc| 60 +++- tcg/loongarch64/tcg-target.c.in

[PATCH v3 065/162] tcg: Convert ctpop to TCGOutOpUnary

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-has.h | 2 - tcg/arm/tcg-target-has.h | 1 - tcg/i386/tcg-target-has.h| 2 - tcg/loongarch64/tcg-target-has.h | 2 - tcg/mips/tcg-target-has.h| 2 - tcg/ppc/tcg-target-has.h | 2 - tcg/riscv/tcg-

[PATCH v3 128/162] target/s390x: Use tcg_gen_addcio_i64 for op_addc64

Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 00073c5560..a714f9c0c2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/tran

[PATCH v3 051/162] tcg: Merge INDEX_op_remu_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 5 + tcg/optimize.c | 9 + tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 7 files

[PATCH v3 062/162] tcg: Merge INDEX_op_clz_{i32,i64}

Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 22 ++ tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.

[PATCH v3 138/162] tcg/s390x: Honor carry_live in tcg_out_movi

Do not clobber flags if they're live. Required in order to perform register allocation on add/sub carry opcodes. LA and AGHI are the same size, so use LA unconditionally. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 35 +-- 1 file changed, 21

[PATCH v3 142/162] tcg/s390x: Remove support for add2/sub2

We have replaced this with support for add/sub carry. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-has.h | 8 +++--- tcg/s390x/tcg-target.c.inc | 50 -- 3 files changed, 4 insertions(+), 56 deletions(-)

[PATCH v3 150/162] tcg: Formalize tcg_out_br

Split these functions out from tcg_out_op. Call it directly from tcg_gen_code. Signed-off-by: Richard Henderson --- tcg/tcg.c| 4 tcg/aarch64/tcg-target.c.inc | 6 +- tcg/arm/tcg-target.c.inc | 8 +--- tcg/i386/tcg-target.c.inc| 8

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