Hello Jamin,
On 2/10/25 02:46, Jamin Lin wrote:
Hi Cedric, Andrew
-Original Message-
From: Jamin Lin
Sent: Thursday, February 6, 2025 5:53 PM
To: Cédric Le Goater ; Peter Maydell
; Steven Lee ; Troy
Lee ; Andrew Jeffery ;
Joel Stanley ; open list:ASPEED BMCs
; open list:All patches CC
On Thu, Feb 6, 2025 at 9:45 PM Rajnesh Kanwal wrote:
>
> On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis wrote:
> >
> > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal wrote:
> > >
> > > This series enables Control Transfer Records extension support on riscv
> > > platform. This extension is simil
On Mon Feb 3, 2025 at 8:09 PM AEST, Vaibhav Jain wrote:
> Add support for reporting Hostwide state counters for nested KVM pseries
I'd add a brief first paragraph that just describe the concept of
"hostwide state counters" without going into any spec.
Hostwide state counters are statistics abou
This is useful to hanlde InterruptSource slice and pass it to C
bindings.
Suggested-by: Paolo Bonzini
Signed-off-by: Zhao Liu
---
Changes since RFC:
* New commit.
Changes since Patch v1:
* Drop `pub(crate) use crate::bindings::IRQState`.
* Derefer `slice[0]` directly.
---
rust/qemu-api/src/
On Thu, Feb 6, 2025 at 7:59 PM Atish Patra wrote:
>
> Here are two small fixes around mhpmevent encoding and reset value.
> The first patch is picked from the platform specific event encoding
> series[1].
>
> [1]
> https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e...@ri
HPET device (Rust device) needs to define the bit type property.
Add a variant of define_property macro to define bit type property.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/qdev.rs | 12
1 file changed, 12 insertions(+)
diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/
The MemTxAttrs structure contains bitfield members, and bindgen is
unable to generate an equivalent macro definition for
MEMTXATTRS_UNSPECIFIED.
Therefore, manually define a global constant variable
MEMTXATTRS_UNSPECIFIED to support calls from Rust code.
Signed-off-by: Zhao Liu
---
Changes since
Add timer bindings to help handle idiomatic Rust callbacks.
Additionally, wrap QEMUClockType in ClockType binding to avoid unsafe
calls in device code.
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Use FnCall to support timer callback.
* Only add timer_init_full() binding. timer_new() is un
Wrap qdev_init_gpio_{in|out} as methods in DeviceMethods. And for
qdev_init_gpio_in, based on FnCall, it can support idiomatic Rust
callback without the need for C style wrapper.
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Use FnCall to support gpio in callback.
* Place gpio_{in|out} in De
Define HPETFwEntry structure with the same memory layout as
hpet_fw_entry in C.
Further, define the global hpet_cfg variable in Rust which is the
same as the C version. This hpet_cfg variable in Rust will replace
the C version one and allows both Rust code and C code to access it.
The Rust versio
Implement QOM & QAPI support for HPET device.
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Merge qdev.rs to hpet.rs.
* Apply memory and Resettable bindings.
* Consolidate inmutable &self and QOM casting.
* Prefer timer iterator over loop.
* Move init_mmio() and init_irq() to post_init().
Add HPET configuration in PC's Kconfig options, and select HPET device
(Rust version) if Rust is supported.
Signed-off-by: Zhao Liu
---
Changes since RFC:
* Fix rust hpet not being optional.
* Fix bios-tables-test missing rust hpet.
---
configs/devices/i386-softmmu/default.mak | 1 +
hw/i386/f
HPET device needs to access and update hpet_cfg variable, but now it is
defined in hw/i386/fw_cfg.c and Rust code can't access it.
Move hpet_cfg definition to hpet.c (and rename it to hpet_fw_cfg). This
allows Rust HPET device implements its own global hpet_fw_cfg variable,
and will further reduce
Hi folks,
This is Rust HPET normal patch series, and you can find the previous RFC
at [1].
This series is based on Paolo's rust-next branch at the commit
43c0ef3bfb3b ("rust: vmstate: remove redundant link targets") along with
another 2 more seperate patches:
*
https://lore.kernel.org/qemu-deve
Add the HPETTimer and HPETState (HPET timer block), along with their
basic methods and register definitions.
This is in preparation for supporting the QAPI interfaces.
Note, wrap all items in HPETState that may be changed in the callback
called by C code into the BqlCell/BqlRefCell.
Signed-off-b
Hi Cedric, Andrew
> -Original Message-
> From: Jamin Lin
> Sent: Thursday, February 6, 2025 5:53 PM
> To: Cédric Le Goater ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Jamin Lin ; Troy Lee
On Thu, Feb 6, 2025 at 7:59 PM Atish Patra wrote:
>
> As per the latest privilege specification v1.13[1], the sscofpmf
> only reserves first 8 bits of hpmeventX. Update the corresponding
> masks accordingly.
>
> [1]https://github.com/riscv/riscv-isa-manual/issues/1578
>
> Reviewed-by: Daniel Henri
Hi Philippe Mathieu-Daudé:
Hi,
On 8/2/25 08:50, Xianglai Li wrote:
When the KVM_REG_LOONGARCH_VCPU_RESET command word
is sent to the kernel through the kvm_set_one_reg interface,
the parameter source needs to be a legal address,
otherwise the kernel will return an error and the command word
wil
On Fri, Feb 7, 2025 at 1:35 AM Rob Bradford wrote:
>
> Add missing Sdtrig CSRs per the latest RISC-V Debug specification. (+ minor
> whitespace fix)
>
> Rob Bradford (2):
> disas/riscv: Fix minor whitespace issues
> disas/riscv: Add missing Sdtrig CSRs
Thanks!
Applied to riscv-to-apply.next
On Fri, Feb 7, 2025 at 1:35 AM Rob Bradford wrote:
>
> This reflects the latest frozen version of the RISC-V Debug
> specification (1.0.0-rc4) which includes the Sdtrig extension.
>
> Signed-off-by: Rob Bradford
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 4 +++-
> 1 file cha
On Fri, Feb 7, 2025 at 1:35 AM Rob Bradford wrote:
>
> Some extra spaces made into into the RISC-V opcode data table.
>
> Signed-off-by: Rob Bradford
Reviewed-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --g
On Mon, Feb 3, 2025 at 4:20 PM julia wrote:
>
> For instance, QEMUs newer than b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
> would silently treat this akin to an unmapped page (as required by the
> RISC-V spec, admittedly). However, not all hardware platforms do (e.g.
> CVA6) which leads to an appare
On Fri, Feb 7, 2025 at 4:29 AM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3d4bd157d2c..ed9da692030 100
On Sat, Feb 8, 2025 at 1:29 AM Rob Bradford wrote:
>
> The mvendorid/mimpid/marchid properties have the wrong amount of
> whitespace ahead of them.
>
> Signed-off-by: Rob Bradford
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 6 +++---
> 1 file changed, 3 inser
On Fri, Feb 7, 2025 at 4:22 AM Philippe Mathieu-Daudé wrote:
>
> Alistair's email is typed differently, so the get_maintainer.pl
> script add it twice :) Unify to reduce traffic.
>
> $ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u
> M: Alistair Francis
> M: Alistair Francis
Thes
On Fri, Feb 7, 2025 at 4:20 AM Philippe Mathieu-Daudé wrote:
>
> opentitan_machine_init() calls get_system_memory(),
> which is declared in "exec/address-spaces.h". Include
> it in order to avoid when refactoring unrelated headers:
>
> hw/riscv/opentitan.c:83:29: error: call to undeclared functi
On 9/2/25 23:20, Philippe Mathieu-Daudé wrote:
On 9/2/25 19:53, Philippe Mathieu-Daudé wrote:
On 9/2/25 19:44, Philippe Mathieu-Daudé wrote:
On 6/2/25 22:16, Richard Henderson wrote:
It would be nice if this were const, i.e.
.class_data = (void *) &(const RISCVCPUDef){
...
},
T
On 9/2/25 19:53, Philippe Mathieu-Daudé wrote:
On 9/2/25 19:44, Philippe Mathieu-Daudé wrote:
On 6/2/25 22:16, Richard Henderson wrote:
It would be nice if this were const, i.e.
.class_data = (void *) &(const RISCVCPUDef){
...
},
This will in fact create an anonymous object in .
On Wed, Feb 5, 2025 at 10:03 AM Mikael Szreder wrote:
>
> Fixed a mistake I made in the FqTOx instruction.
> Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions.
>
> Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
> Resolves: https://gitlab.com/qemu-project/qemu/-
On Sun, Feb 2, 2025 at 10:47 PM Richard Henderson
wrote:
>
> On 1/31/25 13:44, Artyom Tarasenko wrote:
> > fake access to
> > PCR Performance Control Register
> > and
> > PIC Performance Instrumentation Counter.
> >
> > Ignore writes in privileged mode, and return 0 on reads.
> >
> > This allows b
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko
---
target/sparc/insns.decode | 7 ++-
t
On 2/6/25 08:41, Akihiko Odaki wrote:
> On 2025/02/06 2:40, Dmitry Osipenko wrote:
>> On 2/3/25 08:31, Akihiko Odaki wrote:
>> ...
Requirements don't vary much. For example virglrenderer minigbm support
is mandatory for crosvm, while for QEMU it's not.
>>>
>>> Is that true? It seems that
Hi Dapeng,
On 2/7/25 1:52 AM, Mi, Dapeng wrote:
>
> On 11/21/2024 6:06 PM, Mi, Dapeng wrote:
>> On 11/8/2024 7:44 AM, dongli.zh...@oracle.com wrote:
>>> Hi Zhao,
>>>
>>>
>>> On 11/6/24 11:52 PM, Zhao Liu wrote:
(+Dapang & Zide)
Hi Dongli,
On Mon, Nov 04, 2024 at 01:40:17A
On Wed, 5 Feb 2025 at 22:02, Philippe Mathieu-Daudé
wrote:
> +Igor
>
> On 9/12/24 21:36, p...@philjordan.eu wrote:
> > From: Phil Dennis-Jordan
> >
> > Some VM state required for fully configuring vCPUs is only available
> > after all devices have been through their init phase. This extra
> > fu
On 2/8/25 18:53, Joelle van Dyne wrote:
According to the ARM manual, when SSE=1 the data item must be sign
extended.
Signed-off-by: Joelle van Dyne
---
target/arm/hvf/hvf.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 0afd9601
On Tue, 28 Jan 2025 at 14:55, Philippe Mathieu-Daudé
wrote:
> GICv3 isn't supported on aarch64/HVF, but GICv2 is.
Hmm. I'm still trying to get my head around this patch series and QTest in
general, but in my experience GICv3 works fine with HVF? (Device name
"arm-gicv3") Can you clarify what yo
On 9/2/25 19:44, Philippe Mathieu-Daudé wrote:
On 6/2/25 22:16, Richard Henderson wrote:
It would be nice if this were const, i.e.
.class_data = (void *) &(const RISCVCPUDef){
...
},
This will in fact create an anonymous object in .rodata.
We have other uses that do the extra ca
On 6/2/25 22:16, Richard Henderson wrote:
It would be nice if this were const, i.e.
.class_data = (void *) &(const RISCVCPUDef){
...
},
This will in fact create an anonymous object in .rodata.
We have other uses that do the extra casting away const,
e.g. armsse_variants in hw/arm
On Fri, 7 Feb 2025 at 22:07, Richard Henderson
wrote:
> Require a 64-bit host binary to spawn a 64-bit guest.
>
> For HVF this is trivially true because macOS 11 dropped
> support for 32-bit applications entirely.
Nit: it was 10.15.
> For NVMM, NetBSD only enables nvmm on x86_64:
>
> http://c
On 7/2/25 16:45, Igor Mammedov wrote:
On Tue, 28 Jan 2025 15:21:43 +0100
Philippe Mathieu-Daudé wrote:
Hi,
The goal of this series is to expose vCPUs in a stable state
to the accelerators, in particular the QDev 'REALIZED' step.
I'll take some of your patches (with Richard's feedback fixed)
On 8/2/25 08:06, Bibo Mao wrote:
This is code cleanup with loongArch virt machine type. One separate file
is added for fdt table building, also rename file acpi-build with
virt-acpi-build.
It is only cod movement and function rename. There is no any function
change.
Bibo Mao (3):
hw/loongarc
Hi,
On 8/2/25 08:50, Xianglai Li wrote:
When the KVM_REG_LOONGARCH_VCPU_RESET command word
is sent to the kernel through the kvm_set_one_reg interface,
the parameter source needs to be a legal address,
otherwise the kernel will return an error and the command word
will fail to be sent.
Signed-o
On 9/2/25 10:41, Michael Tokarev wrote:
09.02.2025 12:37, Michael Tokarev wrote:
25.01.2025 21:24, Philippe Mathieu-Daudé wrote:
- * You need not call an explicit deinit call. Simply make
+ * You need not call an explicit timer_deinit() call. Simply make
* sure it is not on a list with time
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by: Alex Bennée
Cc: Sergio Lopez Pascual
Sign
a port of an embeddable x86-mini disassembler to QEMU.
- https://github.com/michaeljclark/qemu/tree/x86-mini-v2
# x86-mini disassembler
the x86-mini library is a lightweight x86 encoder, decoder, and
disassembler that uses extensions to the Intel instruction set
metadata format to encode modern
add detailed information on the instruction opcode encoding
format for LEX/VEX/EVEX prefix, map and opcode encoding, the
operand encoding format, the field order encoding format and
notes on instruction synthesis for parameterized opcodes.
Signed-off-by: Michael Clark
---
docs/x86-metadata.txt |
the x86-mini metadata tablegen python script reads instruction
set metadata CSV files and translates them into tables used
by the disassembler. it generates the following tables:
- x86_opc_table that encodes prefix, map, and opcode
- x86_opr_table that encodes instruction operands
- x86_ord_table
Extend virtio-gpu documentation with a link to the Mesa VirGL
documentation.
Suggested-by: Akihiko Odaki
Reviewed-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gpu.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/system/devices/vi
Change virtio-gpu Venus link, pointing it at the Mesa Venus
documentation instead of the protocol. The Mesa doc provides more
information and also has a link to the protocol.
Suggested-by: Akihiko Odaki
Reviewed-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gp
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
using a new virtio-gpu-gl device option "drm_native_context=on".
Unlike Virgl and Venus contexts that operate on application API level,
DRM native contexts work on a kernel UAPI level. This lower level results
in a lightweig
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
From: Pierre-Eric Pelloux-Prayer
If EGL is used, we can rely on dmabuf to import textures without
doing copies.
To get this working on X11, we use the existing SDL hint:
SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX).
Reviewed-by: Akihiko Odaki
Acked-by: Michael S. Tsirki
Print out error messages when virgl fence creation fails to aid debugging
of the fence-related bugs.
Reviewed-by: Akihiko Odaki
Acked-by: Michael S. Tsirkin
Tested-by: Alex Bennée
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 13 -
1 file changed, 12 insertion
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
Contarary to Virgl and Venus contexts that mediates high level GFX APIs,
DRM native context [1] mediates lower level kernel driver UAPI, which
reflects in a less CPU overhead and less/simpler code needed to support it.
DRM contex
SDL API changes GL context to a newly created GL context, which differs
from other GL providers that don't switch context. Change SDL backend to
restore the original GL context. This allows Qemu's virtio-gpu to support
new virglrenderer async-fencing feature for Virgl contexts, otherwise
virglrende
On 2/3/25 09:04, Akihiko Odaki wrote:
> On 2025/02/03 8:21, Dmitry Osipenko wrote:
>> From: Alex Bennée
>>
>> This attempts to tidy up the VirtIO GPU documentation to make the list
>> of requirements clearer. There are still a lot of moving parts and the
>> distros have some catching up to do befo
Am 6. Februar 2025 13:49:38 UTC schrieb BALATON Zoltan :
>On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
>> On 6/2/25 13:49, BALATON Zoltan wrote:
>>> On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
> The interrupt enable registers are not re
Am 12. Januar 2025 13:08:03 UTC schrieb Bernhard Beschow :
>
>
>Am 31. Dezember 2024 11:59:50 UTC schrieb "Volker Rümelin"
>:
>>Windows only:
>>
>>The libSDL2 Windows message loop needs the libSDL2 Windows low
>>level keyboard hook procedure to grab the left and right Windows
>>keys correctly.
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extracting CONFIG_USB_CHIPIDEA fro
09.02.2025 12:37, Michael Tokarev wrote:
25.01.2025 21:24, Philippe Mathieu-Daudé wrote:
- * You need not call an explicit deinit call. Simply make
+ * You need not call an explicit timer_deinit() call. Simply make
* sure it is not on a list with timer_del.
Reworded this as "You need not c
25.01.2025 21:24, Philippe Mathieu-Daudé wrote:
- * You need not call an explicit deinit call. Simply make
+ * You need not call an explicit timer_deinit() call. Simply make
* sure it is not on a list with timer_del.
Reworded this as "You need not call timer_deinit() explicitly. Simply make
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