For instance, QEMUs newer than b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
would silently treat this akin to an unmapped page (as required by the
RISC-V spec, admittedly). However, not all hardware platforms do (e.g.
CVA6) which leads to an apparent QEMU bug.
Instead, log a guest error so that in fut
fY3jfRbpdO9l1l2wwDZ2l0AAZzaGE1MTIAAABTC3NzaC1lZDI1NTE5
QP6c2B82m4kq6h046Ou/LV6c9I/D/uUtUlivmbvR/lSdCWOiPIYnpK5HPtvhcgVYoQ
8X1k8kKjplch4iy6JnNgU=
-END SSH SIGNATURE-
julia (1):
target/riscv: log guest errors when reserved bits are set in PTEs
target/riscv/cpu_helper.
* Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrote:
> From: "Maciej S. Szmigiero"
>
> postcopy_ram_listen_thread() is a free running thread, so it needs to
> take BQL around function calls to migration methods requiring BQL.
>
> qemu_loadvm_state_main() needs BQL held since it ultimately c
On Sat, 1 Feb 2025, Bernhard Beschow wrote:
Am 1. Februar 2025 14:55:15 UTC schrieb Bernhard Beschow :
Am 30. Januar 2025 12:45:58 UTC schrieb BALATON Zoltan :
On Wed, 15 Jan 2025, BALATON Zoltan wrote:
This allows guests to set the CCSR base address. Also store and return
values of the local
17.01.2025 17:05, Laurent Vivier wrote:
CC: qemu-stable and qemu-trivial.
On 17/01/2025 12:17, Laurent Vivier wrote:
announce_self that sends a RARP packet after migration
or with announce_self QMP/HMP command doesn't work with
vhost because of the vnet headers.
announce_self is the only user
Implement the FPCR.AH semantics for the SVE FMAX and FMIN operations
that take an immediate as the second operand.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/tra
From: Richard Henderson
Move ARMFPStatusFlavour to cpu.h with which to index
this array. For now, place the array in an anonymous
union with the existing structures. Adjust the order
of the existing structures to match the enum.
Simplify fpstatus_ptr() using the new array.
Signed-off-by: Rich
From: Richard Henderson
The negation step in FCMLA mustn't negate a NaN when FPCR.AH
is set. Handle this by passing FPCR.AH to the helper via the
SIMD data field, and use this to select whether to do the
negation via XOR or via the muladd negate_product flag.
Signed-off-by: Richard Henderson
Me
Implement the FPCR.AH semantics for the SVE FMAX and FMIN
operations that take two vector operands.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c |
Split the handling of vector FABD so that it calls a different set
of helpers when FPCR.AH is 1, which implement the "no negation of
the sign of a NaN" semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/helper.h| 4
target/arm/tcg/translate-a
From: Richard Henderson
Replace with fp_status[FPST_STD_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c
From: Richard Henderson
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need
For FEAT_AFP, we want to emit different code when FPCR.NEP is set, so
that instead of zeroing the high elements of a vector register when
we write the output of a scalar operation to it, we instead merge in
those elements from one of the source registers. Since this affects
the generated code, we
Handle the FPCR.AH semantics that we do not change the sign of an
input NaN in the FRECPS and FRSQRTS scalar insns, by providing
new helper functions that do the CHS part of the operation
differently.
Since the extra helper functions would be very repetitive if written
out longhand, we condense th
Currently in softfloat we canonicalize input denormals and so the
code that implements floating point operations does not need to care
whether the input value was originally normal or denormal. However,
both x86 and Arm FEAT_AFP require that an exception flag is set if:
* an input is denormal
*
Make SVE FNEG honour the FPCR.AH "don't negate the sign of a NaN"
semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files changed, 18 inse
FPCR.AH == 1 mandates that negation of a NaN value should not flip
its sign bit. This means we can no longer use gen_vfp_neg*()
everywhere but must instead generate slightly more complex code when
FPCR.AH is set.
Make this change for the scalar FNEG and for those places in
translate-a64.c which w
Implement the increased precision variation of FRECPE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRecipEstimate() and
RecipEstimate() functions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/vfp_helper.c | 54 +++
For FEAT_AFP's FPCR.NEP bit, we need to programmatically change the
behaviour of the writeback of the result for most SIMD scalar
operations, so that instead of zeroing the upper part of the result
register it merges the upper elements from one of the input
registers.
Provide new functions write_f
When FPCR.AH is set, various behaviours of AArch64 floating point
operations which are controlled by softfloat config settings change:
* tininess and ftz detection before/after rounding
* NaN propagation order
* result of 0 * Inf + NaN
* default NaN value
When the guest changes the value of th
From: Richard Henderson
Replace with fp_status[FPST_AH_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 3 +--
target/arm/cpu.c| 2
Make the SVE FABD insn honour the FPCR.AH "don't negate the sign
of a NaN" semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 7 +++
target/arm/tcg/sve_helper.c| 22 ++
target/arm/tcg/translate-sve.c | 2 +-
Handle FPCR.NEP merging for scalar FABS and FNEG; this requires
an extra parameter to do_fp1_scalar_int(), since FMOV scalar
does not have the merging behaviour.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 27 ---
1 fi
From: Richard Henderson
Handle FPCR.AH's requirement to not negate the sign of a NaN
in FMLSL by element and vector, using the usual trick of
negating by XOR when AH=0 and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and do
For the instructions FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, use
FPST_FPCR_AH or FPST_FPCR_AH_F16 when FPCR.AH is 1, so that they get
the required behaviour changes.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
v1->v2: rename select_fpst() to select_ah_fpst(), put it in
tran
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS
(indexed). We do this by creating 6 new helpers, which allow us to
do the negation either by XOR (for AH=0) or by muladd flags
(for AH=1).
Signed-off-by: Peter Maydell
[PMM: Mostly from RTH's patch; error in index order into fn
Handle FPCR.NEP in the operations handled by do_cvtf_scalar().
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
From: Richard Henderson
Select on index instead of pointer.
No functional change.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/mve_helper.c | 40 +
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.
In this commit we
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this in the same way we did for
the base ASIMD FCADD, by encoding FPCR.AH into the SIMD data field
passed to the helper and using that to decide whether to negate the
values.
The construction o
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in FMLS (vector), by implementing a new set of helpers for
the AH=1 case.
The float_muladd_negate_product flag produces the same result
as negating either of the multiplication operands, assuming
neither of the operands are NaNs. But s
When FPCR.AH == 1, floating point FMIN and FMAX have some odd special
cases:
* comparing two zeroes (even of different sign) or comparing a NaN
with anything always returns the second argument (possibly
squashed to zero)
* denormal outputs are not squashed to zero regardless of FZ or FZ16
Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects
flushing of single and double precision denormal inputs to zero for
AArch64 floating point instructions. (For half-precision, the
existing FPCR.FZ16 control remains the only one.)
FPCR.FIZ differs from FPCR.FZ in that if we flush
Implement the FPCR.AH semantics for the SVE FMAXV and FMINV
vector-reduction-to-scalar max/min operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 +++
target/arm/tcg/sve_helper.c| 43 +-
tar
From: Richard Henderson
Replace with fp_status[FPST_AH].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 3 +--
target/arm/cpu.c| 6 +++---
do_fp3_scalar_idx() is used only for the FMUL and FMULX scalar by
element instructions; these both need to merge the result with the Rn
register when FPCR.NEP is set.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 6 +++---
1 file changed, 3 ins
From: Richard Henderson
Replace with fp_status[FPST_A64].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c|
When FPCR.AH is 1, the behaviour of some instructions changes:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2, BFMLALB, BFMLALT
* SVE BFCVT, BFCVTNT, BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
* SME BFCVT, BFCVTN, BFMLAL, BFMLSL (these are all in SME2 which
QEMU does not yet implement)
* FRECPE, FRECPS, FRECPX, F
From: Richard Henderson
Replace with fp_status[FPST_STD].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c|
Now the emulation is complete, we can enable FEAT_RPRES for the 'max'
CPU type.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst
From: Richard Henderson
Replace with fp_status[FPST_A32]. As this was the last of the
old structures, we can remove the anonymous union and struct.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-15-richard.hender...@linaro.org
[PMM: twea
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2
* SVE BFCVT, BFCVTNT
so that they get the required behaviour changes.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 27 +--
target/arm/tcg/tran
Make SVE FABS honour the FPCR.AH "don't negate the sign of a NaN"
semantics.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 4
target/arm/tcg/sve_helper.c| 8
target/arm/tcg/translate-sve.c | 7 ++-
3 files changed, 18 inse
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we
can enable FEAT_AFP for '-cpu max', and document that we support it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 ins
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in the vector versions of FRECPS and FRSQRTS, by implementing
new vector wrappers that call the _ah_ scalar helpers.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
From: Richard Henderson
The negation step in FCMLA by index mustn't negate a NaN when
FPCR.AH is set. Use the same approach as vector FCMLA of
passing in FPCR.AH and using it to select whether to negate
by XOR or by the muladd negate_product flag.
Signed-off-by: Richard Henderson
Message-id: 20
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
target/arm/tcg/translate-a64.c | 25 +
target/arm/tc
Implement the FPCR.AH semantics for FMAXV and FMINV. These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the _ah_ helper for the reduction step when
FPCR.AH == 1.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/t
The negation step in the SVE FTSSEL insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
v2: squashed in RTH's fix to use float*_may
FPCR.AH == 1 mandates that taking the absolute value of a NaN should
not change its sign bit. This means we can no longer use
gen_vfp_abs*() everywhere but must instead generate slightly more
complex code when FPCR.AH is set.
Implement these semantics for scalar FABS and FABD. This change also
a
Currently we handle flushing of output denormals in uncanon_normal
always before we deal with rounding. This works for architectures
that detect tininess before rounding, but is usually not the right
place when the architecture detects tininess after rounding. For
example, for x86 the SDM states
Currently we implement BFCVT scalar via do_fp1_scalar(). This works
even though BFCVT is a narrowing operation from 32 to 16 bits,
because we can use write_fp_sreg() for float16. However, FPCR.NEP
support requires that we use write_fp_hreg_merging() for float16
outputs, so we can't continue to bor
Handle the FPCR.AH "don't negate the sign of a NaN" semantics fro the
SVE FMLS (vector) insns, by providing new helpers for the AH=1 case
which end up passing fpcr_ah = true to the do_fmla_zpzzz_* functions
that do the work.
The float*_muladd functions have a flags argument that can
perform option
From: Richard Henderson
Replace with fp_status[FPST_A32_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFMLALB, BFMLALT
* SVE BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
so that they get the required behaviour changes.
We do this by making gen_gvec_op4_fpst() take an ARMFPStatusFlavour
rather than a bool is_fp16; existing callsites now select
FPST_FPCR_F
Add a test case which tests some corner case behaviour of
fused-multiply-add on x86:
* 0 * Inf + SNaN should raise Invalid
* 0 * Inf + QNaN shouldh not raise Invalid
* tininess should be detected after rounding
There is also one currently-disabled test case:
* flush-to-zero should be done afte
We are going to need to generate different code in some cases when
FPCR.AH is 1. For example:
* Floating point neg and abs must not flip the sign bit of NaNs
* some insns (FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, and various
BFCVT and BFM bfloat16 ops) need to use a different float_status
From: Richard Henderson
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need
From: Richard Henderson
Pass ARMFPStatusFlavour index instead of fp_status[FOO].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-17-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/vfp_helper.c | 10 +-
1
From: Richard Henderson
Read the bit from the source, rather than from the proxy via
get_flush_inputs_to_zero. This makes it clear that it does
not matter which of the float_status structures is used.
Signed-off-by: Richard Henderson
Message-id: 20250129013857.135256-34-richard.hender...@linar
For the x86 and the Arm FEAT_AFP semantics, we need to be able to
tell the target code that the FPU operation has used an input
denormal. Implement this; when it happens we set the new
float_flag_denormal_input_used.
Note that we only set this when an input denormal is actually used by
the operat
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this by encoding FPCR.AH into
the SIMD data field passed to the helper and using that to decide
whether to negate the values.
The construction of neg_imag and neg_real were done to make it easy
Implement the increased precision variation of FRSQRTE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRSqrtEstimate() and
RecipSqrtEstimate() functions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/vfp_helper.c | 7
The negation step in the SVE FTMAD insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field,
so we can select the correct behaviour.
Because the operand is known to be negative, negating the operand
is the same as taking the absolute value. Defer this to
From: Richard Henderson
Sink common code from the callers into do_fmlal
and do_fmlal_idx. Reorder the arguments to minimize
the re-sorting from the caller's arguments.
Signed-off-by: Richard Henderson
Message-id: 20250129013857.135256-35-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
This patchset implements emulation of the Arm FEAT_AFP and FEAT_RPRES
extensions, which are floating-point related. (Summary of what
these are exactly is at the bottom of the cover letter.)
If you'd rather have these patches as a git branch:
https://git.linaro.org/people/pmaydell/qemu-arm.git fe
Handle FPCR.NEP for the 3-input scalar operations which use
do_fmla_scalar_idx() and do_fmadd(), by making them call the
appropriate write_fp_*reg_merging() functions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 12 ++--
1 file change
From: Richard Henderson
Replace with fp_status[FPST_A64_F16].
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20250129013857.135256-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1 -
target/arm/cpu.c
From: Richard Henderson
The negation step in SVE FCMLA mustn't negate a NaN when FPCR.AH is
set. Use the same approach as we did for A64 FCMLA of passing in
FPCR.AH and using it to select whether to negate by XOR or by the
muladd negate_product flag.
Signed-off-by: Richard Henderson
Message-id
Handle FPCR.NEP for the 1-input scalar operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran
Implement the FPCR.AH == 1 semantics for vector FMIN/FMAX, by
creating new _ah_ versions of the gvec helpers which invoke the
scalar fmin_ah and fmax_ah helpers on each element.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 14 ++
t
Unlike the other users of do_2misc_narrow_scalar(), FCVTXN (scalar)
is always double-to-single and must honour FPCR.NEP. Implement this
directly in a trans function rather than using
do_2misc_narrow_scalar().
We still need gen_fcvtxn_sd() and the f_scalar_fcvtxn[] array for
the FCVTXN (vector) in
The Armv8.7 FEAT_AFP feature defines three new control bits in
the FPCR:
* FPCR.AH: "alternate floating point mode"; this changes floating
point behaviour in a variety of ways, including:
- the sign of a default NaN is 1, not 0
- if FPCR.FZ is also 1, denormals detected after rounding
In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in
pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always
raise the Invalid exception regardless of target architecture. (This
was a change affecting hppa, i386, sh4 and tricore.) However, this
was incorrect for i386, wh
When FPCR.AH = 1, some of the cumulative exception flags in the FPSR
behave slightly differently for A64 operations:
* IDC is set when a denormal input is used without flushing
* IXC (Inexact) is set when an output denormal is flushed to zero
Update vfp_get_fpsr_from_host() to do this.
Note tha
Am 30. Januar 2025 23:05:53 UTC schrieb "Philippe Mathieu-Daudé"
:
>Cc'ing AMD folks
>
>Hi Bernhard,
>
>TL;DR; can't you use the PCF8574 which is a more complete model of I/O
>expander? (See hw/gpio/pcf8574.c)
If it is software-compatible then I could use it. I'm modeling a real board
whose d
Am 1. Februar 2025 14:55:15 UTC schrieb Bernhard Beschow :
>
>
>Am 30. Januar 2025 12:45:58 UTC schrieb BALATON Zoltan :
>>On Wed, 15 Jan 2025, BALATON Zoltan wrote:
>>> This allows guests to set the CCSR base address. Also store and return
>>> values of the local access window registers but the
Am 30. Januar 2025 12:45:58 UTC schrieb BALATON Zoltan :
>On Wed, 15 Jan 2025, BALATON Zoltan wrote:
>> This allows guests to set the CCSR base address. Also store and return
>> values of the local access window registers but their functionality
>> isn't implemented.
>
>Ping?
I guess you're try
Am 29. Januar 2025 17:54:46 UTC schrieb BALATON Zoltan :
>On Tue, 28 Jan 2025, Bernhard Beschow wrote:
>> Am 28. Januar 2025 14:33:14 UTC schrieb Peter Maydell
>> :
>>> On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote:
Linux checks for the PLLs in the PHY to be locked, so implem
On 1/2/25 10:15, Philippe Mathieu-Daudé wrote:
On 32-bit hosts, rename 'raspi4b' -> 'raspi4b-1g' to clarify the
machine has 1GB of RAM.
On 64-bit hosts, rename 'raspi4b' -> 'raspi4b-2g'.
Keep the 'raspi4b' alias but deprecate it.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/deprecated
On Sat, 1 Feb 2025 at 12:57, BALATON Zoltan wrote:
>
> On Sat, 1 Feb 2025, Philippe Mathieu-Daudé wrote:
> > - Deprecate the 'raspi4b' machine name, renaming it as
> > 'raspi4b-1g' on 32-bit hosts, 'raspi4b-2g' otherwise.
> > - Add the 'raspi4b-4g' and 'raspi4b-8g' machines, with
> > respectivel
On Sat, 1 Feb 2025, Philippe Mathieu-Daudé wrote:
- Deprecate the 'raspi4b' machine name, renaming it as
'raspi4b-1g' on 32-bit hosts, 'raspi4b-2g' otherwise.
- Add the 'raspi4b-4g' and 'raspi4b-8g' machines, with
respectively 4GB and 8GB of DRAM.
IMHO (meaning you can ignore it, just my opin
Philippe Mathieu-Daudé writes:
> On 24/1/25 17:22, Philippe Mathieu-Daudé wrote:
>> On 23/1/25 02:22, Gustavo Romero wrote:
>>> Add me as the maintainer for the ivshmem-pci.c device, the ivshmem
>>> server, and the ivshmem client tool. Also, adjust remaining parts left
>>> behind after ivshmem PC
From: David Hildenbrand
Notify registered listeners about the remap at the end of
qemu_ram_remap() so e.g., a memory backend can re-apply its
settings correctly.
Signed-off-by: David Hildenbrand
Signed-off-by: William Roche
---
hw/core/numa.c | 11 +++
include/exec/ramlist.h |
From: William Roche
Let's register a RAM block notifier and react on remap notifications.
Simply re-apply the settings. Exit if something goes wrong.
Merging and dump settings are handled by the remap notification
in addition to memory policy and preallocation.
Co-developed-by: David Hildenbran
From: William Roche
The list of hwpoison pages used to remap the memory on reset
is based on the backend real page size.
To correctly handle hugetlb, we must mmap(MAP_FIXED) a complete
hugetlb page; hugetlb pages cannot be partially mapped.
Signed-off-by: William Roche
Co-developed-by: David Hi
From: William Roche
In case of a large page impacted by a memory error, provide an
information about the impacted large page before the memory
error injection message.
This message would also appear on ras enabled ARM platforms, with
the introduction of an x86 similar error injection message.
I
From: William Roche
Hello David,
Here is the version with the small nits corrected.
And the 'Acked-by' entries you gave me for patch 1 and 2.
---
This set of patches fixes several problems with hardware memory errors
impacting hugetlbfs memory backed VMs and the generic memory recovery
on VM r
From: David Hildenbrand
We want to reuse the functionality when remapping RAM.
Signed-off-by: David Hildenbrand
Signed-off-by: William Roche
---
backends/hostmem.c | 155 -
1 file changed, 82 insertions(+), 73 deletions(-)
diff --git a/backends/hos
From: William Roche
Repair poisoned memory location(s), calling ram_block_discard_range():
punching a hole in the backend file when necessary and regenerating
a usable memory.
If the kernel doesn't support the madvise calls used by this function
and we are dealing with anonymous memory, fall back
On 1/30/25 18:02, David Hildenbrand wrote:
On 27.01.25 22:31, “William Roche wrote:
From: William Roche
In case of a large page impacted by a memory error, provide an
information about the impacted large page before the memory
error injection message.
This message would also appear on ras ena
Add the raspi4b-8g machine, a raspi4b rev1.5 with 8GB of RAM.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi4b.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 2cf8bc467c5..2120bc1a6f8 100644
--- a/hw/arm/raspi4b.c
+++ b/hw
Add the raspi4b-4g machine, a raspi4b rev1.4 with 4GB of RAM.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2797
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi4b.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 59
There is no particular reason to not have the raspi4b-1g machine
available on 64-bit hosts, so expose it there.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi4b.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 7
In preparation of adding more machines based on the raspi4,
introduce TYPE_RASPI4_MACHINE. Remove TYPE_RASPI4B_MACHINE
definitions, declaring the machine name in place via the
MACHINE_TYPE_NAME("raspi4b") macro.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi4b.c | 16 ++--
1
On 32-bit hosts, rename 'raspi4b' -> 'raspi4b-1g' to clarify the
machine has 1GB of RAM.
On 64-bit hosts, rename 'raspi4b' -> 'raspi4b-2g'.
Keep the 'raspi4b' alias but deprecate it.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/deprecated.rst | 6 ++
hw/arm/raspi4b.c | 6 +++
Current raspi4b_machine_class_init() method register 2 distinct
machines, with different board revision (thus different memory
size), whether the host is 32-bit or more. Split it as 2 new
methods, one for the raspi4b with 1GB of memory (on 32-bit hosts)
and another for the raspi4b with 2GB of memor
- Deprecate the 'raspi4b' machine name, renaming it as
'raspi4b-1g' on 32-bit hosts, 'raspi4b-2g' otherwise.
- Add the 'raspi4b-4g' and 'raspi4b-8g' machines, with
respectively 4GB and 8GB of DRAM.
Philippe Mathieu-Daudé (7):
hw/arm/raspi4b: Declare machine types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Since
we are going to add more machines, convert type_init()
by DEFINE_TYPES().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/raspi4b.c | 19 ---
1 file changed, 8 inser
On 1/31/25 18:15, Cédric Le Goater wrote:
> On 1/30/25 21:41, Alex Williamson wrote:
>> On Fri, 31 Jan 2025 02:33:03 +0800
>> Tomita Moeko wrote:
>>
>>> On 1/25/25 15:42, Tomita Moeko wrote:
On 1/25/25 05:13, Alex Williamson wrote:
> On Sat, 25 Jan 2025 03:12:45 +0800
> Tomita Moeko
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