On 1/31/25 04:41, Alex Williamson wrote:
> On Fri, 31 Jan 2025 02:33:03 +0800
> Tomita Moeko wrote:
>
>> On 1/25/25 15:42, Tomita Moeko wrote:
>>> On 1/25/25 05:13, Alex Williamson wrote:
On Sat, 25 Jan 2025 03:12:45 +0800
Tomita Moeko wrote:
> Both enable opregion option
On 30/1/25 19:23, Peter Maydell wrote:
CP_ACCESS_TRAP_UNCATEGORIZED is technically an accurate description
of what this return value from a cpreg accessfn does, but it's liable
to confusion because it doesn't match how the Arm ARM pseudocode
indicates this case. What it does is an EXCP_UDEF with
On 30/1/25 19:23, Peter Maydell wrote:
On XScale CPUs, there is no EL2 or AArch64, so no syndrome register.
These traps are just UNDEFs in the traditional AArch32 sense, so
CP_ACCESS_TRAP_UNCATEGORIZED is more accurate than CP_ACCESS_TRAP.
This has no visible behavioural change, because the guest
On 31/1/25 22:07, Luke Craig wrote:
This PR extends the plugin API with two functions which allow convenient access
around tbs.
Luke Craig (3):
plugin: extend API with qemu_plugin_tb_get_insn_by_vaddr
plugin: extend API with qemu_plugin_tb_size
plugins: extend insn test for new conve
> On Jan 29, 2025, at 2:15 AM, Eric Auger wrote:
> Hi Shameer,
>
> On 1/29/25 9:10 AM, Shameerali Kolothum Thodi wrote:
>>
>>> -Original Message-
>>> From: Eric Auger
>>> Sent: Wednesday, January 29, 2025 7:56 AM
>>> To: Matt Ochs ; Shameerali Kolothum Thodi
>>>
>>> Cc: qemu-devel@nong
On Fri, 31 Jan 2025 14:23:58 +0100
Gerd Hoffmann wrote:
> On Fri, Jan 31, 2025 at 01:42:31PM +0100, Cédric Le Goater wrote:
> > + Gerd for insights regarding vIOMMU support in edk2.
> >
> > > > +static bool vfio_device_check_address_space(VFIODevice *vbasedev,
> > > > Error **errp)
> > > > +{
On Fri, 31 Jan 2025 17:15:01 +
Shivaprasad G Bhat wrote:
> Currently, the PCI_INTERRUPT_PIN alone is checked before enabling
> the INTx. Its also necessary to have the IRQ Lines assigned for
> the INTx to work. So, check the PCI_INTERRUPT_LINE against 0xff
> indicates no connection.
>
> The
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko
---
target/sparc/insns.decode | 7 ++-
t
On Thu, Jan 30, 2025 at 06:09:24PM +, Shameerali Kolothum Thodi wrote:
>
> Each "arm-smmuv3-nested" instance, when the first device gets attached
> to it, will create a S2 HWPT and a corresponding SMMUv3 domain in kernel
> SMMUv3 driver. This domain will have a pointer representing the physica
On Fri, Jan 31, 2025 at 06:08:32PM +0100, Paolo Bonzini wrote:
> Il ven 31 gen 2025, 17:46 Richard Henderson
> ha scritto:
>
> > On 1/29/25 04:47, Paolo Bonzini wrote:
> > > The difference with TCG of course is that TCG is in active development,
> > and therefore its
> > > 32-bit host support is
Rather than passing a boolean 'is_big_endian' argument,
directly pass the ELFDATA, which can be unspecified using
the ELFDATANONE value.
Update the call sites:
0 -> ELFDATA2LSB
1 -> ELFDATA2MSB
TARGET_BIG_ENDIAN -> TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB
Remove one &first_cpu use in hw/mips/loongson3_bootp.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-10-phi...@linaro.org>
---
hw/mips/loongson3_bootp.h | 2 +-
hw/mips/loongson3_bootp.c | 5 ++---
hw/mips/loongson3_virt.c | 1 +
3 file
From: Peter Maydell
Our style for other conversions of OMAP devices to qdev has been to
inline the creation and wiring into omap310_mpu_init() -- see for
instance the handling of omap-intc, omap-gpio and omap_i2c. Do
the same for omap-mmc.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hende
load_elf_ram_sym() with load_rom=true, sym_cb=NULL is
equivalent to load_elf_as(). Replace by the latter to
simplify.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250127113824.50177-2-phi...@linaro.org>
---
hw/avr/boot.c | 8 +++-
1 file changed, 3 ins
The FPGA exposes a fixed set of IRQs. Hold them in the FPGA
state and initialize them in place calling qemu_init_irqs().
Move r2d_fpga_irq enums earlier so we can use NR_IRQS within
the r2d_fpga_t structure. r2d_fpga_init() returns r2d_fpga_t,
and we dereference irq from it in r2d_init().
Signed-
From: Luke Craig
Signed-off-by: Luke Craig
---
tests/tcg/plugins/insn.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/tcg/plugins/insn.c b/tests/tcg/plugins/insn.c
index 0c723cb9ed..5974e9d6e6 100644
--- a/tests/tcg/plugins/insn.c
+++ b/tests/tcg/plugins/insn.c
@@ -142,6
MemMapEntry is declared in "exec/hwaddr.h", cpu_to_le32() in
"qemu/bswap.h". These headers are indirectly included via "cpu.h".
Include them explicitly in order to avoid when removing "cpu.h":
In file included from ../../hw/mips/loongson3_bootp.c:27:
hw/mips/loongson3_bootp.h:234:14: error: un
From: Peter Maydell
The coverswitch qemu_irq is never connected to anything, and the only thing
we do with it is set it in omap_mmc_reset(). Remove it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250128104519.3981448-8-peter.m
From: Peter Maydell
Do a minimal conversion of the omap_mmc device model to QDev.
In this commit we do the bare minimum to produce a working device:
* add the SysBusDevice parent_obj and the usual type boilerplate
* omap_mmc_init() now returns a DeviceState*
* reset is handled by sysbus reset
Rather than passing a boolean 'is_big_endian' argument,
directly pass the ELFDATA, which can be unspecified using
the ELFDATANONE value.
Update the call sites:
0 -> ELFDATA2LSB
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2
Signed-off-by: Luke Craig
---
include/qemu/qemu-plugin.h | 10 ++
plugins/api.c | 7 +++
2 files changed, 17 insertions(+)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index a1c478c54f..1fa656da82 100644
--- a/include/qemu/qemu-plugin.h
+++ b/inc
From: Peter Maydell
The SDCardClass has an 'enable' method, but nothing actually invokes it.
The underlying implementation is sd_enable(), which is documented
in sdcard_legacy.h as something that should not be used and was only
present for the benefit of the now-removed nseries boards. Unlike
all
From: Peter Maydell
The omap_mmc device has three outbound qemu_irq lines:
* one actual interrupt line
* two which connect to the DMA controller and are signalled for
TX and RX DMA
Convert these to a sysbus IRQ and two named GPIO outputs.
Signed-off-by: Peter Maydell
Reviewed-by: Richard
There are a fixed number of PCI IRQs, known beforehand.
Allocate them within PCIMultiSerialState, and initialize
using qemu_init_irq(), allowing to remove the legacy
qemu_allocate_irqs() and qemu_free_irqs() calls.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id:
From: Peter Maydell
This is a very old source file, and still has some lingering
hard-coded tabs; untabify it.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250128104519.3981448-9-peter.mayd...@linaro.org>
Signed-off-by: Philipp
This PR extends the plugin API with two functions which allow convenient access
around tbs.
The first, qemu_plugin_tb_size, provides a mechanism for determining the total
size of a translation block.
The second, qemu_plugin_tb_get_insn_by_vaddr, allows users to get a reference
to an instruction b
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-9-phi...@linaro.org>
---
hw/mips/loongson3_bootp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
index 91b58a71
Hi Pierrick,
Thank you for your reply.
I have submitted a new patch series with commits signed off.
Thanks!
-Luke
On Fri, Jan 31, 2025, 2:53 PM Pierrick Bouvier
wrote:
> Hi Luke,
>
> On 1/31/25 09:57, Luke Craig wrote:
> > This PR extends the plugin API with two functions which allow convenie
From: Titus Rwantare
This has been useful when debugging and unsure if the guest is
generating i2c traffic.
Signed-off-by: Titus Rwantare
Reviewed-by: Hao Wu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250121105935.3069035-1-tit...@google.com>
Signed-off-by: Philippe Mathieu-Daudé
---
From: Peter Maydell
The approach we've settled on for handling the omap_clk wiring for
OMAP devices converted to QDev is to have a function omap_foo_set_clk()
whose implementation just sets the field directly in the device's
state struct. (See the "TODO" comment near the top of omap.h.)
Make omap
From: Peter Maydell
Convert the OMAP MMC controller to the new SDBus API:
* the controller creates an SDBus bus
* instead of sd_foo functions on the SDState object, call
sdbus_foo functions on the SDBus
* the board code creates a proper TYPE_SD_CARD object and attaches
it to the controll
From: Peter Maydell
Now that sd_enable() has been removed, SD::enable is set to true in
sd_instance_init() and then never changed. So we can remove it.
Note that the VMSTATE_UNUSED() size argument should be '1', not
'sizeof(bool)', as noted in the CAUTION comment in vmstate.h.
Signed-off-by: Pe
From: Peter Maydell
The sdcard_legacy.h header defines function prototypes for the "legacy"
SD card API, which was used by non-qdevified SD controller models.
We've now converted the only remaining non-qdev SD controller, so
we can drop the legacy API.
Entirely unused functions:
sd_init(), sd_
From: BALATON Zoltan
The variable is uint64_t so needs %PRIu64 instead of %d.
Fixes: 3ae7eb88c47 ("ehci: fix overflow in frame timer code")
Signed-off-by: BALATON Zoltan
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250124124713.64f8c4e6...@zero.eik.bme.hu>
Sig
No need to dynamically allocate IRQ when we know before hands
how many we'll use. Declare the 2 of them in IPackDevice state
and initialize them in the DeviceRealize handler.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250121155526.29982-4-phi...@linaro.or
load_elf_ram_sym() compares target_data_order versus
host data_order. Rename 'data_order' -> 'host_data_order'
to ease code review. Avoid the preprocessor by directly
checking HOST_BIG_ENDIAN.
Reviewed-by: BALATON Zoltan
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Messa
From: Peter Maydell
Mechanically convert the remaining uses of 'struct omap_mmc_s' to
'OMAPMMCState'.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250128104519.3981448-3-peter.mayd...@linaro.org>
Signed-off-by: Philippe Mathieu
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232}
- IPack is a bus
- TPCI200 is a PCI device providing an IPack bus
- IP-Octal232 is an IPack device plugged on an IPack bus
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Fabiano Rosas
Message-Id: <20250121155526.29982-3-phi...@lin
Signed-off-by: Luke Craig
---
include/qemu/qemu-plugin.h | 11 +++
plugins/api.c | 13 +
2 files changed, 24 insertions(+)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 3a850aa216..a1c478c54f 100644
--- a/include/qemu/qemu-plugin.h
++
Rather than passing a boolean 'is_big_endian' argument,
directly pass the ELFDATA, which can be unspecified using
the ELFDATANONE value.
Update the call sites:
0 -> ELFDATA2LSB
1 -> ELFDATA2MSB
Note, this allow removing the target_words_bigendian() call
in the GENERIC_LOADER device, where we
Pass the first vCPU as argument, allowing to remove
another &first_cpu global use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-5-phi...@linaro.org>
---
hw/mips/loongson3_virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Last use of load_elf_ram() was removed in commit 188e255bf8e
("hw/s390x: Remove the possibility to load the s390-netboot.img
binary"), remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20250127113824.50177-3-phi...@linaro.
Remove one use of the 'current_machine' global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-8-phi...@linaro.org>
---
hw/mips/loongson3_virt.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/mips/loongson3_v
While qemu_init_irq() initialize a single IRQ,
qemu_init_irqs() initialize an array of them.
Suggested-by: Bernhard Beschow
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250121155526.29982-2-phi...@linaro.org>
---
include/hw/irq.h | 11 +++
hw/core
main_cpu_reset() is misleadingly named "main": it resets
all vCPUs, with a special case for the first vCPU.
Factor generic_cpu_reset() out of main_cpu_reset(),
allowing to remove one &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952
Propagate %processor_id from mips_loongson3_virt_init() where
we have a reference to the first vCPU, so use it instead of
the &first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-11-phi...@linaro.org>
---
hw/mips/loongson3_vir
Create vCPUs from the last one to the first one.
No need to use the &first_cpu global since we already
have it referenced.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20250115232952.31166-3-phi...@linaro.org>
---
hw/mips/loongson3_virt.c | 9 -
1 fi
loongson3_bootp.c doesn't contain any target-specific code
and can be build generically, move it to common_ss[].
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-12-phi...@linaro.org>
---
hw/mips/meson.build | 3 ++-
1 file changed, 2 insert
Propagate the %cpu_count from the machine file, allowing
to remove the "hw/boards.h" dependency (which is machine
specific) from loongson3_bootp.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-7-phi...@linaro.org>
---
hw/mips/loongson3_boo
The following changes since commit 871af84dd599fab68c8ed414d9ecbdb2bcfc5801:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2025-01-29 09:51:03 -0500)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-20250131
rx_gdbsim_init() has access to the single CPU via:
RxGdbSimMachineState {
RX62NState {
RXCPU cpu;
...
} mcu;
} s;
Directly use that instead of the &first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250110180442.82687-1
'loaderparams' is declared statically. Let fw_conf_init()
access its 'cpu_freq' and 'ram_size' fields.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20250115232952.31166-4-phi...@linaro.org>
---
hw/mips/loongson3_virt.c | 12 ++--
1 file changed, 6 in
On Fri, Jan 24, 2025 at 03:19:46PM +, Jonathan Cameron wrote:
> On Thu, 23 Jan 2025 10:39:03 +0530
> Vinayak Holikatti wrote:
>
> > CXL spec 3.1 section 8.2.9.9.5.3 describes media operations commands.
> > CXL devices supports media operations Sanitize and Write zero command.
>
> As
On 1/28/25 3:05 AM, Alistair Francis wrote:
Bin Meng has been a long time contributor and maintainer for QEMU RISC-V
and has been very beneficial to the RISC-V ecosystem.
Unfortunately his email has started to bounce so this patch is removing
them from MAINTAINERS. If in the future Bin Meng w
Hi Luke,
On 1/31/25 09:57, Luke Craig wrote:
This PR extends the plugin API with two functions which allow convenient access
around tbs.
The first, qemu_plugin_tb_size, provides a mechanism for determining the total
size of a translation block.
The second, qemu_plugin_tb_get_insn_by_vaddr, a
On Fri, 24 Jan 2025 17:28:02 +0100
Philippe Mathieu-Daudé wrote:
> On 24/1/25 17:20, Jonathan Cameron wrote:
> > On Thu, 23 Jan 2025 09:51:51 +
> > Jonathan Cameron via wrote:
> >
> >> On Wed, 22 Jan 2025 07:56:24 +0100
> >> Philippe Mathieu-Daudé wrote:
> >>
> >>> Map the component I/
On Fri, Jan 24, 2025 at 2:40 PM Xiaoyao Li wrote:
>
> For TDX guest, the phys_bits is not configurable and can only be
> host/native value.
>
> Validate phys_bits inside tdx_check_features().
Hi Xiaoyao,
to avoid
qemu-kvm: TDX requires guest CPU physical bits (48) to match host CPU
physical bit
On 31/1/25 19:30, Helge Deller wrote:
On 1/31/25 19:15, Philippe Mathieu-Daudé wrote:
On 28/1/25 18:09, del...@kernel.org wrote:
From: Helge Deller
Since I contribute quite some code to hppa, I'd like to step up and
become the secondary maintainer for HPPA beside Richard.
Additionally change
On 24/1/25 17:22, Philippe Mathieu-Daudé wrote:
On 23/1/25 02:22, Gustavo Romero wrote:
Add me as the maintainer for the ivshmem-pci.c device, the ivshmem
server, and the ivshmem client tool. Also, adjust remaining parts left
behind after ivshmem PCI device was renamed from ivshmem.c to
ivshmem-
On 1/31/25 19:15, Philippe Mathieu-Daudé wrote:
On 28/1/25 18:09, del...@kernel.org wrote:
From: Helge Deller
Since I contribute quite some code to hppa, I'd like to step up and
become the secondary maintainer for HPPA beside Richard.
Additionally change status of hppa machines to maintained a
On 30.01.2025 21:27, Maciej S. Szmigiero wrote:
On 30.01.2025 21:19, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
This is an updated v4 patch series of the v3 series located here:
https://lore.kernel.org/qemu-devel/cover.1731773021.git.maciej.szmigi...@orac
On 28/1/25 18:09, del...@kernel.org wrote:
From: Helge Deller
Since I contribute quite some code to hppa, I'd like to step up and
become the secondary maintainer for HPPA beside Richard.
Additionally change status of hppa machines to maintained as I will
take care of them.
Signed-off-by: Helge
On 16/1/25 00:29, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (11):
hw/mips/loongson3_virt: Factor generic_cpu_reset() out
hw/mips/loongson3_virt: Invert vCPU creation order to remove
&first_cpu
hw/mips/loongson3_virt: Have fw_conf_init() access local loaderparams
hw/mi
---
include/qemu/qemu-plugin.h | 10 ++
plugins/api.c | 7 +++
2 files changed, 17 insertions(+)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index a1c478c54f..1fa656da82 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugin.h
@@
---
include/qemu/qemu-plugin.h | 11 +++
plugins/api.c | 13 +
2 files changed, 24 insertions(+)
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 3a850aa216..a1c478c54f 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugi
This PR extends the plugin API with two functions which allow convenient access
around tbs.
The first, qemu_plugin_tb_size, provides a mechanism for determining the total
size of a translation block.
The second, qemu_plugin_tb_get_insn_by_vaddr, allows users to get a reference
to an instructio
From: Luke Craig
---
tests/tcg/plugins/insn.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/tcg/plugins/insn.c b/tests/tcg/plugins/insn.c
index 0c723cb9ed..5974e9d6e6 100644
--- a/tests/tcg/plugins/insn.c
+++ b/tests/tcg/plugins/insn.c
@@ -142,6 +142,8 @@ static void vcpu
The hw_error_le pointer is used for legacy support (virt-9.2).
Starting from virt-10.0, HEST table is accessed via hest_addr_le.
Remove fw_cfg logic for legacy support if virt is 10.0 or upper.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 30 --
1 file c
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 10.0 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
The GHES migration logic should now support HEST table location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/gener
Using the QMP GHESv2 API requires preparing a raw data array
containing a CPER record.
Add a helper script with subcommands to prepare such data.
Currently, only ARM Processor error CPER record is supported, by
using:
$ ghes_inject.py arm
which produces those warnings on Linux:
[ 705.0
The current code is actually dependent on having just one error
structure with a single source.
As the number of sources should be arch-dependent, as it will depend on
what kind of notifications will exist, change the logic to dynamically
build the table.
Yet, for a proper support, we need to get
Creates a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU a
Now that the ghes preparation patches were merged, let's add support
for error injection.
On this series, the first 6 patches chang to the math used to calculate offsets
at HEST
table and hardware_error firmware file, together with its migration code.
Migration tested
with both latest QEMU relea
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the ack.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table and the type of the
HEST error block st
Store HEST table address at GPA, placing its the start of the table at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 16
include/hw/acpi/ghes.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/hw/ac
Move the check logic into a common function and simplify the
code which checks if GHES is enabled and was properly setup.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes-stub.c| 7 ---
hw/acpi/ghes.c | 40
The DSDT table will also be affected by such change.
Signed-off-by: Mauro Carvalho Chehab
---
tests/data/acpi/aarch64/virt/HEST | 0
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/aarch64/virt/HEST
diff --git a/te
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
hw/acpi/ghes.c | 5 -
include/hw/acpi/ghes.h | 3 +++
2 files
--- a/DSDT.dsl2025-01-28 09:38:15.155347858 +0100
+++ b/DSDT.dsl2025-01-28 09:39:01.684836954 +0100
@@ -9,9 +9,9 @@
*
* Original Table Header:
* Signature"DSDT"
- * Length 0x1516 (5398)
+ * Length 0x1542 (5442)
* Revision
On 1/29/25 04:18, Gurchetan Singh wrote:
> On Sun, Jan 26, 2025 at 12:14 PM Dmitry Osipenko <
> dmitry.osipe...@collabora.com> wrote:
>
>> From: Alex Bennée
>>
>> This attempts to tidy up the VirtIO GPU documentation to make the list
>> of requirements clearer. There are still a lot of moving par
On 1/27/25 09:28, Akihiko Odaki wrote:
...
Thanks for the doc review! Will improve the patch in the next iteration.
--
Best regards,
Dmitry
Currently, the PCI_INTERRUPT_PIN alone is checked before enabling
the INTx. Its also necessary to have the IRQ Lines assigned for
the INTx to work. So, check the PCI_INTERRUPT_LINE against 0xff
indicates no connection.
The problem was observed on Power10 systems which primarily use
MSI-X, and LSI
On 1/27/25 19:17, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>>
>> Contarary to Virgl and Venus contexts that mediates high level GFX APIs,
>> DRM native context [1] mediates lower level kernel driver UAPI, which
>> refle
Il ven 31 gen 2025, 17:46 Richard Henderson
ha scritto:
> On 1/29/25 04:47, Paolo Bonzini wrote:
> > The difference with TCG of course is that TCG is in active development,
> and therefore its
> > 32-bit host support is not surviving passively in the same way that a
> random device is.
> > Still,
On Sat, 25 Jan 2025 at 17:08, Richard Henderson
wrote:
>
> On 1/24/25 08:27, Peter Maydell wrote:
> > diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
> > index 3c8f3e65887..8c79ab4fc8a 100644
> > --- a/target/arm/vfp_helper.c
> > +++ b/target/arm/vfp_helper.c
> > @@ -242,6 +242,9 @@
Hello Gerd,
On 1/31/25 14:23, Gerd Hoffmann wrote:
On Fri, Jan 31, 2025 at 01:42:31PM +0100, Cédric Le Goater wrote:
+ Gerd for insights regarding vIOMMU support in edk2.
+static bool vfio_device_check_address_space(VFIODevice *vbasedev, Error **errp)
+{
+uint32_t cpu_aw_bits = cpu_get_ph
On 28/1/25 11:45, Peter Maydell wrote:
This series QOMifies the omap-mmc device. The main reason for
this is that this device is now the only remaining in-tree
user of the legacy SD APIs defined in sdcard_legacy.h.
The first 8 patches QOMify the device and do some minor
cleanup on it. Patches 9 t
Hi Nicolin,
On 1/9/25 5:45 AM, Nicolin Chen wrote:
> On Mon, Dec 16, 2024 at 10:01:29AM +, Shameerali Kolothum Thodi wrote:
>> And patches prior to this commit adds that support:
>> 4ccdbe3: ("cover-letter: Add HW accelerated nesting support for arm
>> SMMUv3")
>>
>> Nicolin is soon going to
On 1/29/25 04:47, Paolo Bonzini wrote:
The difference with TCG of course is that TCG is in active development, and therefore its
32-bit host support is not surviving passively in the same way that a random device is.
Still, I think we can identify at least three different parts that should be t
On Wed, 29 Jan 2025 at 01:39, Richard Henderson
wrote:
>
> Split negation cases out of gvec_fmla, creating 6 new helpers.
> We no longer pass 'neg' as a bit in simd_data.
>
> Handle FPCR.AH=0 via xor and FPCR.AH=1 via muladd flags.
> static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a,
On Fri, 31 Jan 2025 16:49:19 +0100
Mauro Carvalho Chehab wrote:
> Em Wed, 29 Jan 2025 16:29:53 +0100
> Igor Mammedov escreveu:
>
> > On Wed, 29 Jan 2025 09:04:18 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > DSDT has gained a GED device to notify errors:
> > >
> > > --- a/DSDT.dsl
Em Wed, 29 Jan 2025 16:23:28 +0100
Igor Mammedov escreveu:
> > +
> > +/*
> > + * Tell firmware to write into GPA the address of HEST via fw_cfg,
> > + * once initialized.
> > + */
> > +bios_linker_loader_write_pointer(linker,
> > + ACPI_HEST
Em Thu, 30 Jan 2025 15:38:30 +0100
Igor Mammedov escreveu:
> On Thu, 30 Jan 2025 14:03:24 +0100
> Mauro Carvalho Chehab wrote:
>
> > Em Wed, 29 Jan 2025 16:03:28 +0100
> > Igor Mammedov escreveu:
> >
> > > On Wed, 29 Jan 2025 09:04:08 +0100
> > > Mauro Carvalho Chehab wrote:
> > >
> >
Hi,
On 1/31/25 4:23 PM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Jason Gunthorpe
>> Sent: Friday, January 31, 2025 2:54 PM
>> To: Shameerali Kolothum Thodi
>> Cc: Daniel P. Berrangé ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org; eric.au...@redhat.com;
>> peter
Em Wed, 29 Jan 2025 16:29:53 +0100
Igor Mammedov escreveu:
> On Wed, 29 Jan 2025 09:04:18 +0100
> Mauro Carvalho Chehab wrote:
>
> > DSDT has gained a GED device to notify errors:
> >
> > --- a/DSDT.dsl2025-01-28 09:38:15.155347858 +0100
> > +++ b/DSDT.dsl2025-01-28 09:39:01.68
On 2025-01-31 10:03, Peter Xu wrote:
> On Fri, Jan 31, 2025 at 02:42:41PM +0100, Juraj Marcin wrote:
> > On 2025-01-30 16:04, Peter Xu wrote:
> > > On Thu, Jan 30, 2025 at 05:11:36PM +0100, Juraj Marcin wrote:
> > > > When there are no page requests from the destination side and the
> > > > connect
> -Original Message-
> From: Jason Gunthorpe
> Sent: Friday, January 31, 2025 2:54 PM
> To: Shameerali Kolothum Thodi
> Cc: Daniel P. Berrangé ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; eric.au...@redhat.com;
> peter.mayd...@linaro.org; nicol...@nvidia.com; ddut...@redhat.com;
> L
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