Re: [PATCH] hw/virtio/vhost: Disable IOTLB callbacks when IOMMU gets disabled

On Sat, Jan 25, 2025 at 12:42 AM Peter Xu wrote: > > Hello, Jason, Eric, > > On Fri, Jan 24, 2025 at 11:30:56AM +0800, Jason Wang wrote: > > It might be because neither virtio bus nor virtio-net provides a > > shutdown method. > > > > There used to be requests to provide those to unbreak the kexec

[PATCH 06/12] target/riscv: handle vzext.vf2 form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index a873536eea..0952bcbe2c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b

[PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f5ba1c4280..a873536eea 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b

[PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register

Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/target/ris

[PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bc2780497e..f5ba1c4280 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b

[PATCH 08/12] target/riscv: handle vwadd.vv form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bc22b42801..45b2868c54 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b

[PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap because it would mean a register is read with two different SEW settings. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv

[PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 312d8b1b81..2741f8bd8e 100644 --- a/target/ris

[PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 0952bcbe2c..bc22b42801 100644 --- a/target/riscv/insn_tr

[PATCH 02/12] target/riscv: handle vrgather mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 20b1cb127b..c66cd95bdb 100644 --- a/target/riscv/insn

[PATCH 12/12] target/riscv: handle overlap in widening instructions with overwrite

In these instructions vd is considered a source, so no overlap is allowed between vd and vs1/vs2. See: https://github.com/riscv/riscv-isa-manual/issues/1789 Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 71 +++-- 1 file changed, 56 insertions(+

[PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

This series fixes some RISC-V instruction corner cases, specifically illegal overlaps between mask and source registers, illegal overlaps between source registers and illegal overlaps between source and destination registers. These were found by looking at miscompares between QEMU and the Tenstorre

[PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index c66cd95bdb..bc2780497e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b

[PATCH 09/12] target/riscv: handle vwadd.wv form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 45b2868c54..2309d9abd0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b

RE: [PATCH] hw/virtio/vhost: Disable IOTLB callbacks when IOMMU gets disabled

Hi Eric, >-Original Message- >From: Eric Auger >Subject: Re: [PATCH] hw/virtio/vhost: Disable IOTLB callbacks when IOMMU gets >disabled ... >> vtd_address_space_refresh_all() will basically disable the iommu >> memory region. It looks not sufficient to trigger the region_del >

SPARC64 Support and Solaris 10

How is the support for SPARC64? Is anyone able to run Solaris 10?

Re: [PATCH v7 1/6] coreaudio: Remove unnecessary explicit casts

On 2025/01/25 19:41, Christian Schoenebeck wrote: On Saturday, January 25, 2025 6:58:30 AM CET Akihiko Odaki wrote: On 2025/01/24 18:39, Christian Schoenebeck wrote: On Friday, January 24, 2025 6:12:04 AM CET Akihiko Odaki wrote: coreaudio had unnecessary explicit casts and they had extra whit

Re: [PATCH v5 3/4] audio: Add functions to initialize buffers

On 2025/01/26 3:25, Philippe Mathieu-Daudé wrote: On 24/1/25 05:58, Akihiko Odaki wrote: On 2025/01/23 17:43, Philippe Mathieu-Daudé wrote: Hi Akihiko, On 23/1/25 08:18, Akihiko Odaki wrote: These functions can be used to re-initialize buffers when hardware parameters change due to device hot

Re: [PATCH 2/7] guest_memfd: Introduce an object to manage the guest-memfd with RamDiscardManager

> Definitely not suggesting to install an invalid pointer anywhere. The > mapped pointer will still be valid for gmem for example, but the fault > isn't. We need to differenciate two things (1) virtual address mapping, > then (2) permission and accesses on the folios / pages of the mapping. > Her

Re: [PULL 15/32] tests/functional/aarch64: add tests for FEAT_RME

Pierrick Bouvier writes: > Hi Thomas, > > On 1/24/25 05:29, Thomas Huth wrote: >> On 10/01/2025 14.17, Alex Bennée wrote: >>> From: Pierrick Bouvier >>> >>> This boot an OP-TEE environment, and launch a nested guest VM inside it >>> using the Realms feature. We do it for virt and sbsa-ref platfo

Re: [PATCH v1 4/4] x86-disas: add x86-mini disassembler implementation

to save time on reviews. I had a look over the patch in light of QEMU conventions I neglected due to it being portable code. this is what I have found so far: - use g_malloc/g_malloc0/g_free instead of malloc/calloc/free. - remove duplicate unused definition of ctz/clz/popcnt. - remove some magi

Re: [PATCH v5 3/4] audio: Add functions to initialize buffers

On 24/1/25 05:58, Akihiko Odaki wrote: On 2025/01/23 17:43, Philippe Mathieu-Daudé wrote: Hi Akihiko, On 23/1/25 08:18, Akihiko Odaki wrote: These functions can be used to re-initialize buffers when hardware parameters change due to device hotplug, for example. Signed-off-by: Akihiko Odaki R

[PATCH 2/2] qemu/timer: Sanity check timer_list in timer_init_full()

Ensure we are not re-initializing a QEMUTimer already added to an active list. timer_init*() functions expect either a recently created and zeroed QEMUTimer, or one previously free'd with timer_free(). Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/timer.h | 2 +- util/qemu-timer.c|

[PATCH 1/9] hw/sysbus: Use sizeof(BusState) in main_system_bus_create()

Rather than using the obscure system_bus_info.instance_size, directly use sizeof(BusState). Signed-off-by: Philippe Mathieu-Daudé --- hw/core/sysbus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 9355849ff0a..f713bbfe04f 100644

[PATCH 0/2] qemu/timer: Clarify QEMUTimer new/free API

Update few QEMUTimer docstring and add a sanity check during timer initialization. Noticed trying to understand leaks in QDev Realize -> Unrealize -> Realize transition. Philippe Mathieu-Daudé (2): qemu/timer: Clarify timer_new*() must be freed with timer_free() qemu/timer: Sanity check timer

[PATCH 1/2] qemu/timer: Clarify timer_new*() must be freed with timer_free()

There was not mention QEMUTimer created with timer_new*() must be released with timer_free() instead of g_free(), because then active timers are removed from the active list. Update the documentation mentioning timer_free(). Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/timer.h | 10 +++

[PATCH 5/9] hw/display: Have RAMFB device inherit from DYNAMIC_SYS_BUS_DEVICE

Because the RAM FB device can be optionally plugged on the TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE. Signed-off-by: Philippe Mathieu-Daudé --- hw/display/ramfb-standalone.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/display/ramfb-standal

[PATCH 8/9] hw/tpm: Have TPM TIS sysbus device inherit from DYNAMIC_SYS_BUS_DEVICE

Because the TPM TIS sysbus device can be optionally plugged on the TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE. Signed-off-by: Philippe Mathieu-Daudé --- hw/tpm/tpm_tis_sysbus.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/tpm/tpm_tis_sysbus.

[PATCH 7/9] hw/net: Have eTSEC device inherit from DYNAMIC_SYS_BUS_DEVICE

Because the network eTSEC device can be optionally plugged on the TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/etsec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/net/fsl_etsec/etse

[PATCH 2/9] hw/sysbus: Declare QOM types using DEFINE_TYPES() macro

When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Signed-off-by: Philippe Mathieu-Daudé --- hw/core/sysbus.c | 39 +-- 1 f

[PATCH 0/9] hw/sysbus/platform-bus: Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE

Some SysBus devices can optionally be dynamically plugged onto the sysbus-platform-bus (then virtual guests are aware of mmio mapping and IRQs via device tree / ACPI rules). This series makes these devices explicit by having them implement the DYNAMIC_SYS_BUS_DEVICE class, which only sets 'user_cr

[RFC PATCH 9/9] hw/xen: Have legacy Xen backend inherit from DYNAMIC_SYS_BUS_DEVICE

Because the legacy Xen backend devices can optionally be plugged on the TYPE_PLATFORM_BUS_DEVICE, have it inherit TYPE_DYNAMIC_SYS_BUS_DEVICE. Remove the implicit TYPE_XENSYSDEV instance_size. Untested, but I'm surprised the legacy devices work because they had a broken instance size (QDev instead

[PATCH 6/9] hw/i386: Have X86_IOMMU devices inherit from DYNAMIC_SYS_BUS_DEVICE

Do not explain why _X86_IOMMU devices are user_creatable, have them inherit TYPE_DYNAMIC_SYS_BUS_DEVICE, to explicit they can optionally be plugged on TYPE_PLATFORM_BUS_DEVICE. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/amd_iommu.c | 2 -- hw/i386/intel_iommu.c | 2 -- hw/i386/x86-iommu

[PATCH 4/9] hw/vfio: Have VFIO_PLATFORM devices inherit from DYNAMIC_SYS_BUS_DEVICE

Do not explain why VFIO_PLATFORM devices are user_creatable, have them inherit TYPE_DYNAMIC_SYS_BUS_DEVICE, to explicit they can optionally be plugged on TYPE_PLATFORM_BUS_DEVICE. Signed-off-by: Philippe Mathieu-Daudé --- hw/vfio/amd-xgbe.c | 2 -- hw/vfio/calxeda-xgmac.c | 2 -- hw/vfio/pl

[PATCH 3/9] hw/sysbus: Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE

Some TYPE_SYS_BUS_DEVICEs can be optionally dynamically plugged on the TYPE_PLATFORM_BUS_DEVICE. Rather than sometimes noting that with comment around the 'user_creatable = true' line in each DeviceRealize handler, introduce an abstract TYPE_DYNAMIC_SYS_BUS_DEVICE class. Signed-off-by: Philippe Ma

Re: [PATCH 39/76] target/arm: Handle FPCR.NEP for BFCVT scalar

On 1/24/25 08:27, Peter Maydell wrote: Currently we implement BFCVT scalar via do_fp1_scalar(). This works even though BFCVT is a narrowing operation from 32 to 16 bits, because we can use write_fp_sreg() for float16. However, FPCR.NEP support requires that we use write_fp_hreg_merging() for flo

Re: [PATCH 38/76] target/arm: Handle FPCR.NEP for 3-input scalar operations

On 1/24/25 08:27, Peter Maydell wrote: Handle FPCR.NEP for the 3-input scalar operations which use do_fmla_scalar_idx() and do_fmadd(), by making them call the appropriate write_fp_*reg_merging() functions. Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 12 ++-- 1 f

Re: [PATCH 37/76] target/arm: Define and use new write_fp_*reg_merging() functions

On 1/24/25 08:27, Peter Maydell wrote: For FEAT_AFP's FPCR.NEP bit, we need to programmatically change the behaviour of the writeback of the result for most SIMD scalar operations, so that instead of zeroing the upper part of the result register it merges the upper elements from one of the input

Re: [PATCH 36/76] target/arm: Add FPCR.NEP to TBFLAGS

On 1/24/25 08:27, Peter Maydell wrote: For FEAT_AFP, we want to emit different code when FPCR.NEP is set, so that instead of zeroing the high elements of a vector register when we write the output of a scalar operation to it, we instead merge in those elements from one of the source registers. S

Re: [PATCH 35/76] target/arm: Use FPST_FPCR_AH for BFMLAL*, BFMLSL* insns

On 1/24/25 08:27, Peter Maydell wrote: When FPCR.AH is 1, use FPST_FPCR_AH for: * AdvSIMD BFMLALB, BFMLALT * SVE BFMLALB, BFMLALT, BFMLSLB, BFMLSLT so that they get the required behaviour changes. We do this by making gen_gvec_op4_fpst() take an ARMFPStatusFlavour rather than a bool is_fp16

Re: [PATCH 34/76] target/arm: Use FPST_FPCR_AH for BFCVT* insns

On 1/24/25 08:27, Peter Maydell wrote: When FPCR.AH is 1, use FPST_FPCR_AH for: * AdvSIMD BFCVT, BFCVTN, BFCVTN2 * SVE BFCVT, BFCVTNT so that they get the required behaviour changes. Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 27 +-- target/

Re: [PATCH 33/76] target/arm: Use FPST_FPCR_AH for FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS

On 1/24/25 08:27, Peter Maydell wrote: For the instructions FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, use FPST_FPCR_AH or FPST_FPCR_AH_F16 when FPCR.AH is 1, so that they get the required behaviour changes. Signed-off-by: Peter Maydell --- select_fpst() is another function I'm not super happy w

Re: [PATCH 32/76] target/arm: Set up float_status to use for FPCR.AH=1 behaviour

On 1/24/25 08:27, Peter Maydell wrote: When FPCR.AH is 1, the behaviour of some instructions changes: * AdvSIMD BFCVT, BFCVTN, BFCVTN2, BFMLALB, BFMLALT * SVE BFCVT, BFCVTNT, BFMLALB, BFMLALT, BFMLSLB, BFMLSLT * SME BFCVT, BFCVTN, BFMLAL, BFMLSL (these are all in SME2 which QEMU does no

[PATCH v3 01/24] cpus: Restrict cpu_has_work() to system emulation

This method is not used on user emulation, because there is always work to do there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/include/hw/core/

Re: [PATCH 31/76] target/arm: Add FPCR.AH to tbflags

On 1/24/25 08:27, Peter Maydell wrote: We are going to need to generate different code in some cases when FPCR.AH is 1. For example: * Floating point neg and abs must not flip the sign bit of NaNs * some insns (FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, and various BFCVT and BFM bfloat16

Re: [PATCH 30/76] target/arm: Adjust exception flag handling for AH = 1

On 1/24/25 08:27, Peter Maydell wrote: When FPCR.AH = 1, some of the cumulative exception flags in the FPSR behave slightly differently for A64 operations: * IDC is set when a denormal input is used without flushing * IXC (Inexact) is set when an output denormal is flushed to zero Update vfp

Re: [PATCH 29/76] target/arm: Adjust FP behaviour for FPCR.AH = 1

On 1/24/25 08:27, Peter Maydell wrote: When FPCR.AH is set, various behaviours of AArch64 floating point operations which are controlled by softfloat config settings change: * tininess and ftz detection before/after rounding * NaN propagation order * result of 0 * Inf + NaN * default NaN

Re: [PATCH 28/76] target/arm: Implement FPCR.FIZ handling

On 1/24/25 08:27, Peter Maydell wrote: Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects flushing of single and double precision denormal inputs to zero for AArch64 floating point instructions. (For half-precision, the existing FPCR.FZ16 control remains the only one.) FPCR.FIZ

[PATCH v3 10/24] target/loongarch: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a604704..20aba0e1fff 100644 --- a/target/loongarch/cpu.c +++ b/tar

[PATCH v3 05/24] target/arm: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 048b825a006..322c95038d5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -123,6 +123,

Re: [PATCH 27/76] target/arm: Define FPCR AH, FIZ, NEP bits

On 1/24/25 08:27, Peter Maydell wrote: The Armv8.7 FEAT_AFP feature defines three new control bits in the FPCR: * FPCR.AH: "alternate floating point mode"; this changes floating point behaviour in a variety of ways, including: - the sign of a default NaN is 1, not 0 - if FPCR.FZ i

[PATCH v3 24/24] cpus: Remove CPUClass::has_work() handler

All handlers have been converted to SysemuCPUOps::has_work(). Remove CPUClass::has_work along with cpu_common_has_work() and simplify cpu_has_work(), making SysemuCPUOps::has_work handler mandatory. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h

[PATCH v3 15/24] target/ppc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c05c2dc42dc..081fb5bd343 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/c

[PATCH v3 14/24] target/openrisc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..5d80c4aa9ac 100644 --- a/target/openrisc/cpu.c +++ b/target/openr

[PATCH v3 08/24] target/hppa: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4c..d5a58a03cbb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -125,10

[PATCH v3 20/24] target/sh4: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 24a22724c61..80a66e1f1d6 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -82,12 +82,

[PATCH v3 06/24] target/avr: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8a126ff3222..8712813f3e2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -200,6 +200,7 @

Re: [PATCH 26/76] target/arm: Use FPST_FPCR_F16_A64 for halfprec-to-other conversions

On 1/24/25 08:27, Peter Maydell wrote: We should be using the F16-specific float_status for conversions from half-precision, because halfprec inputs never set Input Denormal. Without FEAT_AHP, using the wrong fpst here had no effect, because the only difference between the F16_A64 and A64 fpst i

[PATCH v3 18/24] target/s390x: Restrict I/O handler installers to system emulation

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/s390x/s390x-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index a750e7a343a..6e2c98de97a 100644 --- a/target/s390x/s390x-internal.h +++

[PATCH v3 23/24] target/xtensa: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps, simplifying xtensa_cpu_has_work() by directly using CPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/xtensa

[PATCH v3 22/24] target/tricore: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/tricore/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 95202fadbfd..e4f95876efd 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.

[PATCH v3 12/24] target/microblaze: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f114789abd8..7a90cb3016b 100644 --- a/target/microblaze/cpu.c +++ b/targ

[PATCH v3 21/24] target/sparc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index fbd38ec334a..94e807f9f84 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -7

[PATCH v3 16/24] target/riscv: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé --- Cc: qemu-ri...@nongnu.org --- target/riscv/internals.h | 4 +++- target/riscv/cpu.c | 8 +++- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 67291933f84..213aff31d85 10064

[PATCH v3 19/24] target/s390x: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps, move s390_cpu_has_work() to cpu-system.c so it is only build for system emulation binaries, restrict functions not used anymore on user emulation in interrupt.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/s390x/

[PATCH v3 09/24] target/i386: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps, restrict x86_cpu_pending_interrupt() to system. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.h | 4 ++-- target/i386/cpu.c | 8 +++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/targ

[PATCH v3 17/24] target/rx: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/rx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index aa310bd6144..79b95090e7a 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -187,6 +187,7 @@ sta

[PATCH v3 11/24] target/m68k: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 41dfdf58045..eb7fb4f7e4c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -51,10

[PATCH v3 13/24] target/mips: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps and cpu_mips_hw_interrupts_enabled() to system. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 4 ++-- target/mips/cpu.c | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a

[PATCH v3 04/24] target/alpha: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e1b898e5755..83164a694d8 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -6

[PATCH v3 00/24] cpus: Restrict CPU has_work() handlers to system emulation

Missing review: 16 (I plan to merge this myself once reviewed) Since v2: - Check mandatory SysemuCPUOps handlers in class_post_init() v1 cover: On user emulation, threads always have work to do, and CPUClass::has_work() is never called. Restrict it to system emulation, allowing to simplify a bi

[PATCH v3 02/24] cpus: Un-inline cpu_has_work()

In order to expand cpu_has_work(), un-inline it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 6 +- hw/core/cpu-system.c | 6 ++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cp

[PATCH v3 03/24] cpus: Introduce SysemuCPUOps::has_work() handler

SysemuCPUOps::has_work() is similar to CPUClass::has_work(), but only exposed on system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/sysemu-cpu-ops.h | 4 include/hw/core/tcg-cpu-ops.h| 2 +- hw/core/cpu-system.c | 4 ++

[PATCH v3 07/24] target/hexagon: Remove CPUClass:has_work() handler

Remove as unreachable code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Brian Cain --- target/hexagon/cpu.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0b7fc98f6ce..f77e305d611 100644 --- a/tar

[PATCH 1/2] qom: Declare class_base_init() before class_init()

Since class_base_init() is called *before* class_init(), move its declaration in TypeInfo before class_init() to help a bit. No logical change. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 10 +- qom/object.c | 4 ++-- rust/qemu-api/src/qom.rs | 2 +-

Re: [PATCH 25/76] target/arm: Remove redundant advsimd float16 helpers

On 1/24/25 08:27, Peter Maydell wrote: The advsimd_addh etc helpers defined in helper-a64.c are identical to the vfp_addh etc helpers defined in helper-vfp.c: both take two float16 inputs (in a uint32_t type) plus a float_status* and are simple wrappers around the softfloat float16_* functions.

[PATCH 0/2] qom: Introduce class_post_init() handler

Add a class_post_init() handler to be called by parents *after* child class_init() handler is called. This is necessary to have parent class check children properly set some values or mandatory handlers. Philippe Mathieu-Daudé (2): qom: Declare class_base_init() before class_init() qom: Introd

[PATCH 2/2] qom: Introduce class_post_init() handler

Add a class_post_init() handler to be called by parents *after* child class_init() handler is called. This is necessary to have parent class check children properly set some values or mandatory handlers. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 7 +-- qom/object.

Re: [PATCH 24/76] fpu: allow flushing of output denormals to be after rounding

On 1/24/25 08:27, Peter Maydell wrote: Currently we handle flushing of output denormals in uncanon_normal always before we deal with rounding. This works for architectures that detect tininess before rounding, but is usually not the right place when the architecture detects tininess after roundi

[PATCH v2 11/24] target/m68k: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 41dfdf58045..eb7fb4f7e4c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -51,10

[PATCH v2 13/24] target/mips: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps and cpu_mips_hw_interrupts_enabled() to system. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 4 ++-- target/mips/cpu.c | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a

Re: [PATCH v2 24/24] cpus: Remove CPUClass::has_work() handler

On 25/1/25 17:05, Philippe Mathieu-Daudé wrote: All handlers have been converted to SysemuCPUOps::has_work(). Remove CPUClass::has_work along with cpu_common_has_work() and simplify cpu_has_work(), making SysemuCPUOps::has_work handler mandatory. Reviewed-by: Richard Henderson Signed-off-by: Ph

[PATCH v2 23/24] target/xtensa: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps, simplifying xtensa_cpu_has_work() by directly using CPU env. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/xtensa

[PATCH v2 12/24] target/microblaze: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f114789abd8..7a90cb3016b 100644 --- a/target/microblaze/cpu.c +++ b/targ

[PATCH v2 19/24] target/s390x: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps, move s390_cpu_has_work() to cpu-system.c so it is only build for system emulation binaries, restrict functions not used anymore on user emulation in interrupt.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/s390x/

[PATCH v2 21/24] target/sparc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index fbd38ec334a..94e807f9f84 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -7

[PATCH v2 20/24] target/sh4: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 24a22724c61..80a66e1f1d6 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -82,12 +82,

[PATCH v2 14/24] target/openrisc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b7bab0d7abf..5d80c4aa9ac 100644 --- a/target/openrisc/cpu.c +++ b/target/openr

[PATCH v2 16/24] target/riscv: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé --- Cc: qemu-ri...@nongnu.org --- target/riscv/internals.h | 4 +++- target/riscv/cpu.c | 8 +++- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 67291933f84..213aff31d85 10064

[PATCH v2 04/24] target/alpha: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e1b898e5755..83164a694d8 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -6

[PATCH v2 18/24] target/s390x: Restrict I/O handler installers to system emulation

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/s390x/s390x-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index a750e7a343a..6e2c98de97a 100644 --- a/target/s390x/s390x-internal.h +++

[PATCH v2 24/24] cpus: Remove CPUClass::has_work() handler

All handlers have been converted to SysemuCPUOps::has_work(). Remove CPUClass::has_work along with cpu_common_has_work() and simplify cpu_has_work(), making SysemuCPUOps::has_work handler mandatory. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h

[PATCH v2 17/24] target/rx: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/rx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index aa310bd6144..79b95090e7a 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -187,6 +187,7 @@ sta

[PATCH v2 10/24] target/loongarch: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d611a604704..20aba0e1fff 100644 --- a/target/loongarch/cpu.c +++ b/tar

[PATCH v2 09/24] target/i386: Move has_work() from CPUClass to SysemuCPUOps

Move has_work() from CPUClass to SysemuCPUOps, restrict x86_cpu_pending_interrupt() to system. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.h | 4 ++-- target/i386/cpu.c | 8 +++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/targ

[PATCH v2 02/24] cpus: Un-inline cpu_has_work()

In order to expand cpu_has_work(), un-inline it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 6 +- hw/core/cpu-system.c | 6 ++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cp

[PATCH v2 22/24] target/tricore: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/tricore/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 95202fadbfd..e4f95876efd 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.

[PATCH v2 15/24] target/ppc: Move has_work() from CPUClass to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c05c2dc42dc..081fb5bd343 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/c

[PATCH v2 01/24] cpus: Restrict cpu_has_work() to system emulation

This method is not used on user emulation, because there is always work to do there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/include/hw/core/

[PATCH v2 03/24] cpus: Introduce SysemuCPUOps::has_work() handler

SysemuCPUOps::has_work() is similar to CPUClass::has_work(), but only exposed on system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/sysemu-cpu-ops.h | 4 include/hw/core/tcg-cpu-ops.h| 2 +- hw/core/cpu-system.c | 4 ++

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