On 2025/01/18 2:03, Nicholas Piggin wrote:
The ITR minimum value may be a mis-reading or ambiguity in the spec.
Section 10.2.4.2 says the maximum observable interrupt rate should never
exceed 7813, but that is in context of example of the interval being
programmed to 500. On the other hand 7.4.4
On 2025/01/18 2:28, Nicholas Piggin wrote:
Of the MSI-X PBA pending bits, the PCI Local Bus Specification says:
Software should never write, and should only read
Pending Bits. If software writes to Pending Bits, the
result is undefined.
Log a GUEST_ERROR message if the PBA is written t
To prepare to support another USB PCI Host Controller, make some PCI
configuration dynamic.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci-pci.h | 9 +
hw/usb/hcd-xhci-pci.c | 87 +--
2 files changed, 85 insertions(+), 11 deletions(-)
diff --git
Implement XHCI TR NOOP commands by setting up then immediately
completing the packet.
The IBM AIX XHCI HCD driver uses NOOP commands to check driver and
hardware health, which works after this change.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.c | 28 +++-
1 file
Since last posting, I accounted for feedback from Phil and
others.
- Improved the names of the XHCI register constants
when moving them to the header file.
- Leaving the symbolic cases for unimplemented registers
in the handlers.
- Fixed a bug introduced in a register field calculation
when
The TI TUSB73X0 controller has some interesting differences from NEC,
notably a separate BAR for MSIX, and PM capabilities. The spec is freely
available without sign-up.
This controller is accepted by IBM Power proprietary firmware and
software (when the subsystem IDs are set to Power servers, whi
Add tests which init the host controller registers to the point where
command and event rings, irqs are operational. Enumerate ports and set
up an attached device context that enables device transfer ring to be
set up and tested.
This test does a bunch of things at once and is not yet well librifi
Add support in the test code for running multiple drivers, and add
tests for the qemu-xhci device.
Signed-off-by: Nicholas Piggin
---
tests/qtest/usb-hcd-xhci-test.c | 96 +
1 file changed, 63 insertions(+), 33 deletions(-)
diff --git a/tests/qtest/usb-hcd-xhci-t
This also adds some missing constants rather than open-coding
offsets and sizes.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.h | 16
hw/usb/hcd-xhci.c | 48 ++-
2 files changed, 38 insertions(+), 26 deletions(-)
diff --git a/hw
Run some TR NOOP commands through the transfer ring.
Signed-off-by: Nicholas Piggin
---
tests/qtest/usb-hcd-xhci-test.c | 36 -
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c
index b9
Prepare to use some of these constants in xhci qtest code.
Signed-off-by: Nicholas Piggin
---
hw/usb/hcd-xhci.h | 214 ++
hw/usb/hcd-xhci.c | 450 +++---
2 files changed, 360 insertions(+), 304 deletions(-)
diff --git a/hw/usb/hcd-xhci
On Fri, Jan 17, 2025 at 02:10:14PM -0500, Steven Sistare wrote:
> On 1/17/2025 1:16 PM, Peter Xu wrote:
> > On Fri, Jan 17, 2025 at 09:46:11AM -0800, Steve Sistare wrote:
> > > +/*
> > > + * Return true if ram contents would be lost during CPR.
> > > + * Return false for ram_device because it is re
Hi Marc-André,
I could successfully build all targets with gcc 14.2.0 (using a debian
sid container) with ubsan and asan enabled, and with -O2.
Pierrick
On 1/14/25 22:40, Marc-André Lureau wrote:
Hi
On Tue, Jan 14, 2025 at 8:00 PM Pierrick Bouvier
wrote:
On 1/14/25 02:48, marcandre.lur..
Richard Henderson writes:
> These are not particularly useful outside of optimization passes.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> These defines are not required outside of tcg/tcg.c,
> which includes tcg-target.c.inc before use.
> Reduces the exported symbol set of tcg-target.h.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Benné
Ilya Leoshkevich writes:
>
> Hi,
>
> This series adds the ability to attach GDB to a running qemu-user
> instance. This is useful for debugging multi-process apps.
>
> Patches 1 and 2 implement a small related feature: the ability to
> create individual UNIX sockets for each child process.
>
> P
From: Jared Rossi
This is a small fix to the IPL behavior in case the user has entered an invalid
loadparm. The loadparm is a very specific value, which must be deliberately set
by the user. Therefore, if it is not valid, then it is a mistake in the guest
configuration.
As such, we immediately
From: Jared Rossi
Because the loadparm specifies an exact kernel the user wants to boot, if the
loadparm is invalid it must represent a misconfiguration of the guest. Thus we
should abort the IPL immediately, without attempting to use other devices, to
avoid booting into an unintended guest image
Ilya Leoshkevich writes:
> Allow debugging individual processes in multi-process applications by
> starting them with export QEMU_GDB=/tmp/qemu-%d.sock,suspend=n.
> Currently one would have to attach to every process to ensure the app
> makes progress.
>
> In case suspend=n is not specified, the
Ilya Leoshkevich writes:
> In case an emulated process execve()s another emulated process, bind()
> will fail, because the socket already exists. So try deleting it. Use
> the existing unix_listen() function which does this. Link qemu-user
> with qemu-sockets.c and add the monitor_get_fd() stub.
Steven Sistare writes:
> On 1/17/2025 2:06 PM, Fabiano Rosas wrote:
>> Steven Sistare writes:
>>
>>> On 1/17/2025 10:29 AM, Fabiano Rosas wrote:
Steven Sistare writes:
> On 1/17/2025 9:42 AM, Fabiano Rosas wrote:
>> Steve Sistare writes:
> [...]
>>>
>>> Thank-you for the s
Hello,
I am running on the host with intel alderlake (12'th gen) cpu which is
i7 12700h, running fedora 40, linux kernel 6.12.8, qemu 8.2.8.
I run newest windows 11 as a guest, but this problem traces back at
least to windows 10.
It works, until I enable hyperv. After that, it starts boot
Add a Rust version of qdev_init_clock_in, which can be used in
instance_init. There are a couple differences with the C
version:
- in Rust the object keeps its own reference to the clock (in addition to
the one embedded in the NamedClockList), and the reference is dropped
automatically by ins
Signed-off-by: Paolo Bonzini
---
meson.build | 1 +
rust/hw/char/pl011/src/device.rs | 10 ++-
rust/qemu-api/src/qdev.rs| 116 ---
rust/qemu-api/tests/tests.rs | 5 +-
4 files changed, 102 insertions(+), 30 deletions(-)
diff --git
This is needed for the MemoryRegionOps to be declared as static;
Rust requires static elements to be Sync.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/bindings.rs | 19 ++-
rust/qemu-api/src/irq.rs | 3 +++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git
In practice it has to be implemented always in order to access an
implementation of ClassInitImpl. Make the relationship
explicit in the code.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/qdev.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rust/qemu-api/src/qdev.rs
In some cases, callbacks are optional. Using "Some(function)" and "None"
does not work well, because when someone writes "None" the compiler does
not know what to use for "F" in "Option".
Therefore, adopt () to mean a "null" callback. It is possible to enforce
that a callback is valid by adding
From: Zhao Liu
missing signed-off-by from zhao
---
rust/qemu-api/tests/tests.rs | 56 ++--
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/rust/qemu-api/tests/tests.rs b/rust/qemu-api/tests/tests.rs
index 526c3f4f8ea..5c3e75ed3d5 100644
--- a/rust/q
The basic object lifecycle test can now be implemented using safe code!
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 13 -
rust/qemu-api/src/prelude.rs | 1 +
rust/qemu-api/src/qom.rs | 23 +--
rust/qemu-api/tests/tests.rs |
Unlike regular classes, interface vtables can only be obtained via
object_class_dynamic_cast. Provide a wrapper that allows accessing
the vtable and pass it to a ClassInitImpl implementation, for example
ClassInitImpl.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/prelude.rs | 1 +
rust/q
This is what I have left for qdev bindings, including 1) reference
counting and object creation 2) clocks 3) Resettable 4) MemoryRegionOps.
I have no rush for this series, and I expect HPET to be merged before it.
The documentation is not yet complete (will be fixed) and the API is
limited to what
Add a smart pointer that allows to add and remove references from
QOM objects. It's important to note that while all QOM objects have a
reference count, in practice not all of them have their lifetime guarded
by it. Embedded objects, specifically, are confined to the lifetime of
the owner.
When
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 43 +++---
rust/hw/char/pl011/src/lib.rs| 1 -
rust/hw/char/pl011/src/memory_ops.rs | 36 -
rust/qemu-api/meson.build| 1 +
rust/qemu-api/src/lib.rs | 1 +
rust/qemu-api/src/memory.
On 1/17/2025 2:06 PM, Fabiano Rosas wrote:
Steven Sistare writes:
On 1/17/2025 10:29 AM, Fabiano Rosas wrote:
Steven Sistare writes:
On 1/17/2025 9:42 AM, Fabiano Rosas wrote:
Steve Sistare writes:
[...]
Thank-you for the simple example. I reproduced the failure.
To fix, add "-mach
QEMU currently crashes when you try to inspect the machines based on
TYPE_PC_MACHINE for their properties:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "pc-q35-10.0-machine"}}' \
| ./qemu-system-x86_64 -M
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
One is a trivial, mechanical change to consistenlty use "vCPU". The
other updates some details about the "PAuth" (Pointer Authentication)
feature.
I replaced the "TCG vCPU Features" heading with "PAuth" because of this:
before this change, the section says, it is about "CPU features that are
spec
Signed-off-by: Kashyap Chamarthy
---
docs/system/arm/cpu-features.rst | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
index a5fb929243c..78f18c87a81 100644
--- a/docs/system/arm/cpu-feat
PAuth (Pointer Authentication), a security feature in software, is
relevant for both KVM and QEMU. Relect this fact into the docs:
- For KVM, `pauth` is a binary, "on" vs "off" option. The host CPU
will choose the cryptographic algorithm.
- For TCG, however, along with `pauth`, a couple
On 1/17/2025 1:16 PM, Peter Xu wrote:
On Fri, Jan 17, 2025 at 09:46:11AM -0800, Steve Sistare wrote:
+/*
+ * Return true if ram contents would be lost during CPR.
+ * Return false for ram_device because it is remapped in new QEMU. Do not
+ * exclude rom, even though it is readonly, because the
Steven Sistare writes:
> On 1/17/2025 10:29 AM, Fabiano Rosas wrote:
>> Steven Sistare writes:
>>
>>> On 1/17/2025 9:42 AM, Fabiano Rosas wrote:
Steve Sistare writes:
> Add documentation for the cpr-transfer migration mode.
>
> Signed-off-by: Steve Sistare
> Reviewe
On 17/01/2025 17.41, Philippe Mathieu-Daudé wrote:
On 17/1/25 09:58, Thomas Huth wrote:
On 16/01/2025 00.22, Philippe Mathieu-Daudé wrote:
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove
On 17/01/2025 17.43, Philippe Mathieu-Daudé wrote:
On 17/1/25 10:08, Thomas Huth wrote:
On 16/01/2025 00.22, Philippe Mathieu-Daudé wrote:
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_4[] array, via the 'x-disable-pcie=false'
property. We removed all machines using that array,
This flag is no longer used.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 22 +++---
include/tcg/tcg.h | 2 --
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
0500)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250117
for you to fetch changes up to db1649823d4f27b924a5aa5f9e0111457accb798:
softfloat: Constify helpers returning float_status field (2025-01-17 08:29
Now that we're no longer assigning to TCGOpDef.args_ct,
we can make the array constant.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
tcg/tcg-common.c | 2 +-
tcg/tcg.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff -
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-8-phi...@linaro.org>
---
tcg/mips/tcg-target-has.h | 122 ++
tcg/mips/tcg-target.h | 112 +-
2 files changed, 123 insert
This macro is unused.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/emit.c.inc | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index 785ff63f2a..ab416627b7 100644
--- a/target/i386/tcg/emit.c
In the replacement, drop the TCGType - TCG_TYPE_V64 adjustment,
except for the call to tcg_out_vec_op. Pass type to tcg_gen_op[1-6],
so that all integer opcodes gain the type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
tcg/tcg-inte
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-has.h | 22 --
tcg/s390x/tcg-target.c.inc | 37 ++
These defines are not required outside of tcg/tcg.c,
which includes tcg-target.c.inc before use.
Reduces the exported symbol set of tcg-target.h.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 13 -
tcg/arm/tcg-target.h
The armv6 uxt and sxt opcodes have a 2-bit rotate field
which supports extractions from ofs = {0,8,16,24}.
Special case ofs = 0, len <= 8 as AND.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-has.h | 21 ++--
tcg/arm/tcg-target.c.inc | 5
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-has.h | 16 ++--
tcg/ppc/tcg-target.c.inc | 30
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-has.h | 15 --
tcg/loongarch64/tcg-target.c.inc | 34 ++
TCG_TARGET_HAS_* definitions don't need to be exposed
by "tcg/tcg.h". Only include 'tcg-has.h' when necessary.
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-15-phi...@linaro.org>
---
include/tcg/tcg.h | 2 --
tcg/optimize.c| 1 +
tcg
Extracts which abut bit 32 may use 32-bit shifts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-has.h | 24 +++-
tcg/riscv/tcg-target.c.inc | 16
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
index 0e79e01266..26ce65b6a5 10
We should have checked that the op is supported before
emitting it. The backend cannot be expected to have a
constraint set for unsupported ops.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4
1 file changed, 4 insertions(+)
diff --git a/tcg/tcg.c
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-9-phi...@linaro.org>
---
tcg/ppc/tcg-target-has.h | 124 +++
tcg/ppc/tcg-target.h | 114 +--
2 files changed, 125 insert
From: Philippe Mathieu-Daudé
These helpers don't alter float_status. Make it const.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250116214359.67295-1-phi...@linaro.org>
---
include/fpu/softfloat-helpers.h | 25 ++
The br, mb, goto_tb and exit_tb opcodes do not have
register operands, only constants, flags, or labels.
Remove the special case in opcode_args_ct by including
TCG_OPF_NOT_PRESENT in the flags for these opcodes.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tc
From: Ilya Leoshkevich
These similarly named functions serve different purposes; add
docstrings to highlight them.
Suggested-by: Alex Bennée
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250116213214.5
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-11-phi...@linaro.org>
---
tcg/s390x/tcg-target-has.h | 124 +
tcg/s390x/tcg-target.h | 114 +-
2 files changed, 125 inse
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-has.h | 39 ++
tcg/riscv/tcg-target.c.inc | 34 ++
We're about to change canonicalization of masks as extract
instead of and. Retain the andi expansion here.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64
We already have these assertions during opcode creation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.in
Left-over from commit 623d7e3551a ("util: Add cpuinfo-ppc.c").
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-2-phi...@linaro.org>
---
tcg/ppc/tcg-target.h | 8
1 file changed, 8 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target-has.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index 3397403910..2f45ad614f 100644
--- a/t
Make extract and sextract "unconditional" in the sense
that the opcodes are always present. Rely instead on
TCG_TARGET_HAS_{s}extract_valid, now always defined.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 4
tcg/arm/tcg-targ
When we generalize {s}extract_i32, we'll lose the
specific register constraints on ext8u and ext8s.
It's just as easy to emit a couple of insns instead.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 23 +++
1 file change
In addition, add empty files for mips, sparc64 and tci.
Make the include unconditional within tcg-opc.h.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 4 +---
tcg/aarch64/{tcg-target.opc.h => tcg-target-opc.
Accept AND, ext32u, ext32s extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-has.h | 26 ++
tcg/mips/tcg-target.c.inc | 33 ++
Acked-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-ID: <20250102181601.1421059-3-richard.hender...@linaro.org>
---
tcg/riscv/tcg-target-has.h | 8 +++-
tcg/riscv/tcg-target.c.inc | 11 +--
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg
From: Helge Deller
Add some missing fields which may be parsed by userspace applications.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID:
---
linux-user/sparc/target_proc.h | 20 +++-
1 file changed, 19 insertions(+), 1
Pass TCGOp.type to the output function.
For aarch64 and tci, use this instead of testing TCG_OPF_64BIT.
For s390x, use this instead of testing INDEX_op_deposit_i64.
For i386, use this to initialize rexw.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-7-phi...@linaro.org>
---
tcg/loongarch64/tcg-target-has.h | 113 +++
tcg/loongarch64/tcg-target.h | 102 +---
2 files changed, 114 inser
This is now a direct replacement.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 89 +++-
tcg/aarch64/tcg-target-opc.h.inc | 4 +-
tcg/arm/tcg-target-opc.h.inc | 6 +--
tcg/i386/tcg-target-opc.h.inc
Do not reference TCG_TARGET_HAS_* directly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/emit.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index a2b940a5c3..f30
Extracts which abut bit 32 may use 32-bit shifts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-has.h | 13 +
tcg/sparc64/tcg-target.c.inc | 11 +++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/tcg/sparc64/
From: Ilya Leoshkevich
Currently one-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they generate exceptions, they are not
handled by cpu_restore_state_from_tb().
For x86 this is not a problem, because x86_restore_state_to_opc() only
restores pc and cc, which alr
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-has.h | 49 +++
tcg/tcg-has.h | 12 +---
t
Make deposit "unconditional" in the sense that the opcode is
always present. Rely instead on TCG_TARGET_deposit_valid,
now always defined.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 3 +--
tcg/arm/tcg-target-has.h | 2 +
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-5-phi...@linaro.org>
---
tcg/arm/tcg-target-has.h | 85
tcg/arm/tcg-target.h | 74 +-
2 files changed, 86 insertion
We always provide bswap subroutines, whether they are optimized
using mips32r2 when available or not.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-has.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg/mips/tcg-targe
Acked-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-ID: <20250102181601.1421059-2-richard.hender...@linaro.org>
---
host/include/riscv/host/cpuinfo.h | 5 +++--
util/cpuinfo-riscv.c | 18 --
2 files changed, 19 in
Introduce a new function, opcode_args_ct, to look up the argument
set for an opcode. We lose the ability to assert the correctness
of the map from TCGOpcode to constraint sets at startup, but we can
still validate at runtime upon lookup.
Rename process_op_defs to process_constraint_sets, as it no
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-6-phi...@linaro.org>
---
tcg/i386/tcg-target-has.h | 139 ++
tcg/i386/tcg-target.h | 129 +--
2 files changed, 140 inser
Now that we use a functional interface to query whether the opcode
is supported, we can drop the TCG_OPF_NOT_PRESENT bit mapping from
TCG_TARGET_HAS_foo in tcg-opc.h
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 306 +++-
Allow the backend to make constraint choices based on more parameters.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4 ++--
tcg/aarch64/tcg-target.c.inc | 3 ++-
tcg/arm/tcg-target.c.inc | 3 ++-
tcg/i386/tcg-target.c.in
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-10-phi...@linaro.org>
---
tcg/riscv/tcg-target-has.h | 112 +
tcg/riscv/tcg-target.h | 102 +
2 files changed, 113 inser
Don't reference TCG_TARGET_MAYBE_vec in a public header.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 ---
tcg/tcg.c | 4
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index
Signed-off-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20250108215156.8731-13-phi...@linaro.org>
---
tcg/tci/tcg-target-has.h | 83
tcg/tci/tcg-target.h | 75 +---
2 files changed, 84 insert
Do not reference TCG_TARGET_HAS_* directly.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 0ef3743f3e..6819b
Return C_NotImplemented instead of asserting for opcodes
not implemented by the backend. For now, the assertion
moves to process_op_defs.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 10 ++
tcg/aarch64/tcg-target.c.inc
These are not particularly useful outside of optimization passes.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 4
tcg/tcg-internal.h | 5 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tc
Avoid direct usage of TCG_TARGET_deposit_*_valid.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/emit.c.inc | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index ab416627b
To be used by some integer operations instead of,
or in addition to, a trailing constant argument.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 5d96cdfc30..238c55c9ac 100644
--- a/include/tc
Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint
arrays based on those. Only afterward process the TCGOpcodes and
share those TCGArgConstraint arrays.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 +-
tcg/tcg.c | 27
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 ++-
tcg/tcg.c | 11 +++
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 238c55c9ac..ac0a080b15 100644
--- a/include/tcg
1 - 100 of 297 matches
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