Re: [PATCH v3] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`

15.01.2025 10:58, Li Zhijian via wrote: This assertion always happens when we sanitize the CXL memory device. $ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize It is incorrect to register an MSIX number beyond the device's capability. Increase the device's MSIX number to cover the mailbox

Re: [PATCH v2 01/13] hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriate

17.01.2025 02:39, Bernhard Beschow wrote: Am 15. Januar 2025 12:55:29 UTC schrieb Michael Tokarev : Is this a qemu-stable material? Good question. Given that this part of the code has some further issues [1] I'd rather not alter stable behavior because we might just trade one bug for anoth

Re: [PATCH 2/3] pci: acpi: Windows 'PCI Label Id' bug workaround

On Wed, Jan 15, 2025 at 6:23 PM Igor Mammedov wrote: > > Current versions of Windows call _DSM(func=7) regardless > of whether it is supported or not. It leads to NICs having bogus > 'PCI Label Id = 0', where none should be set at all. > > Also presence of 'PCI Label Id' triggers another Windows b

Re: [PATCH-for-10.1 v2 00/13] hw/arm: Remove virt-2.6 up to virt-2.12 machines

On 16/01/2025 22.13, Philippe Mathieu-Daudé wrote: Hi Peter, On 16/1/25 15:59, Philippe Mathieu-Daudé wrote: The versioned 'virt' machines up to 2.12 been marked as deprecated two releases ago, and are older than 6 years, so according to our support policy we can remove them. Remove associated

[PATCH v4 3/3] coreaudio: Initialize the buffer for device change

Reallocate buffers when the active device change as the required buffer size may differ. Signed-off-by: Akihiko Odaki --- audio/coreaudio.m | 1 + 1 file changed, 1 insertion(+) diff --git a/audio/coreaudio.m b/audio/coreaudio.m index b9e1a952ed37..72a6df0f75ee 100644 --- a/audio/coreaudio.m ++

[PATCH v4 2/3] audio: Add functions to initialize buffers

These functions can be used to re-initialize buffers when hardware parameters change due to device hotplug, for example. Signed-off-by: Akihiko Odaki --- audio/audio_int.h | 2 ++ audio/audio.c | 24 ++-- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/au

[PATCH v4 1/3] coreaudio: Commit the result of init in the end

init_out_device may only commit some part of the result and leave the state inconsistent when it encounters a fatal error or the device gets unplugged during the operation, which is expressed by kAudioHardwareBadObjectError or kAudioHardwareBadDeviceError. Commit the result in the end of the functi

[PATCH v4 0/3] coreaudio fixes

This series contains two fixes for coreaudio. See each one for details. Signed-off-by: Akihiko Odaki --- Changes in v4: - Splitted patch "audio: Add functions to initialize buffers" from patch "coreaudio: Initialize the buffer for device change". - Changed the message of patch "coreaudio: Commi

Re: [PATCH 2/3] pci: acpi: Windows 'PCI Label Id' bug workaround

15.01.2025 15:53, Igor Mammedov wrote: Current versions of Windows call _DSM(func=7) regardless of whether it is supported or not. It leads to NICs having bogus 'PCI Label Id = 0', where none should be set at all. Also presence of 'PCI Label Id' triggers another Windows bug on localized versions

Re: [PATCH v7 1/2] memory: Update inline documentation

On 2025/01/17 1:13, BALATON Zoltan wrote: On Thu, 16 Jan 2025, Peter Maydell wrote: On Tue, 14 Jan 2025 at 19:12, Peter Xu wrote: On Tue, Jan 14, 2025 at 05:42:57PM +, Peter Maydell wrote: There's at least one test in the arm qtests that will hit this. I suspect that you'll find that mos

Re: [PATCH] pci/msix: Fix msix pba read vector poll end calculation

12.12.2024 15:04, Nicholas Piggin wrote: The end vector calculation has a bug that results in polling fewer than required vectors when reading at a non-zero offset in PBA memory. Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll") Signed-off-by: Nicholas Piggin This sm

Re: [PATCH v7 1/2] memory: Update inline documentation

On 2025/01/16 23:33, Peter Xu wrote: On Thu, Jan 16, 2025 at 02:37:38PM +0900, Akihiko Odaki wrote: On 2025/01/16 1:14, Peter Xu wrote: On Thu, Jan 16, 2025 at 12:52:56AM +0900, Akihiko Odaki wrote: Functionally, the ordering of container/subregion finalization matters if some device tries to

Re: [PATCH v2] pci: ensure valid link status bits for downstream ports

03.12.2024 15:19, Sebastian Ott wrote: PCI hotplug for downstream endpoints on arm fails because Linux' PCIe hotplug driver doesn't like the QEMU provided LNKSTA: pcieport :08:01.0: pciehp: Slot(2): Card present pcieport :08:01.0: pciehp: Slot(2): Link Up pcieport :08:01.0:

[PULL 29/50] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-2-e83d797ae...@ri

[PULL 05/50] target/riscv: add shvstvala

From: Daniel Henrique Barboza shvstvala is defined in RVA22 as: "vstval must be written in all cases described above for stval." By "cases describe above" the doc refer to the description of sstvala: "stval must be written with the faulting virtual address for load, store, and instruction page

[PULL 23/50] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu

[PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-3-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 4 tar

[PULL 22/50] target/riscv: Handle Smrnmi interrupt and exception

From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to

[PULL 34/50] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Ati

[PULL 36/50] target/riscv: Invoke pmu init after feature enable

From: Atish Patra The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110

[PULL 11/50] target/riscv: use RISCVException enum in exception helpers

From: Daniel Henrique Barboza Do a cosmetic change in riscv_raise_exception() to change 'exception' type from uint32_t to RISCVException, making it a bit clear that the arg is directly correlated to the RISCVException enum. As a side effect, change 'excp' type from int to RISCVException in gener

[PULL 16/50] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250106102346.1100149-5-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper

[PULL 44/50] target/riscv: Add Smdbltrp CSRs handling

From: Clément Léger Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-7-cle...@rivosinc.com> Signed-off-by: Alistair F

[PULL 32/50] target/riscv: Add properties for counter delegation ISA extensions

From: Atish Patra This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-I

[PULL 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250116223609.81594-1-phi...@linaro.org> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 15 +++ hw/char/trace-events | 4 2 files changed, 7 insertions(

[PULL 13/50] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm extension is finally ratified. And it's much simplier compared to the experimental one. The newer version doesn't allow to specify custom mask or base for pointer masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-

[PULL 18/50] target/riscv: Apply pointer masking for virtualized memory accesses

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-7-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/internals.h | 54 ++

[PULL 31/50] target/riscv: Support generic CSR indirect access

From: Kaiwen Xue This adds the indirect access registers required by sscsrind/smcsrind and the operations on them. Note that xiselect and xireg are used for both AIA and sxcsrind, and the behavior of accessing them depends on whether each extension is enabled and the value stored in xiselect. Co

qemu-devel@nongnu.org

From: Philippe Mathieu-Daudé virt_machine_init() creates the HARTs vCPUs, then later virt_machine_done() calls create_fdt_sockets(), so the latter has access to the first vCPU via: RISCVVirtState { RISCVHartArrayState { RISCVCPU *harts; ... } soc[VIRT_SOCKETS_MAX]; ...

[PULL 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

From: Atish Patra Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-11-e83d797ae...@rivosinc.com> Signed-off-by: Alistair F

[PULL 46/50] target/riscv: Implement Smdbltrp behavior

From: Clément Léger When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-9-cle...@

[PULL 24/50] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disabl

[PULL 30/50] target/riscv: Enable S*stateen bits for AIA

From: Atish Patra As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable correspond

[PULL 42/50] target/riscv: Implement Ssdbltrp exception handling

From: Clément Léger When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-5-cle...@rivosinc.com> Signed-

[PULL 17/50] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-6-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helpe

[PULL 20/50] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-2-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- targe

[PULL 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-8-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.

[PULL 28/50] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegatio

[PULL 25/50] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of MNP

[PULL 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch

From: Clément Léger Add the switch to enable the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-6-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff

[PULL 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior

From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Clément Léger Reviewed-by: Alist

[PULL 08/50] target/riscv: add shvsatpa

From: Daniel Henrique Barboza shvsatpa is defined in RVA22 as: "All translation modes supported in satp must be supported in vsatp." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241218114026.1652

[PULL 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache

From: Jason Chien This commit introduces a translation tag to avoid invalidating an entry that should not be invalidated when IOMMU executes invalidation commands. E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping of single stage translation and a mapping of nested translation

[PULL 37/50] target/riscv: Add implied rule for counter delegation extensions

From: Atish Patra The counter delegation/configuration extensions depend on the following extensions. 1. Smcdeleg - To enable counter delegation from M to S 2. S[m|s]csrind - To enable indirect access CSRs Add an implied rule so that these extensions are enabled by default if the sscfg extensio

[PULL 39/50] target/riscv: Fix henvcfg potentially containing stale bits

From: Clément Léger With the current implementation, if we had the following scenario: - Set bit x in menvcfg - Set bit x in henvcfg - Clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a mi

[PULL 02/50] target/riscv: rvv: speed up small unit-stride loads and stores

From: Craig Blackmore Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Signed-off-by: Crai

[PULL 40/50] target/riscv: Add Ssdbltrp CSRs handling

From: Clément Léger Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-

[PULL 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0

From: Alexey Baturo The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are used in profile specification. Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only Smnpm. Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Message-ID: <202

[PULL 33/50] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20250110-counter_delegation-v5-6-e83d797ae...@rivosinc.com> Signed-o

[PULL 47/50] target/riscv: Add Smdbltrp ISA extension enable switch

From: Clément Léger Add the switch to enable the Smdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-10-cle...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff

[PULL 35/50] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Reviewed

[PULL 09/50] target/riscv: add shgatpa

From: Daniel Henrique Barboza shgatpa is defined in RVA22 as: "For each supported virtual memory scheme SvNN supported in satp, the corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare must also be supported." Claim support for shgatpa since this is always true for TCG. Signe

[PULL 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior

From: Clément Léger When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20250110125441.3208676-8-cle...@rivosin

[PULL 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu

From: Philippe Mathieu-Daudé Keep kvm_riscv_get_timebase_frequency() prototype aligned with the other ones declared in "kvm_riscv.h", have it take a RISCVCPU cpu as argument. Include "target/riscv/cpu-qom.h" which declares the RISCVCPU typedef. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by:

[PULL 00/50] riscv-to-apply queue

The following changes since commit 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5: Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu into staging (2025-01-16 09:03:43 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/

[PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250106102346.1100149-4-baturo.ale...@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 5 +++ target/riscv/cpu_helper.c | 78 ++

[PULL 21/50] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis Message-ID: <20250106054336.1878291-3-frank.ch...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.

[PULL 10/50] target/riscv/tcg: add sha

From: Daniel Henrique Barboza 'sha' is the augmented hypervisor extension, defined in RVA22 as a set of the following extensions: - RVH - Ssstateen - Shcounterenw (always present) - Shvstvala (always present) - Shtvala (always present) - Shvstvecd (always present) - Shvsatpa (always present) - S

[PULL 12/50] target/riscv: add trace in riscv_raise_exception()

From: Daniel Henrique Barboza When using system mode we can get the CPU traps being taken via the 'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of logging/showing exceptions to users. Add a trace in riscv_raise_exception() to allow qemu-riscv(32/64) users to check all exc

[PULL 07/50] target/riscv: add shvstvecd

From: Daniel Henrique Barboza shvstvecd is defined in RVA22 as: "vstvec.MODE must be capable of holding the value 0 (Direct). When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any valid four-byte-aligned address." This is always true for TCG so let's claim support for it. Signed-

[PULL 04/50] target/riscv: add shcounterenw

From: Daniel Henrique Barboza shcounterenw is defined in RVA22 as: "For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Fran

[PULL 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names

From: Craig Blackmore Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Reviewed-by: Richard Henderson Message-ID: <20241218142353.1027938-2-craig.blackm...@embecosm.com> Signed-off-by: Alistair Francis --- targe

[PULL 06/50] target/riscv: add shtvala

From: Daniel Henrique Barboza shtvala is described in RVA22 as: "htval must be written with the faulting guest physical address in all circumstances permitted by the ISA." This is the case since commit 3067553993, so claim support for shtvala. Signed-off-by: Daniel Henrique Barboza Reviewed-b

[PULL 03/50] riscv/gdbstub: add V bit to priv reg

From: Yanfeng Liu This adds virtualization mode (V bit) as bit(2) of register `priv` per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1. Note that GDB may display `INVALID` tag for `priv` reg when V bit is set, this doesn't affect actual access to the bit though. Signed-off-by: Y

Re: [PATCH v2 1/2] tcg: Document tb_lookup() and tcg_tb_lookup()

On 1/16/25 13:31, Ilya Leoshkevich wrote: These similarly named functions serve different purposes; add docstrings to highlight them. Suggested-by: Alex Bennée Signed-off-by: Ilya Leoshkevich --- accel/tcg/cpu-exec.c | 15 ++- include/tcg/tcg.h| 41 ++

Re: [PATCH] softfloat: Constify helpers returning float_status field

On 1/16/25 13:43, Philippe Mathieu-Daudé wrote: These helpers don't alter float_status. Make it const. Signed-off-by: Philippe Mathieu-Daudé --- include/fpu/softfloat-helpers.h | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson

Re: [PATCH v8 2/2] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine

Hi David, Nick, Sorry about not getting back on this for long! On 2/28/24 2:22 AM, David Gibson wrote: On Tue, Feb 27, 2024 at 10:21:23PM +1000, Nicholas Piggin wrote: On Fri Feb 2, 2024 at 12:46 AM AEST, Shivaprasad G Bhat wrote: As per the PAPR, bit 0 of byte 64 in pa-features property indi

[PATCH v9 0/2] ppc: Enable 2nd DAWR support on Power10

Extends the existing watchpoint facility from TCG DAWR0 emulation to DAWR1 on Power10 for powernv in the first patch, and for pseries in the second patch with both TCG and KVM. --- Changelog: v8: https://lore.kernel.org/qemu-devel/170679876639.188422.11634974895844092362.st...@ltc-boston1.aus.stg

[PATCH v9 2/2] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine

As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to set the pa-feature bit

[PATCH v9 1/2] ppc: Enable 2nd DAWR support on Power10 PowerNV machine

Extend the existing watchpoint facility from TCG DAWR0 emulation to DAWR1 on POWER10. Reviewed-by: Nicholas Piggin Reviewed-by: Harsh Prateek Bora Signed-off-by: Shivaprasad G Bhat --- --- target/ppc/cpu.c | 45 +-- target/ppc/cpu.h |6 +++-

Re: [PATCH] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

On Fri, Jan 17, 2025 at 8:37 AM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/char/riscv_htif.c | 15 +++ > hw/char/trace-events | 4 > 2 files changed, 7 insertions(+), 12 deletions(-) > >

Re: [PATCH] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

On Fri, Jan 17, 2025 at 8:37 AM Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/char/riscv_htif.c | 15 +++ > hw/char/trace-events | 4 > 2 files changed, 7 insertions(+), 12 deletions(-) > > diff --g

[PATCH 1/1] cxl/cxl-host: Support creation of a new CXL Host Bridge

This work defines a new cxl host bridge type (TYPE_CXL_HOST). This could be considered as a prototype of an independent cxl host bridge which combines gpex features (ecam, mmio windows & irq) and pxb-cxl features(CHBCR) at meanwhile. The root bus path of CXL_HOST is "0001:00", that would not affec

[PATCH 0/1] cxl/cxl-host: Support creation of a new CXL Host Bridge

Background == Currently the base CXL support for arm platforms is only on Jonathan's patches[1] which have not yet merged into upstream. Some platform like SBSA-REF can be more like a real machine, thus the support of cxl could be meaningful. However, the pxb-cxl-host realization on this pl

Re: [PATCH] hw/cxl: Introduce CXL_T3_MSIX_VECTOR enumeration

On 16/01/2025 18:50, Jonathan Cameron wrote: > On Thu, 16 Jan 2025 01:18:28 + > "Zhijian Li (Fujitsu)" wrote: > >> On 15/01/2025 21:51, Jonathan Cameron wrote: >>> On Wed, 15 Jan 2025 15:58:46 +0800 >>> Li Zhijian wrote: >>> Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specif

Re: [PATCH v2] qemu/compiler: Absorb 'clang-tsa.h'

On 1/16/25 13:11, Philippe Mathieu-Daudé wrote: We already have "qemu/compiler.h" for compiler-specific arrangements, automatically included by "qemu/osdep.h" for each source file. No need to explicitly include a header for a Clang particularity, let the common "qemu/compiler.h" deal with that by

Re: CXL emulation on aarch64

> On Jan 16, 2025, at 19:58, Jonathan Cameron > wrote: > > On Thu, 16 Jan 2025 15:04:53 +0900 > Itaru Kitayama wrote: > >> Hi Jonathan, >> >>> On Jan 14, 2025, at 19:26, Jonathan Cameron >>> wrote: >>> >>> On Tue, 14 Jan 2025 12:03:03 +0900 >>> Itaru Kitayama wrote: >>> Hi Jonath

Re: CXL emulation on aarch64

> On Jan 16, 2025, at 19:58, Jonathan Cameron > wrote: > > On Thu, 16 Jan 2025 15:04:53 +0900 > Itaru Kitayama wrote: > >> Hi Jonathan, >> >>> On Jan 14, 2025, at 19:26, Jonathan Cameron >>> wrote: >>> >>> On Tue, 14 Jan 2025 12:03:03 +0900 >>> Itaru Kitayama wrote: >>> Hi Jonath

[PATCH v6 3/8] user: Introduce user/signal.h

gdbstub needs target_to_host_signal(), so move its declaration to a public header. Reviewed-by: Richard Henderson Reviewed-by: Warner Losh Signed-off-by: Ilya Leoshkevich --- bsd-user/signal-common.h | 1 - bsd-user/signal.c | 1 + include/user/signal.h | 23 +

[PATCH v6 0/8] gdbstub: Allow late attachment

Based-on: <20250116160306.1709518-1-alex.ben...@linaro.org> v5: https://lore.kernel.org/qemu-devel/20250110141255.2328-1-...@linux.ibm.com/ v5 -> v6: Rebase on top of the Alex's changes. v4: https://lore.kernel.org/qemu-devel/20250108202625.149869-1-...@linux.ibm.com/ v4 -> v5: Fix the qemu-user

[PATCH v6 7/8] docs/user: Document the %d placeholder and suspend=n QEMU_GDB features

Reviewed-by: Alex Bennée Signed-off-by: Ilya Leoshkevich --- docs/user/main.rst | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/docs/user/main.rst b/docs/user/main.rst index 80a77f0a0c9..9a1c60448c5 100644 --- a/docs/user/main.rst +++ b/docs/user/main.rst @@

[PATCH v6 4/8] user: Introduce host_interrupt_signal

Attaching to the gdbstub of a running process requires stopping its threads. For threads that run on a CPU, cpu_exit() is enough, but the only way to grab attention of a thread that is stuck in a long-running syscall is to interrupt it with a signal. Reserve a host realtime signal for this, just l

[PATCH v6 5/8] osdep: Introduce qemu_kill_thread()

Add a function for sending signals to individual threads. It does not make sense on Windows, so do not provide an implementation, so that if someone uses it by accident, they will get a linker error. Reviewed-by: Richard Henderson Reviewed-by: Warner Losh Signed-off-by: Ilya Leoshkevich --- in

[PATCH v6 1/8] gdbstub: Allow the %d placeholder in the socket path

Just like for QEMU_LOG_FILENAME, replace %d with PID in the GDB socket path. This allows running multi-process applications with, e.g., export QEMU_GDB=/tmp/qemu-%d.sock. Currently this is not possible, since the first process will cause the subsequent ones to fail due to not being able to bind() t

[PATCH v6 2/8] gdbstub: Try unlinking the unix socket before binding

In case an emulated process execve()s another emulated process, bind() will fail, because the socket already exists. So try deleting it. Use the existing unix_listen() function which does this. Link qemu-user with qemu-sockets.c and add the monitor_get_fd() stub. Note that it is not possible to ha

[PATCH v6 6/8] gdbstub: Allow late attachment

Allow debugging individual processes in multi-process applications by starting them with export QEMU_GDB=/tmp/qemu-%d.sock,suspend=n. Currently one would have to attach to every process to ensure the app makes progress. In case suspend=n is not specified, the flow remains unchanged. If it is speci

[PATCH v6 8/8] tests/tcg: Add late gdbstub attach test

Add a small test to prevent regressions. Make sure that host_interrupt_signal is not visible to the guest. Reviewed-by: Alex Bennée Signed-off-by: Ilya Leoshkevich --- tests/guest-debug/run-test.py | 15 ++-- tests/tcg/multiarch/Makefile.target| 9 - tests/tcg/mult

Re: [PATCH v2 01/13] hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriate

Am 15. Januar 2025 12:55:29 UTC schrieb Michael Tokarev : >11.01.2025 21:36, Bernhard Beschow wrote: >> In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and >> "DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. >> QEMU >> currently misses to set t

Re: [PATCH 08/14] hw/sd/sd: Allow for inverting polarities of presence and write-protect GPIOs

Am 12. Januar 2025 18:06:04 UTC schrieb "Philippe Mathieu-Daudé" : >On 9/1/25 17:20, Bernhard Beschow wrote: >> >> >> Am 9. Januar 2025 11:40:10 UTC schrieb "Philippe Mathieu-Daudé" >> : >>> Hi Bernhard, >>> >>> On 8/1/25 10:25, Bernhard Beschow wrote: Signed-off-by: Bernhard Beschow

[RFC PATCH 1/2] cpus: Introduce const_cpu_env() and const_env_archcpu()

const_cpu_env() is similar to cpu_env() but return a const CPU 'env' state. Same for const_env_archcpu() w.r.t. env_archcpu(). Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 5 + include/hw/core/cpu.h | 6 ++ 2 files changed, 11 insertions(+) diff --git a/incl

[RFC PATCH 2/2] target/arm: Constify lot of helpers taking CPUARMState argument

When methods don't modify the CPUARMState* argument, we can mark it const. This allow enforcing places where the CPU env shouldn't be modified at all, Signed-off-by: Philippe Mathieu-Daudé --- I went via the "modify one and fix until it builds" path, and the result seemed trivial enough, but can

[RFC PATCH 0/2] target/arm: Constify helpers taking CPUARMState arg

Hi, I'd like to enforce some CpuClass handlers to take a const CPUState* argument, but before I need to clean each target. RFC starting with ARM, mostly to get feedback on const_cpu_env() and const_env_archcpu(). Thanks, Phil. Based-on: <20250116214359.67295-1-phi...@linaro.org> "softfloat: Co

[PATCH] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events

Signed-off-by: Philippe Mathieu-Daudé --- hw/char/riscv_htif.c | 15 +++ hw/char/trace-events | 4 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 11a0e1a7b7d..ec5db5a597f 100644 --- a/hw/char/riscv_htif.c +++ b/h

Re: [PULL 0/8] loongarch-to-apply queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/48] virtio,pc,pci: features, fixes, cleanups

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 0/8] Xen regression fixes and cleanups

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v3 0/8] qapi-go: add generator for Golang interfaces

On Fri, Jan 10, 2025 at 11:49:38AM +0100, Victor Toso wrote: > I've pushed this series in my gitlab fork: > https://gitlab.com/victortoso/qapi-go/ > > The fork contains some tests, including tests that were generated from > QAPI's own examples from another generator created for testing, if you > a

[PATCH] softfloat: Constify helpers returning float_status field

These helpers don't alter float_status. Make it const. Signed-off-by: Philippe Mathieu-Daudé --- include/fpu/softfloat-helpers.h | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index

[PATCH v2 1/2] tcg: Document tb_lookup() and tcg_tb_lookup()

These similarly named functions serve different purposes; add docstrings to highlight them. Suggested-by: Alex Bennée Signed-off-by: Ilya Leoshkevich --- accel/tcg/cpu-exec.c | 15 ++- include/tcg/tcg.h| 41 + 2 files changed, 55 insertion

[PATCH v2 2/2] accel/tcg: Call tcg_tb_insert() for one-insn TBs

Currently one-insn TBs created from I/O memory are not added to region_trees. Therefore, when they generate exceptions, they are not handled by cpu_restore_state_from_tb(). For x86 this is not a problem, because x86_restore_state_to_opc() only restores pc and cc, which already have the correct val

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