On Thu, Jan 16, 2025 at 07:46:44AM +0100, Thomas Huth wrote:
> Date: Thu, 16 Jan 2025 07:46:44 +0100
> From: Thomas Huth
> Subject: [PATCH] docs/about: Change notes on x86 machine type deprecation
> into a general one
>
> We now have a general note about versioned machine types getting
> depreca
When an eBPF program cannot be attached, virtio_net_load_ebpf() returns
false, and virtio_net_device_realize() enters the code path to handle
errors because of this, but it causes NULL dereference because no error
is generated.
Change virtio_net_load_ebpf() to return false only when a fatal error
On 15/01/2025 18.10, Philippe Mathieu-Daudé wrote:
The VirtMachineClass::claim_edge_triggered_timers field
was only used by virt-2.8 machine, which got removed.
Remove it and simplify fdt_add_timer_nodes() and build_gtdt().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/virt.h|
On 15/01/2025 18.10, Philippe Mathieu-Daudé wrote:
The VirtMachineClass::no_its field was only used by
virt-2.7 machine, which got removed. Remove it and
simplify virt_instance_init() and virt_acpi_build().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/virt.h| 1 -
hw/arm/vir
On Wed, Jan 15, 2025 at 01:08:28PM -0500, Michael S. Tsirkin wrote:
> The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
>
> Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging
> (2025-01-14 12:46:56 -0500)
>
> are available in the Git reposito
On Thu, Jan 16, 2025 at 12:05:59AM +0100, David Woodhouse wrote:
> On 15 January 2025 23:42:41 CET, "Michael S. Tsirkin" wrote:
> >On Wed, Jan 15, 2025 at 07:15:18PM +0100, David Woodhouse wrote:
> >> On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
> >> > The following changes since c
On 15/01/2025 18.09, Philippe Mathieu-Daudé wrote:
The VirtMachineClass::disallow_affinity_adjustment
field was only used by virt-2.6 machine, which got
removed. Remove it along with the GIC*_TARGETLIST_BITS
definitions, and simplify virt_cpu_mp_affinity().
Signed-off-by: Philippe Mathieu-Daudé
On 15/01/2025 18.09, Philippe Mathieu-Daudé wrote:
This machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") it can now be removed.
Signe
On 15/01/2025 18.09, Philippe Mathieu-Daudé wrote:
The VirtMachineClass::no_pmu field was only used by
virt-2.6 machine, which got removed. Remove it and
simplify machvirt_init().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/virt.h | 1 -
hw/arm/virt.c | 4
2 files
We now have a general note about versioned machine types getting
deprecated and removed at the beginning of the deprecated.rst file,
so we should also have a general note about this in removed-features.rst
(which will also apply to versioned non-x86 machine types) instead of
listing individual old
> > > +impl_vmstate_scalar!(vmstate_info_uint64, u64);
> >
> > What about applying this to "usize" with vmstate_info_uint64?
>
> There's 32-bit hosts too... So one would have to add vmstate_info_ulong
> which is serialized as 64-bit.
>
> We can add it later, but perhaps we could also create a
On 15/01/2025 20.58, Philippe Mathieu-Daudé wrote:
On 6/1/25 06:50, Philippe Mathieu-Daudé wrote:
While I was very enthusiastic when Avocado was presented to
the QEMU community and pushed forward to have it integrated,
time passed and I lost interest. Be honest, remove my R: tag
to not give fake
Hi Jonathan,
> On Jan 14, 2025, at 19:26, Jonathan Cameron
> wrote:
>
> On Tue, 14 Jan 2025 12:03:03 +0900
> Itaru Kitayama wrote:
>
>> Hi Jonathan,
>>
>>> On Jan 10, 2025, at 21:31, Jonathan Cameron
>>> wrote:
>>>
>>> On Fri, 10 Jan 2025 09:20:54 +
>>> "Zhijian Li (Fujitsu)" via wr
On 2025/01/16 0:01, Nicholas Piggin wrote:
The e1000e and igb tests don't clear the msix pending bit after waiting
for it, as it is masked so the irq doesn't get sent. This means all
subsequent waits for the interrupt does not wait or verify the interrupt
was generated, affecting the multiple_tra
On 2025/01/16 1:14, Peter Xu wrote:
On Thu, Jan 16, 2025 at 12:52:56AM +0900, Akihiko Odaki wrote:
Functionally, the ordering of container/subregion finalization matters if
some device tries to a container during finalization. In such a case,
|
^ so
On 2025/01/16 10:17, Jason Wang wrote:
On Wed, Jan 15, 2025 at 1:17 PM Akihiko Odaki wrote:
On 2025/01/13 11:59, Jason Wang wrote:
On Sat, Jan 11, 2025 at 1:43 PM Akihiko Odaki wrote:
Hi Jason,
Can you check this patch again?
I would like to have this if
1) it would be used by libvirt.
On 2025/01/16 2:10, Christian Schoenebeck wrote:
On Wednesday, January 15, 2025 4:37:28 PM CET Akihiko Odaki wrote:
On 2025/01/16 0:14, Christian Schoenebeck wrote:
On Wednesday, January 15, 2025 1:06:55 PM CET Akihiko Odaki wrote:
init_out_device may only commit some part of the result and le
commit 0788a56bd1ae3 ("i386: Make unversioned CPU models be aliases")
introduced 'default_cpu_version' for PCMachineClass. This created three
categories of CPU models:
- Most unversioned CPU models would use version 1 by default.
- For machines 4.0.1 and older that do not support cpu model aliase
From: Yu-Ming Chang
Only check misa.C will cause issues when ext_zca is enabled without
misa.C being set. For example, only enable ext_zce.
Signed-off-by: Yu-Ming Chang
---
target/riscv/op_helper.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/op
On Wed, Jan 15, 2025 at 9:38 PM Ani Sinha wrote:
>
> On Wed, Jan 15, 2025 at 7:08 PM Michael S. Tsirkin wrote:
> >
> > On Wed, Jan 15, 2025 at 11:33:10AM +0530, Ani Sinha wrote:
> > > On Thu, Dec 12, 2024 at 8:19 PM Ani Sinha wrote:
> > > >
> > > > commit 0788a56bd1ae3 ("i386: Make unversioned C
> and the structure of all the blanket implementation is always the same:
>
> pub trait DeviceClassMethods: IsA {...}
> impl DeviceClassMethods for T where T: IsA {}
>
> pub trait DeviceMethods: ObjectDeref
> where
> Self::Target: IsA,
> {...}
> impl DeviceMethods for R where R::Target: IsA {
Supported CPU number can be acquired from function
possible_cpu_arch_ids(), cpu-num property is not necessary and can
be removed.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 13 -
include/hw/intc/loongson_ipi_common.h | 2 ++
2 files ch
There is arch_id and CPUState pointer in IPICore object. With function
cpu_by_arch_id() it can be implemented by parsing IPICore array inside,
rather than possible_cpus array.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 36 +++-
1
Add realize interface for loongarch ipi device.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 19 +++
include/hw/intc/loongarch_ipi.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
i
Add logic cpu index input parameter for function cpu_by_arch_id,
CPUState::cpu_index is logic cpu slot index for possible_cpus.
At the same time it is logic index with LoongsonIPICommonState::IPICore,
here hide access for CPUState::cpu_index directly, it comes from
function cpu_by_arch_id().
Sign
Since cpu number can be acquired from possible_cpu_arch_ids(),
num-cpu property is not necessary. Here remove num-cpu property
for object TYPE_LOONGARCH_IPI object.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 5 -
hw/loongarch/virt.c | 1 -
2 files change
From: Miao Hao
When dump memory content with gva address, software page table walker is
necessary to get responding gpa address.
Here page table walker is added for debugger usage.
Signed-off-by: Miao Hao
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu_helper.c |
With mips64 loongson ipi, num_cpu property is used. With loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.
Here remove num_cpu setting from loongson_ipi_common, and this piece
of code is put into loongson and loongarch ipi separately.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Ma
With mips64 loongson ipi, num_cpu property is used. With loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.
Here remove property num_cpu from loongson_ipi_common, and put it into
loongson and loongarch ipi separately.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
hw/intc/lo
The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into staging
(2025-01-14 12:46:56 -0500)
are available in the Git repository at:
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20250116
for
On 15/01/2025 21:51, Jonathan Cameron wrote:
> On Wed, 15 Jan 2025 15:58:46 +0800
> Li Zhijian wrote:
>
>> Introduce the `CXL_T3_MSIX_VECTOR` enumeration to specify MSIX vector
>> assignments specific to the Type 3 (T3) CXL device.
>>
>> The primary goal of this change is to encapsulate the MSI
On Wed, Jan 15, 2025 at 1:17 PM Akihiko Odaki wrote:
>
> On 2025/01/13 11:59, Jason Wang wrote:
> > On Sat, Jan 11, 2025 at 1:43 PM Akihiko Odaki
> > wrote:
> >>
> >> Hi Jason,
> >>
> >> Can you check this patch again?
> >
> > I would like to have this if
> >
> > 1) it would be used by libvirt.
This patch extends the existing support we have for NVMe with only DoE
to also add support to SPDM over the NVMe Security Send/Recv commands.
With the new definition of the `spdm-trans` argument, users can specify
`spdm_trans=nvme` or `spdm_trans=doe`. This allows us to select the SPDM
transport r
This header contains the transport encoding for an SPDM message that
uses the SPDM over Storage transport as defined by the DMTF DSP0286.
Signed-off-by: Wilfred Mallawa
---
include/system/spdm-socket.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/system/spdm-socket.h
Adds the NVMe Admin Security Send/Receive command support with support
for DMTFs SPDM. The transport binding for SPDM is defined in the
DMTF DSP0286.
Signed-off-by: Wilfred Mallawa
---
hw/nvme/ctrl.c | 203 ++-
hw/nvme/nvme.h | 5 ++
include/
This series adds support for SPDM to be used over the storage transport, as
defined by the DMTF DSP0286 [1] for NVMe. That is, using the admin
NVMe Security Send/Receive commands, support transport for SPDM as per
DSP0286 [1]. The binding specification (DSP0286) is still currently a draft
specifica
This is to support uni-directional transports such as SPDM
over Storage. As specified by the DMTF DSP0286.
Signed-off-by: Wilfred Mallawa
---
backends/spdm-socket.c | 27 ---
include/system/spdm-socket.h | 35 +++
2 files changed, 59
As per the ISA definition, the upper 8 bits in hpmevent are defined
by Sscofpmf for privilege mode filtering and overflow bits while the
lower 56 bits are desginated for platform specific hpmevent values.
For the reset case, mhpmevent value should have zero in lower 56 bits.
Software may set the OF
: 20250115-pmu_minor_fixes-7a2b8e3658e4
--
Regards,
Atish patra
As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.
[1]https://github.com/riscv/riscv-isa-manual/issues/1578
Signed-off-by: Atish Patra
---
target/riscv/cpu_bits.h | 9 ++---
1 file changed, 6
On 1/15/25 15:20, Ilya Leoshkevich wrote:
Currently single-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they generate exceptions, they are not
handled by cpu_restore_state_from_tb(). For x86 this is not a problem,
because x86_restore_state_to_opc() only restores
On Fri, 2025-01-10 at 11:03 +0100, Klaus Jensen wrote:
> On Jan 7 15:29, Wilfred Mallawa via wrote:
> > Adds the NVMe Admin Security Send/Receive command support with
> > support
> > for DMTFs SPDM. The transport binding for SPDM is defined in the
> > DMTF DSP0286.
> >
> > Signed-off-by: Wilfred
On Wed, 2025-01-15 at 15:36 +0100, Arusekk via wrote:
> This commit adds support for the `prctl(PR_SET_SYSCALL_DISPATCH)`
> function in the Linux userspace emulator.
Typo: this should be PR_SET_SYSCALL_USER_DISPATCH.
> It is implemented as a fully host-independent function, by forcing a
> SIGSYS
On 1/15/25 13:16, Philippe Mathieu-Daudé wrote:
On 7/1/25 08:59, Richard Henderson wrote:
To be used by some integer operations instead of, or in addition to,
a trailing constant argument.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
1 file changed, 1 insertion(+)
diff --g
Propagate the %cpu_count from the machine file, allowing
to remove the "hw/boards.h" dependency (which is machine
specific) from loongson3_bootp.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_bootp.h | 1 +
hw/mips/loongson3_bootp.c | 11 ++-
loongson3_bootp.c doesn't contain any target-specific code
and can be build generically, move it to common_ss[].
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/mips/meson.build
The MachineClass::legacy_fw_cfg_order boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it along with:
- FW_CFG_ORDER_OVERRIDE_* definitions
- fw_cfg_set_order_override()
- fw_cfg_reset_order_override()
- fw_cfg_order[]
- rom_set_order_override()
- rom_r
The PCMachineClass::broken_reserved_end field was only used
by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed.
Remove it and simplify pc_memory_init().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 13 +
2 files changed, 5
Propagate %processor_id from mips_loongson3_virt_init() where
we have a reference to the first vCPU, so use it instead of
the &first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_virt.c | 7 +++
1 file changed, 3 insertions(+), 4 dele
Remove one use of the 'current_machine' global.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_virt.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 93700a1612e..46b
Pass the first vCPU as argument, allowing to remove
another &first_cpu global use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loong
Create vCPUs from the last one to the first one.
No need to use the &first_cpu global since we already
have it referenced.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mi
Remove one &first_cpu use in hw/mips/loongson3_bootp.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_bootp.h | 2 +-
hw/mips/loongson3_bootp.c | 5 ++---
hw/mips/loongson3_virt.c | 1 +
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a
MemMapEntry is declared in "exec/hwaddr.h", cpu_to_le32() in
"qemu/bswap.h". These headers are indirectly included via "cpu.h".
Include them explicitly in order to avoid when removing "cpu.h":
In file included from ../../hw/mips/loongson3_bootp.c:27:
hw/mips/loongson3_bootp.h:234:14: error: un
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_bootp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
index 91b58a71a68..1aab26df69e 100644
--- a/hw/mips/loongson3_bootp.c
'loaderparams' is declared statically. Let fw_conf_init()
access its 'cpu_freq' and 'ram_size' fields.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_virt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/mips/loong
main_cpu_reset() is misleadingly named "main": it resets
all vCPUs, with a special case for the first vCPU.
Factor generic_cpu_reset() out of main_cpu_reset(),
allowing to remove one &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/mips/loongson3_virt
Missing review: #2
Since v1:
- Reworked patch 2 (rth)
Propagate values from machine_init() in order to remove
use of globals such &first_cpu and ¤t_machine.
Philippe Mathieu-Daudé (11):
hw/mips/loongson3_virt: Factor generic_cpu_reset() out
hw/mips/loongson3_virt: Invert vCPU creation order
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS was only used by the
hw_compat_2_5[] array, via the 'x-old-msi-offsets=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/vmxnet3.c | 20
Simplify replacing pvscsi_realize() by pvscsi_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/vmw_pvscsi.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi
PVSCSI_COMPAT_DISABLE_PCIE_BIT was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around PVSCSI_COMPAT_DISABLE_PCIE_BIT.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/vmw_pvscsi.c | 44 -
The X86MachineClass::save_tsc_khz boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it and simplify tsc_khz_needed().
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/x86.h | 5 -
hw/i386/x86.c | 1 -
target/i386/machine.c | 5 ++--
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the now unused empty pc_compat_2_5[] array.
Sig
The "fallback" property was only used by the hw_compat_2_5[] array,
as 'fallback=144'. We removed all machines using that array, lets
remove ISA floppy drive 'fallback' property, manually setting the
default value in isabus_fdc_realize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/fdc-is
PVSCSI_COMPAT_OLD_PCI_CONFIGURATION was only used by the
hw_compat_2_5[] array, via the 'x-old-pci-configuration=on'
property. We removed all machines using that array, lets remove
all the code around PVSCSI_COMPAT_OLD_PCI_CONFIGURATION.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/vmw_pvsc
Simplify merging vmxnet3_realize() within vmxnet3_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/vmxnet3.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmx
VMXNET3_COMPAT_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_DISABLE_PCIE.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/vmxnet3.c | 11 +
We removed the implementations in commit 46a2bd52571
("hw/i386/pc: Remove deprecated pc-i440fx-2.3 machine")
but forgot to remove the declarations. Do it now.
Fixes: 46a2bd52571 ("hw/i386/pc: Remove deprecated pc-i440fx-2.3 machine")
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and
pc-i440fx-2.5 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/boards.h | 3 ---
hw/core/machine.c | 9 -
2 files changed, 12 deletions(-)
diff --git a/include/hw/boards.h b/inclu
The pc_compat_2_4[] array was only used by the pc-q35-2.4
and pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 3 ---
hw/i386/pc.c | 19 ---
2 files changed, 22 deletions(-)
diff --git a/include/hw/i3
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove all the code around
E1000_FLAG_MAC.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 63 +
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_4[] array, via the 'x-disable-pcie=false'
property. We removed all machines using that array,
lets remove all the code around VIRTIO_PCI_FLAG_DISABLE_PCIE.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-pci.h | 4 -
VIRTIO_PCI_FLAG_MIGRATE_EXTRA was only used by the
hw_compat_2_4[] array, via the 'migrate-extra=true'
property. We removed all machines using that array,
lets remove all the code around VIRTIO_PCI_FLAG_MIGRATE_EXTRA.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/virtio/virtio-pci.h | 4
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and
pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/boards.h | 3 ---
hw/core/machine.c | 9 -
2 files changed, 12 deletions(-)
diff --git a/include/hw/boards.h b/inclu
The X86CPU::check_cpuid boolean was only set in the
pc_compat_2_4[] array, via the 'check=off' property.
We removed all machines using that array, lets remove
that CPU property and simplify x86_cpu_realizefn().
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 1 -
target/i386/cpu.c
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/
Simplify x86_cpu_realizefn() by passing an Error**
argument to x86_cpu_filter_features().
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 422276
The versioned 'pc' and 'q35' machines up to 2.12 been marked
as deprecated two releases ago, and are older than 6 years,
so according to our support policy we can remove them.
This series only includes the 2.4 and 2.5 machines removal,
as it is a big enough number of LoC removed. Rest will
follow.
Currently single-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they generate exceptions, they are not
handled by cpu_restore_state_from_tb(). For x86 this is not a problem,
because x86_restore_state_to_opc() only restores pc and cc, which are
already correct. Howev
On Wed, 2025-01-15 at 12:28 +1000, Alistair Francis wrote:
> On Wed, Jan 8, 2025 at 12:04 AM Wilfred Mallawa via
> wrote:
> >
> > This is to support uni-directional transports such as SPDM
> > over Storage. As specified by the DMTF DSP0286.
> >
> > Signed-off-by: Wilfred Mallawa
> > ---
> > ba
On 1/15/25 12:32, Philippe Mathieu-Daudé wrote:
On 15/1/25 06:18, Richard Henderson wrote:
On 1/12/25 13:58, Philippe Mathieu-Daudé wrote:
Keep references of all vCPUs created. That allows
to directly access the first vCPU without using the
&first_cpu global.
Signed-off-by: Philippe Mathieu-Da
On 15 January 2025 23:42:41 CET, "Michael S. Tsirkin" wrote:
>On Wed, Jan 15, 2025 at 07:15:18PM +0100, David Woodhouse wrote:
>> On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
>> > The following changes since commit
>> > 7433709a147706ad7d1956b15669279933d0f82b:
>> >
>> > Merge
On Wed, Jan 15, 2025 at 01:06:24AM +, Zhijian Li (Fujitsu) wrote:
> Cced QEMU,
>
> Hi Fan,
>
> I recalled we had a reboot issue[1] months ago
> I guess your issue was caused by some registers not reset during reboot.
>
> [1]
> https://lore.kernel.org/linux-cxl/20240409075846.85370-1-lizhij.
On Wed, Jan 15, 2025 at 07:15:18PM +0100, David Woodhouse wrote:
> On Wed, 2025-01-15 at 13:08 -0500, Michael S. Tsirkin wrote:
> > The following changes since commit 7433709a147706ad7d1956b15669279933d0f82b:
> >
> > Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into
> > stagin
On 7/1/25 09:00, Richard Henderson wrote:
While only mips32r2 has explicit instructions for bswap,
we have built subroutines for bswap for use by qemu_ld/st.
There's no reason not to expose those subroutines for
general purpose use.
Something in the line of this sound simpler to understand to m
On 7/1/25 09:00, Richard Henderson wrote:
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-has.h | 49 +++
tcg/tcg-has.h | 12 ++
mc146818rtc's migration stream is at version 3 since commit
56038ef6234 ("RTC: Update the RTC clock only when reading it")
from 12 years ago, released in QEMU v1.3.0!
No versioned machines are that old, we can safely remove
support for older streams and the qdev_set_legacy_instance_id()
call.
Sign
On 7/1/25 08:59, Richard Henderson wrote:
To be used by some integer operations instead of, or in addition to,
a trailing constant argument.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index
This allows guests to set the CCSR base address. Also store and return
values of the local access window registers but their functionality
isn't implemented.
Signed-off-by: BALATON Zoltan
---
hw/ppc/e500-ccsr.h | 4 +++
hw/ppc/e500.c | 79 --
2 f
On 15/1/25 06:18, Richard Henderson wrote:
On 1/12/25 13:58, Philippe Mathieu-Daudé wrote:
Keep references of all vCPUs created. That allows
to directly access the first vCPU without using the
&first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/loongson3_virt.c | 9 +
On 7/1/25 09:00, Richard Henderson wrote:
Extracts which abut bit 32 may use 32-bit shifts.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-has.h | 24 +++-
tcg/riscv/tcg-target.c.inc | 16
2 files changed, 19 insertions(+), 21 deletions(-)
R
On 7/1/25 09:01, Richard Henderson wrote:
The instruction set does not implement nor with immediate.
There is no reason to pretend that we do.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
Reviewed-by:
Add an option to defer connection to the target monitor, needed by the
cpr-transfer test.
Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
---
tests/qtest/migration/framework.c | 23 ---
tests/qtest/migration/framework.h | 3 +++
2 files changed, 23 insertions(+), 3
On 7/1/25 09:00, Richard Henderson wrote:
Make extract and sextract "unconditional" in the sense
Typo "Make deposit ..."
Reviewed-by: Philippe Mathieu-Daudé
that the opcodes are always present. Rely instead on
TCG_TARGET_deposit_valid, now always defined.
Signed-off-by: Richard Henderson
On 7/1/25 09:00, Richard Henderson wrote:
Make extract and sextract "unconditional" in the sense
that the opcodes are always present. Rely instead on
TCG_TARGET_HAS_{s}extract_valid, now always defined.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-has.h | 4
tcg/arm
On 7/1/25 09:00, Richard Henderson wrote:
This is now a direct replacement.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 89 +++-
tcg/aarch64/tcg-target-opc.h.inc | 4 +-
tcg/arm/tcg-target-opc.h.inc | 6 +--
tcg/i386/tcg-target-
On 7/1/25 09:00, Richard Henderson wrote:
We already have these assertions during opcode creation.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 7/1/25 09:00, Richard Henderson wrote:
When we generalize {s}extract_i32, we'll lose the
specific register constraints on ext8u and ext8s.
It's just as easy to emit a couple of insns instead.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 23 +++
1 fi
On 8/1/25 22:23, Richard Henderson wrote:
On 1/8/25 09:39, Philippe Mathieu-Daudé wrote:
On 7/1/25 08:59, Richard Henderson wrote:
In the replacement, drop the TCGType - TCG_TYPE_V64 adjustment,
except for the call to tcg_out_vec_op. Pass type to tcg_gen_op[1-6],
so that all integer opcodes ga
On 9/1/25 23:57, Philippe Mathieu-Daudé wrote:
On 7/1/25 09:00, Richard Henderson wrote:
The armv6 uxt and sxt opcodes have a 2-bit rotate field
which supports extractions from ofs = {0,8,16,24}.
Special case ofs = 0, len <= 8 as AND.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-h
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