On 1/14/25 08:11, Nicholas Piggin wrote:
On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
Hi Cédric,
Cc'ing Laurent & Richard for user emulation.
...
The deprecation message (see previous patch) was about the
"ppc ``ref405ep`` mac
Hello, Prasad.
Bugs in clang are really very interesting...
This exact patch fixes this exact issue.
What is about applying it?
With best regards,
Dmitry.
On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote:
> On 1/10/25 08:15, Philippe Mathieu-Daudé wrote:
> > Hi Cédric,
> >
> > Cc'ing Laurent & Richard for user emulation.
> >
> ...
> > The deprecation message (see previous patch) was about the
> > "ppc ``ref405ep`` machine". Is that OK w
On 1/9/2025 12:29 PM, Chenyi Qiang wrote:
>
>
> On 1/9/2025 10:55 AM, Alexey Kardashevskiy wrote:
>>
>>
>> On 9/1/25 13:11, Chenyi Qiang wrote:
>>>
>>>
>>> On 1/8/2025 7:20 PM, Alexey Kardashevskiy wrote:
On 8/1/25 21:56, Chenyi Qiang wrote:
>
>
> On 1/8/2025 12:48 P
Hello, Peter.
I beg a pardon, but I guess, we have a misunderstanding here.
The problem is that comparison "if (limit < 0)" will never
be true. Thus, "true" branch is unreachable. According to
the comment below, it was assumed that "limit" may be
negative, and this means, that "QEMU is running to
On Tue Jan 7, 2025 at 8:00 AM AEST, Cédric Le Goater wrote:
> Hello,
>
> On 12/10/24 04:04, Nicholas Piggin wrote:
> > This series makes a bunch of fixes and improvements to the HOMER and
> > OCC unit models for powernv. It gets OPAL OCC code happier again,
>
> Nice. I had similar changes exposing
The line "hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);" was removed
because the same operation is performed later in the address calculation.
This change improves code clarity and avoids unnecessary operations.
Signed-off-by: Huang Borong
---
hw/intc/riscv_aplic.c | 1 -
1 file changed, 1 d
>I removed the lines above, as we don't want to include the changelog or
rebase notes in the commit message
Sure, sorry for that
Thank you Alistair and Daniel!
вт, 14 янв. 2025 г. в 04:43, Alistair Francis :
> On Tue, Jan 14, 2025 at 5:45 AM wrote:
> >
> > From: Alexey Baturo
> >
> > Rebased a
Hi Jonathan,
> On Jan 10, 2025, at 21:31, Jonathan Cameron
> wrote:
>
> On Fri, 10 Jan 2025 09:20:54 +
> "Zhijian Li (Fujitsu)" via wrote:
>
>> On 10/01/2025 13:29, Itaru Kitayama wrote:
>>> Hi,
>>> Is anybody working on the CXL emulation on aarch64?
>>
>> I'm not currently working on
On 1/13/2025 6:56 PM, David Hildenbrand wrote:
> On 13.12.24 08:08, Chenyi Qiang wrote:
>> As guest_memfd is now managed by guest_memfd_manager with
>> RamDiscardManager, only block uncoordinated discard.
>>
>> Signed-off-by: Chenyi Qiang
>> ---
>> system/physmem.c | 2 +-
>> 1 file changed,
On Tue, Jan 14, 2025 at 5:45 AM wrote:
>
> From: Alexey Baturo
>
> Rebased against alistair/riscv-to-apply.next
>
> [v1]:
I removed the lines above, as we don't want to include the changelog
or rebase notes in the commit message
> The Zjpm v1.0 spec states there should be Supm and Sspm extensio
On 1/13/2025 6:23 AM, Xu Yilun wrote:
> On Mon, Jan 13, 2025 at 11:34:44AM +0800, Chenyi Qiang wrote:
>>
>>
>> On 1/10/2025 5:50 AM, Xu Yilun wrote:
>>> On Fri, Jan 10, 2025 at 05:00:22AM +0800, Xu Yilun wrote:
>>
>> https://github.com/aik/qemu/commit/3663f889883d4aebbeb0e4422f7be5e357e2
Thanks David for your review!
On 1/13/2025 6:54 PM, David Hildenbrand wrote:
> On 08.01.25 11:56, Chenyi Qiang wrote:
>>
>>
>> On 1/8/2025 12:48 PM, Alexey Kardashevskiy wrote:
>>> On 13/12/24 18:08, Chenyi Qiang wrote:
As the commit 852f0048f3 ("RAMBlock: make guest_memfd require
uncoor
On Fri, Jan 10, 2025 at 10:55 PM Clément Léger wrote:
>
> A double trap typically arises during a sensitive phase in trap handling
> operations — when an exception or interrupt occurs while the trap
> handler (the component responsible for managing these events) is in a
> non-reentrant state. This
在2025年1月13日一月 下午7:55，Philippe Mathieu-Daudé写道：
> v2:
> - Add documentation
> - Reorder propagation to reduce code churn around &first_cpu
>
> v1:
> - Keep references to vCPUs in CPS and MaltaState,
> - Refactor the MIPS Bootloader API to take CPU argument
> - Access first CPU propagate from mach
On Fri, Jan 10, 2025 at 12:33:59PM -0800, Pierrick Bouvier wrote:
> This attribute is not recognized by clang.
>
> An investigation has been performed to ensure this attribute has no
> effect on layout of structures we use in QEMU [1], so it's safe to
> remove now.
>
> In the future, we'll forbid
Dmitry Osipenko writes:
> Support asynchronous fencing feature of virglrenderer. It allows Qemu to
> handle fence as soon as it's signalled instead of periodically polling
> the fence status. This feature is required for enabling DRM context
> support in Qemu because legacy fencing mode isn't sup
On 1/13/25 13:19, Alex Bennée wrote:
Pierrick Bouvier writes:
On 1/12/25 22:26, Thomas Huth wrote:
On 11/01/2025 16.47, Philippe Mathieu-Daudé wrote:
On 10/1/25 21:37, Pierrick Bouvier wrote:
On 1/10/25 12:33, Pierrick Bouvier wrote:
For now, it was only possible to build plugins using GCC
Pierrick Bouvier writes:
> On 1/12/25 22:26, Thomas Huth wrote:
>> On 11/01/2025 16.47, Philippe Mathieu-Daudé wrote:
>>> On 10/1/25 21:37, Pierrick Bouvier wrote:
On 1/10/25 12:33, Pierrick Bouvier wrote:
> For now, it was only possible to build plugins using GCC on Windows.
> Howev
Peter Maydell writes:
> On Fri, 10 Jan 2025 at 16:28, Peter Maydell wrote:
>>
>> On Thu, 19 Dec 2024 at 18:32, Pierrick Bouvier
>> wrote:
>> >
>> > qemu-system-aarch64 default pointer authentication (QARMA5) is expensive,
>> > we
>> > spent up to 50% of the emulation time running it (when usin
Bug #2594 is about a failure during migration after a cpu hotplug. Add
a test that covers that scenario. Start the source with -smp 2 and
destination with -smp 3, plug one extra cpu to match and migrate.
The issue seems to be a mismatch in the number of virtqueues between
the source and destinatio
On Fri, Jan 10, 2025 at 7:19 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Thu, Jan 9, 2025, 5:34 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > On Fri, Dec 20, 2024 at 9:15 AM Markus Armbruster
> wrote:
> >> >
> >> >> John Snow writes:
> >> >>
> >> >> > This
On 12/9/24 10:30, Pierrick Bouvier wrote:
This series extends our documentation with new pages to help developers
onboarding on QEMU. It focuses on providing a big picture of QEMU (to a
modest extend).
As such, it was written to be simple, short, easy to understand, and pointing to
more details.
On 1/13/25 11:32, Pierrick Bouvier wrote:
On 1/13/25 04:34, Peter Maydell wrote:
On Fri, 10 Jan 2025 at 16:28, Peter Maydell wrote:
On Thu, 19 Dec 2024 at 18:32, Pierrick Bouvier
wrote:
qemu-system-aarch64 default pointer authentication (QARMA5) is expensive, we
spent up to 50% of the emul
On 1/12/25 22:26, Thomas Huth wrote:
On 11/01/2025 16.47, Philippe Mathieu-Daudé wrote:
On 10/1/25 21:37, Pierrick Bouvier wrote:
On 1/10/25 12:33, Pierrick Bouvier wrote:
For now, it was only possible to build plugins using GCC on Windows.
However,
windows-aarch64 only supports Clang.
This bi
On Fri, Dec 20, 2024 at 8:25 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Signed-off-by: John Snow
> > ---
> > docs/sphinx/qapidoc.py | 47 ++
> > 1 file changed, 47 insertions(+)
> >
> > diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc
Propagate the target specific CPU env to the locally
declared bl_gen_nop() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index e57d5c3278f..a54af8160ef 1
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u32(), bl_gen_write_u64() and
bl_gen_write_ulong() functions.
For the Malta machine in bl_setup_gt64120_jump_kernel(),
pass its first CPU (the one we want to start running the
bootloader).
Signed-off-by: Philippe Math
Propagate the target specific CPU env to the locally
declared bl_gen_li() and bl_gen_dli() functions.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
in
Since create_cpu_without_cps() creates the vCPUs iterating
up to the machine SMP count, it knows the first CPU is
created upon the first iteration, at index #0 :)
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --g
Propagate the target specific CPU env to the locally
declared bl_gen_sw() and bl_gen_sd() functions.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index
Propagate the target specific CPU env to the locally
declared bl_gen_dsll() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index a0fc840e89f..e57d5c327
Propagate a CPU to gen_firmware(). Since we expect the first CPU
to run the firmware, get it from the CPS in boston_mach_init(),
resolving it using its QOM path.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/
Propagate the target specific CPU env to the locally
declared bootcpu_supports_isa() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index a
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index f02e5aabe48..1969610224d 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -51,7 +51,7 @@ typedef enum
"exec/hwaddr.h" defines:
typedef uint64_t hwaddr;
typedef struct MemMapEntry {
hwaddr base;
hwaddr size;
} MemMapEntry;
Since MemMapEntry::base is always of type uint64_t,
we can directly use bl_gen_write_u64().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 12
Document bl_gen_write_u[32,64,long]() and bl_gen_jump_[to,kernel]()
prototypes.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 50
1 file changed, 50 insertions(+)
diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootload
Propagate the target specific CPU env to the locally
declared bl_gen_load_ulong() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootlo
When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. In particular, this allow to remove one global
&first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cps.h | 1 +
hw/mips/cps.c | 4 +++-
2 files changed, 4 in
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_jump_to() and bl_gen_jump_kernel() functions.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 6 --
hw/mips/bootloader.c | 6 +++---
hw/mips/boston.c | 2 +-
hw/mips/fuloong
Propagate MaltaState to bl_setup_gt64120_jump_kernel() so
it can access the MaltaState::cpus[] array.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ec8fd954b4b..f7eb990c
Propagate the target specific CPU env to the locally
declared bl_gen_jalr() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 288dccce473..a0fc840e89f
mips_fuloong2e_init() created the vCPU so has its reference,
propagate it to write_bootloader(), removing the &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/fuloong2e.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloon
v2:
- Add documentation
- Reorder propagation to reduce code churn around &first_cpu
v1:
- Keep references to vCPUs in CPS and MaltaState,
- Refactor the MIPS Bootloader API to take CPU argument
- Access first CPU propagate from machine_init()
Based-on: <20250112215835.29320-1-phi...@linaro.org>
Pass MaltaState as argument to write_bootloader() so next
commit can propagate it to bl_setup_gt64120_jump_kernel().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 09
When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. This will be helpful to remove &first_cpu uses
in few commits.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
From: Alexey Baturo
Rebased against alistair/riscv-to-apply.next
[v1]:
The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are
used in profile specification.
Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only
Smnpm.
Signed-off-by: Alexey Baturo
On 1/13/25 04:34, Peter Maydell wrote:
On Fri, 10 Jan 2025 at 16:28, Peter Maydell wrote:
On Thu, 19 Dec 2024 at 18:32, Pierrick Bouvier
wrote:
qemu-system-aarch64 default pointer authentication (QARMA5) is expensive, we
spent up to 50% of the emulation time running it (when using TCG).
Sw
On Mon, Dec 16, 2024 at 8:15 AM Markus Armbruster wrote:
> John Snow writes:
>
> > The code as written can't handle if a header isn't found, because `node`
> > will be uninitialized.
>
> Yes, we initialize @node only if we have a heading.
>
> Made me wonder what happens when we don't. So I dele
Hi Alexey,
On 1/11/25 10:06 AM, baturo.ale...@gmail.com wrote:
From: Alexey Baturo
The Zjpm v1.0 spec states there should be Supm and Sspm extensions that are
used in profile specification.
Enabling Supm extension enables both Ssnpm and Smnpm, while Sspm enables only
Smnpm.
Signed-off-by: A
On 13/1/25 01:47, Philippe Mathieu-Daudé wrote:
- Refactor the MIPS Bootloader API to take CPU argument
Philippe Mathieu-Daudé (23):
hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa()
hw/mips/bootloader: Propagate CPU env to bl_gen_nop()
hw/mips/bootloader: Propagate C
13.01.2025 19:26, Alex Bennée wrote:
Michael Tokarev writes:
Ghrm. 46 recipients seems to be quite a bit too aggressive..
I think git-publish just accumulates Cc's from each run for a given
branch. While I can reset the version counter I'm not sure where I can
reset the Cc list from.
I nev
From: Akihiko Odaki
Check the same code once in the common helper.
Signed-off-by: Akihiko Odaki
[PMD: Split from bigger patch, part 5/6]
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-Id: <20250110091908.64454-6-phi...@linaro.org>
---
hw/core/qdev-hotplug.c | 8 +++
From: Akihiko Odaki
Introduce qdev_hotplug_unplug_allowed_common() to hold
common code between checking hot-plug/unplug is allowed.
Signed-off-by: Akihiko Odaki
[PMD: Split from bigger patch, part 3/6]
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-Id: <2025011009190
From: Akihiko Odaki
Check the same code once in the common helper.
Signed-off-by: Akihiko Odaki
[PMD: Split from bigger patch, part 4/6]
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-Id: <20250110091908.64454-5-phi...@linaro.org>
---
hw/core/qdev-hotplug.c | 9 +++
From: Akihiko Odaki
In preparation of checking the parent bus is hot(un)pluggable
in a few commits, pass a 'bus' argument to qdev_hotplug_allowed().
Signed-off-by: Akihiko Odaki
[PMD: Split from bigger patch, part 1/6]
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-I
The following changes since commit e8aa7fdcddfc8589bdc7c973a052e76e8f999455:
Merge tag 'pull-target-arm-20250113' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2025-01-13
09:43:48 -0500)
are available in the Git repository at:
https://github.com/philmd/qemu.g
From: Akihiko Odaki
Commit 03fcbd9dc508 ("qdev: Check for the availability of a hotplug
controller before adding a device") says:
> The qdev_unplug() function contains a g_assert(hotplug_ctrl)
> statement, so QEMU crashes when the user tries to device_add +
> device_del a device that does not
From: Jiaxun Yang
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting differences on scripting.
Examples of b4:
```
$ b4 prep --check
Checking patches using
From: Akihiko Odaki
Factor qdev_hotunplug_allowed() out of qdev_unplug().
Start checking the device is not blocked.
Signed-off-by: Akihiko Odaki
[PMD: Split from bigger patch, part 2/6]
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Message-Id: <20250110091908.64454-3-phi...
On 12/1/25 22:00, Phil Dennis-Jordan wrote:
This patch set introduces a new ARM and macOS HVF specific machine type
called "vmapple". There are also some patches for fixing XHCI spec
compliance issues and adding a workaround to a quirk in the macOS guest's
XHCI driver.
Phil Dennis-Jordan (3):
On 10/1/25 10:19, Philippe Mathieu-Daudé wrote:
Akihiko Odaki (6):
hw/qdev: Pass bus argument to qdev_hotplug_allowed()
hw/qdev: Factor qdev_hotunplug_allowed() out
hw/qdev: Introduce qdev_hotplug_unplug_allowed_common()
hw/qdev: Check DevClass::hotpluggable in hotplug_unplug_allowed
On Fri, Jan 10, 2025 at 10:09:38AM -0300, Fabiano Rosas wrote:
> Shivam Kumar writes:
>
> > Even if a live migration fails due to some reason, migration status
> > should not be set to MIGRATION_STATUS_FAILED until migrate fd cleanup
> > is done, else the client can trigger another instance of mi
Michael Tokarev writes:
> Ghrm. 46 recipients seems to be quite a bit too aggressive..
I think git-publish just accumulates Cc's from each run for a given
branch. While I can reset the version counter I'm not sure where I can
reset the Cc list from.
> 08.01.2025 15:10, Alex Bennée wrote:
>> Tim
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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On 13/1/25 13:28, Igor Mammedov wrote:
On Sun, 12 Jan 2025 23:16:40 +0100
Philippe Mathieu-Daudé wrote:
QDev objects created with object_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Zhao Liu
Message
On Sat, Jan 11, 2025 at 01:15:24PM +0900, Akihiko Odaki wrote:
> On 2025/01/11 0:18, Peter Xu wrote:
> > On Fri, Jan 10, 2025 at 05:43:15PM +0900, Akihiko Odaki wrote:
> > > On 2025/01/10 4:37, Peter Xu wrote:
> > > > On Thu, Jan 09, 2025 at 02:29:21PM -0500, Peter Xu wrote:
> > > > > On Thu, Jan 0
On 13/1/25 07:53, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 2/1/25 23:53, Jiaxun Yang wrote:
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting diffe
Hi Stefan,
Please drop this PR since Igor made a comment on a patch,
Thanks!
On 12/1/25 23:16, Philippe Mathieu-Daudé wrote:
The following changes since commit 3214bec13d8d4c40f707d21d8350d04e4123ae97:
Merge tag 'migration-20250110-pull-request' of
https://gitlab.com/farosas/qemu into sta
Ghrm. 46 recipients seems to be quite a bit too aggressive..
08.01.2025 15:10, Alex Bennée wrote:
Time will not advance if the system is paused or there are no timer
events set for the future. In absence of pending timer events
advancing time would make no difference the system state. Attempting
13.01.2025 16:03, Fabiano Rosas wrote:
Michael Tokarev writes:
13.01.2025 11:19, Thomas Huth wrote:
On 13/01/2025 08.51, Michael Tokarev wrote:
Picked up:
1/7 migration: Add more error handling to analyze-migration.py
3/7 migration: Fix parsing of s390 stream
7/7 s390x: Fix CSS m
Philippe Mathieu-Daudé writes:
> Respin of Fabiano patch using g_autofree,
> and clarifying method docstrings.
>
> Fabiano Rosas (1):
> block: Fix leak in send_qmp_error_event
>
> Philippe Mathieu-Daudé (1):
> block: Improve blk_get_attached_dev_id() docstring
>
> include/sysemu/block-backen
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
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Hi,
I ran into the issue with only one thread being stopped on a
breakpoint hit [1] again [2]. While a proper solution to this includes
kicking all threads using a reserved host signal and parking them, and
is partially in review and partially in the works, this small series
resolves most of the p
From: Tigran Sogomonian
The value of an arithmetic expression
'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject
to overflow because its operands are not cast to
a larger data type before performing arithmetic. Thus, need
to cast rpm to uint64_t.
Found by Linux Verification Center (linuxtesti
From: Philippe Mathieu-Daudé
Re-indent ASM comments adding the 'loop:' label.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Signed-off-by: Peter Maydell
---
tests/qtest/boot-serial-test.c | 18 +-
1 file changed, 9 insertions
The pauth-3 test explicitly tests that a computation of the
pointer-authentication produces the expected result. This means that
it must be run with the QARMA5 algorithm.
Explicitly set the pauth algorithm when running this test, so that it
doesn't break when we change the default algorithm the '
From: Philippe Mathieu-Daudé
In the next commit we are going to use a different value
for the $w1 register, maintaining the same $x2 value. In
order to keep the next commit trivial to review, set $x2
before $w1.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by:
From: Pierrick Bouvier
Before changing default pauth algorithm, we need to make sure current
default one (QARMA5) can still be selected.
$ qemu-system-aarch64 -cpu max,pauth-qarma5=on ...
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-id: 20241219183211.3493974-2-pierr
From: Pierrick Bouvier
Pointer authentication on aarch64 is pretty expensive (up to 50% of
execution time) when running a virtual machine with tcg and -cpu max
(which enables pauth=on).
The advice is always: use pauth-impdef=on.
Our documentation even mentions it "by default" in
docs/system/intr
From: Philippe Mathieu-Daudé
The tests using the PL011 UART of the virt and raspi machines
weren't properly enabling the UART and its transmitter previous
to sending characters. Follow the PL011 manual initialization
recommendation by setting the proper bits of the control register.
Update the A
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Message-id: 20241219183211.3493974-4-pierrick.bouv...@linaro.org
[PMM: Removed a paragraph about using non-versioned models.]
Signed-off-by: Peter Maydell
---
docs/system/arm/virt.rst | 4
1 file changed, 4 insertions(+)
diff --git a
helper.c includes some small TCG helper functions used for mostly
arithmetic instructions. These are TCG only and there's no need for
them to be in the large and unwieldy helper.c. Move them out to
their own source file in the tcg/ subdirectory, together with the
op_addsub.h multiply-included tem
From: Philippe Mathieu-Daudé
Since registers are not modified, we don't need
to refill their values. Directly jump to the previous
store instruction to keep filling the TXDAT register.
The equivalent C code remains:
while (true) {
*UART_DATA = 'T';
}
Signed-off-by: Philippe Mathieu-D
From: Anastasia Belova
1 << 31 is casted to uint64_t while bitwise and with val.
So this value may become 0x8000 but only
31th "start" bit is required.
This is not possible in practice because the MemoryRegionOps
uses the default max access size of 4 bytes and so none
of the upper by
mu-arm.git
tags/pull-target-arm-20250113
for you to fetch changes up to 435d260e7ec5ff9c79e3e62f1d66ec82d2d691ae:
docs/system/arm/virt: mention specific migration information (2025-01-13
12:35:35 +)
target-arm queue:
* hw/
If multiple threads hit a breakpoint at the same time, GDB gets
confused [1]. Prevent this situation by stopping the other threads once
a thread hits a breakpoint.
[1] https://sourceware.org/bugzilla/show_bug.cgi?id=32023
Signed-off-by: Ilya Leoshkevich
---
gdbstub/user.c | 2 ++
1 file changed
gdb_handlesig() uses current_cpu.
Signed-off-by: Ilya Leoshkevich
---
bsd-user/main.c | 2 ++
linux-user/main.c| 2 ++
linux-user/syscall.c | 1 +
3 files changed, 5 insertions(+)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 0a5bc578365..aa052e515c9 100644
--- a/bsd-user/main.c
Add a macro that produces a start_exclusive() / end_exclusive() pair.
Useful to guarantee an exit from an exclusive section in large
functions.
Signed-off-by: Ilya Leoshkevich
---
include/hw/core/cpu.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/hw/core/cpu.h b/inclu
Michael Tokarev writes:
> 13.01.2025 11:19, Thomas Huth wrote:
>> On 13/01/2025 08.51, Michael Tokarev wrote:
>
>>> Picked up:
>>>
>>> 1/7 migration: Add more error handling to analyze-migration.py
>>> 3/7 migration: Fix parsing of s390 stream
>>> 7/7 s390x: Fix CSS migration
>>>
>>> but st
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 9.2 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/generic_event_
The GHES migration logic at GED should now support HEST table
location too.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
i
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the ack, which needs a reset before next error.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table
The current code is actually dependent on having just one error
structure with a single source.
As the number of sources should be arch-dependent, as it will depend on
what kind of synchronous/assynchronous notifications will exist, change
the logic to dynamically build the table.
Yet, for a prop
(patch resent as c/c ML was missing)
This series was part of the previous PR to add generic error injection
support on GHES. It depends on a cleanup patch series sent in December,
pending merge:
https://lore.kernel.org/qemu-devel/cover.1733297707.git.mchehab+hua...@kernel.org/T/#t
It contai
Store HEST table address at GPA, placing its content at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
---
Change from v8:
- hest_addr_lr is now pointing to the error source size and data.
---
hw/acpi/ghes.c | 17 -
include/hw
Fabiano Rosas writes:
> Michael Tokarev writes:
>
>> 13.01.2025 11:19, Thomas Huth wrote:
>>> On 13/01/2025 08.51, Michael Tokarev wrote:
>>
Picked up:
1/7 migration: Add more error handling to analyze-migration.py
3/7 migration: Fix parsing of s390 stream
7/7 s390
Hello,
On Tue, 7 Jan 2025, Michael Tokarev wrote:
Hi!
For some time, qemu package in debian carries several patches for
roms/u-boot-sam460ex,
fixing a number of issues. It'd be nice to have them in the official
repository.
I didn't applied these yet because I still intend to update to the
On Fri, 10 Jan 2025 10:19:02 +0100
Philippe Mathieu-Daudé wrote:
> Akihiko's v4 patch was doing too many things at once to
> my taste, so I split it to follow dumbly each steps.
> https://lore.kernel.org/qemu-devel/20250104-bus-v4-1-244cf1c6e...@daynix.com/
refactoring in some cases would lead t
Michael Tokarev writes:
> 03.12.2024 15:49, Shameer Kolothum via wrote:
>> From Commit 90fa121c6c07 ("migration/multifd: Inline page_size and
>> page_count") onwards page_size is not part of MutiFD*Params but uses
>> an inline constant instead.
>>
>> However, it missed updating an old usage, ca
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