13.01.2025 09:39, Thomas Huth wrote:
On 12/01/2025 15.29, Michael Tokarev wrote:
# starting QEMU: exec ./qemu-system-s390x -qtest unix:/tmp/ qtest-1137270.sock -qtest-log /dev/null -chardev socket,path=/tmp/
qtest-1137270.qmp,id=char0 -mon chardev=char0,mode=control -display none - audio none
Zhaoxin CPUs (including vendors "Shanghai" and "Centaurhauls") handle the
CMPLegacy bit similarly to Intel CPUs. Therefore, this commit masks the
CMPLegacy bit in CPUID[0x8001].ECX for Zhaoxin CPUs, just as it is done
for Intel CPUs.
AMD uses the CMPLegacy bit (CPUID[0x8001].ECX.bit1) alon
Zhaoxin currently uses two vendors: "Shanghai" and "Centaurhauls".
It is important to note that the latter now belongs to Zhaoxin. Therefore,
this patch replaces CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1.
The previous CPUID_VENDOR_VIA macro was only defined but never used in
QEMU, making this ch
This patch series introduces a new CPU model, Zhaoxin YongFeng, which is
Zhaoxin's latest server processor. Additionally, it consolidates vendor naming
within QEMU: since both " Shanghai " and "Centaurhauls" now belong to
Zhaoxin, the logic has been updated to treat "Centaurhauls" as part of the
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai
Reviewed-by:
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai
Reviewed-by: Zhao Liu
---
target/i386/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386/cpu.h b/target/i38
Philippe Mathieu-Daudé writes:
> On 2/1/25 23:53, Jiaxun Yang wrote:
>> b4 [1] is a convenient tool to manage patch series with mailing list
>> working flow.
>> Add a project default config file to match QEMU's mailing list conventions
>> as well as adopting differences on scripting.
>> Examples
On 10/01/2025 21.54, Pierrick Bouvier wrote:
On 1/10/25 08:30, Peter Maydell wrote:
On Thu, 19 Dec 2024 at 18:32, Pierrick Bouvier
wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/virt.rst | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/docs/s
The timer controller include 8 sets of 32-bit decrement counters, based on
either PCLK or 1MHZ clock and the design of timer controller between AST2600
and AST2700 are almost the same.
TIMER0 – TIMER7 has their own individual control and interrupt status register.
In other words, users are able to
The register set have a significant change in AST2700. The TMC00-TMC3C
are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional,
TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1,
respectively.
Besides, each TIMER has their own control and interrupt status regi
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3
v1:
- Support timer for AST2700
- Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write"
callback functions and "aspeed_2700_timer_ops" memory
region operation for AST2700.
Introduce a new ast2700 class to support AST2700.
v2:
Refactor Timer Callbacks for SoC-Sp
On 12/01/2025 15.29, Michael Tokarev wrote:
12.01.2025 16:06, Michael Tokarev wrote:
09.01.2025 21:52, Fabiano Rosas wrote:
The parsing for the S390StorageAttributes section is currently leaving
an unconsumed token that is later interpreted by the generic code as
QEMU_VM_EOF, cutting the parsin
On 12/01/2025 15.34, Michael Tokarev wrote:
09.01.2025 21:52, Fabiano Rosas wrote:
Commit a55ae46683 ("s390: move css_migration_enabled from machine to
css.c") disabled CSS migration globally instead of doing it
per-instance.
CC: Paolo Bonzini
CC: qemu-sta...@nongnu.org #9.1
Fixes: a55ae46683
On 11/01/2025 16.07, Rahul Chandra wrote:
Hi,
I am not sure if this is the right list to send this to, but the
https://download.qemu.org/ download server is showing no files available for
listing. Is this unintentional? Or should I be querying the Gitlab tags from
now on for version info?
I
On 11/01/2025 16.47, Philippe Mathieu-Daudé wrote:
On 10/1/25 21:37, Pierrick Bouvier wrote:
On 1/10/25 12:33, Pierrick Bouvier wrote:
For now, it was only possible to build plugins using GCC on Windows.
However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc
On 1/10/2025 5:50 AM, Xu Yilun wrote:
> On Fri, Jan 10, 2025 at 05:00:22AM +0800, Xu Yilun wrote:
https://github.com/aik/qemu/commit/3663f889883d4aebbeb0e4422f7be5e357e2ee46
but I am not sure if this ever saw the light of the day, did not it?
(ironically I am using it as
On Fri, Nov 8, 2024 at 9:03 PM Jason Chien wrote:
>
> This commit introduces a translation tag to avoid invalidating an entry
> that should not be invalidated when IOMMU executes invalidation commands.
> E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping
> of single stage transla
On Fri, Jan 10, 2025 at 6:23 PM Atish Patra wrote:
>
> This series adds the counter delegation extension support. The counter
> delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
> extensions.
>
> 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
>
On Sat, Jan 11, 2025 at 1:11 PM Akihiko Odaki wrote:
>
> Jason, can you pull this series?
Queued.
Thanks
>
> Regards,
> Akihiko Odaki
>
> On 2024/05/08 23:51, Philippe Mathieu-Daudé wrote:
> > ping?
> >
> > On 28/4/24 13:11, Akihiko Odaki wrote:
> >> iov_from_buf(), iov_to_buf(), iov_memset(),
On Sat, Jan 11, 2025 at 1:43 PM Akihiko Odaki wrote:
>
> Hi Jason,
>
> Can you check this patch again?
I would like to have this if
1) it would be used by libvirt.
or
2) there's no other way to do this
Thanks
>
> Regards,
> Akihiko Odaki
>
> On 2024/10/22 13:59, Akihiko Odaki wrote:
> > On 2
When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. This will be helpful to remove &first_cpu uses
in few commits.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
Since create_cpu_without_cps() creates the vCPUs iterating
up to the machine SMP count, it knows the first CPU is
created upon the first iteration, at index #0 :)
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --g
> -Original Message-
> From: Michael Tokarev
> Sent: Sunday, January 12, 2025 9:13 PM
> To: Liu, Yuan1 ; pet...@redhat.com; faro...@suse.de
> Cc: qemu-devel@nongnu.org; Zeng, Jason ; Wang,
> Yichen ; qemu-stable
> Subject: Re: [PATCH 0/3] bugfixes for migration using compression methods
>
On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé
wrote:
>
> Pass RISCVCPU to kvm_riscv_get_timebase_frequency(),
> then access the first vCPU via Virt::Array::Hart[]
> rather than the &first_cpu global, which is going to
> be removed as part of the heterogeneous emulation
> effort.
>
> Phili
Propagate MaltaState to bl_setup_gt64120_jump_kernel() so
it can access the MaltaState::cpus[] array.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 589e1a07e47..61b47b0d
In boston_mach_init(), resolves the first CPU from the CPS
container using the QOM "cpu[0]" path. Propagate it to
gen_firmware(), removing the &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --
mips_fuloong2e_init() created the vCPU so has its reference,
propagate it to write_bootloader(), removing the &first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/fuloong2e.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fulo
Propagate the target specific CPU env to the locally
declared bl_gen_li() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 34c3043a563..32811e
Propagate the target specific CPU env to the locally
declared bl_gen_sw() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9f35b23653a..30e6422d3
Propagate the target specific CPU env to the locally
declared bl_gen_sd() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 30e6422d331..34c3043a5
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u32() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 9 +
hw/mips/malta.c | 18 +-
3 files changed, 16
Now than bl_setup_gt64120_jump_kernel() has access to the
MaltaState::cpus[] array, it doesn't need the &first_cpu
global anymore.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/mips/malta.c
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_ulong() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 13 +++--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/inclu
Propagate the target specific CPU env to the locally
declared bl_gen_dli() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 32811e48cdd..95e
Pass MaltaState as argument to write_bootloader() so next
commit can propagate it to bl_setup_gt64120_jump_kernel().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index a0
Propagate the target specific CPU env to the locally
declared bl_gen_load_ulong() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u64() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 9 +
hw/mips/boston.c | 6 +++---
3 files changed, 10 insertions(+),
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_jump_kernel() function.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 2 +-
hw/mips/bootloader.c | 14 +++---
hw/mips/boston.c | 2 +-
hw/mips/fuloong2e.c |
Propagate the target specific CPU env to the locally
declared bl_gen_dsll() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index b2be9267516..7cf1f01
Propagate the target specific CPU env to the locally
declared bl_gen_jalr() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 7cf1f01d225..9f35b23653
Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_jump_to() function.
Include "target/mips/cpu-qom.h" to get MIPSCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/bootloader.h | 3 ++-
hw/mips/bootloader.c | 10 +-
2 files changed, 7
"exec/hwaddr.h" defines:
typedef uint64_t hwaddr;
typedef struct MemMapEntry {
hwaddr base;
hwaddr size;
} MemMapEntry;
Since MemMapEntry::base is always of type uint64_t,
we can directly use bl_gen_write_u64().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/boston.c | 12
- Keep references to vCPUs in CPS and MaltaState,
- Refactor the MIPS Bootloader API to take CPU argument
- Access first CPU propagate from machine_init()
Based-on: <20250112215835.29320-1-phi...@linaro.org>
"hw/mips/loongson3: Remove uses of &first_cpu global"
Philippe Mathieu-Daudé (23):
hw/m
Propagate the target specific CPU env to the locally
declared bl_gen_nop() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 918ce7795c4..b2be9267516
When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. In particular, this allow to remove one global
&first_cpu use.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/mips/cps.h | 1 +
hw/mips/cps.c | 4 +++-
2 files changed, 4 in
Propagate the target specific CPU env to the locally
declared bootcpu_supports_isa() function.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/bootloader.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
ind
On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé
wrote:
>
> virt_machine_init() creates the HARTs vCPUs, then later
> virt_machine_done() calls create_fdt_sockets(), so the
> latter has access to the first vCPU via:
>
> RISCVVirtState {
> RISCVHartArrayState {
> RISCVCPU *harts;
On Mon, Jan 13, 2025 at 9:14 AM Philippe Mathieu-Daudé
wrote:
>
> Keep kvm_riscv_get_timebase_frequency() prototype aligned with
> the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
> cpu as argument. Include "target/riscv/cpu-qom.h" which declares
> the RISCVCPU typedef.
>
> Signed
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
wrote:
>
> While the TYPE_ARMV7M object forward its NVIC interrupt lines,
> it is somehow misleading to name it 'nvic'. Add the 'armv7m'
> local variable for clarity, but also keep the 'nvic' variable
> behaving like before when used for wirin
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
wrote:
>
> When instanciating the machine model, the machine_init()
> implementations usually create the CPUs, so have access
> to its first CPU. Use that rather then the &first_cpu
> global.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewe
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
wrote:
>
> The ARMv7MState object is not simply a CPU, it also
> contains the NVIC, SysTick timer, and various MemoryRegions.
>
> Rename the field as 'armv7m', like other Cortex-M boards.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by
Keep kvm_riscv_get_timebase_frequency() prototype aligned with
the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
cpu as argument. Include "target/riscv/cpu-qom.h" which declares
the RISCVCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/kvm/kvm_riscv.h | 4 +++-
virt_machine_init() creates the HARTs vCPUs, then later
virt_machine_done() calls create_fdt_sockets(), so the
latter has access to the first vCPU via:
RISCVVirtState {
RISCVHartArrayState {
RISCVCPU *harts;
...
} soc[VIRT_SOCKETS_MAX];
...
} s;
Directly use that ins
Pass RISCVCPU to kvm_riscv_get_timebase_frequency(),
then access the first vCPU via Virt::Array::Hart[]
rather than the &first_cpu global, which is going to
be removed as part of the heterogeneous emulation
effort.
Philippe Mathieu-Daudé (2):
target/riscv: Have kvm_riscv_get_timebase_frequency()
On 12/1/25 23:56, Philippe Mathieu-Daudé wrote:
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-of
After renaming a pair of fields in NRF51 & Stellaris boards,
remove the &first_cpu global uses in Cortex-M boards.
Rational is &first_cpu is going to be restricted to generic
accelerator code, then be removed. Similarly the global
'cpus_queue' containing target-agnostic CPUs is going to be
restric
The ARMv7MState object is not simply a CPU, it also
contains the NVIC, SysTick timer, and various MemoryRegions.
Rename the field as 'armv7m', like other Cortex-M boards.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/nrf51_soc.h | 2 +-
hw/arm/nrf51_soc.c | 18 +-
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/stellari
When instanciating the machine model, the machine_init()
implementations usually create the CPUs, so have access
to its first CPU. Use that rather then the &first_cpu
global.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/b-l475e-iot01a.c| 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/mp
From: Gabriel Barrantes
Do not propagate error to the upper, directly output the error
to avoid leaks.
Fixes: 2fda101de07 ("virtio-crypto: Support asynchronous mode")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2714
Signed-off-by: Gabriel Barrantes
Reviewed-by: zhenwei pi
Message-I
From: Bernhard Beschow
While at it add a trace event for input GPIO events.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
Message-ID: <2025083711.2338-14-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/gpio/imx_gpio
From: Helge Deller
On reset:
"The CPU begins fetching instructions from address 0xf004.
This address is in PDC space."
Switch vCPUs to 32-bit mode (PSW_W bit is not set) and start
execution at address 0xf004.
Signed-off-by: Helge Deller
Co-developed-by: Philippe Mathieu-Daudé
Si
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Message-Id: <20241219153857.57450-6-phi...@linaro.org>
---
hw/misc/vmcoreinfo.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/misc/vmcoreinfo.c b/hw/misc/vmcoreinfo.c
index 145f13a65cf..b0145fa
Factor sdhci_sdma_transfer() out of sdhci_data_transfer().
Re-use it in sdhci_write(), so we don't try to run multi
block transfer for a single block.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
Message-Id: <20250109122029.22780-1-phi...@linaro.org>
---
hw/sd/sdhci.c | 2
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-ID: <20250108092538.11474-14-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/imx6_src.c | 23 +--
hw/misc/trace-even
From: Bibo Mao
Code cleanup with directory hw/loongarch/, removing errors from
command "scripts/checkpatch.pl hw/loongarch/*"
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250103064514.2660438-1-maob...@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/lo
From: Gustavo Romero
Add me as the maintainer for the ivshmem-flat device.
Signed-off-by: Gustavo Romero
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250107015639.27648-1-gustavo.rom...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 7 +++
1 file changed, 7 ins
In order to track access to reserved I/O space, use yet
another UnimplementedDevice covering the whole device
memory range. Mapped with lower priority (-1).
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio
From: Nikita Shubin
Drop debug printing macros and replace them with according trace
functions.
Signed-off-by: Nikita Shubin
Reviewed-by: Alistair Francis
Message-ID: <20241220111756.16511-1-nikita.shu...@maquefel.me>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/stm32f2xx_usart.c | 49 +
For a particular physical address within the EthLite MMIO range,
addr_to_port_index() returns which port is accessed.
txbuf_ptr() points to the beginning of a (RAM) TX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Message-Id: <2024111218104
From: Keoseong Park
In ufs_write_attr_value(), the value parameter is handled in the CPU's
endian format but provided in big-endian format by the caller. Thus, it
is converted to the CPU's endian format. The related test code is also
fixed to reflect this change.
Fixes: 7c85332a2b3e ("hw/ufs: mi
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_GIE. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now
unused. Not a concern, this array will soon di
From: Bernhard Beschow
In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and
"DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. QEMU
currently misses to set the DMA bit which causes the driver to loop forever. Fix
that by setting the DMA bit if enabl
Declare TX registers as MMIO region, split it out
of the current mixed RAM/MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3
triboard_machine_init() has access to the single CPU via:
TriBoardMachineState {
TC27XSoCState {
TriCoreCPU cpu;
...
} tc27x_soc;
} ms;
Pass it as argument to tricore_load_kernel() so we can
remove the &first_cpu global use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed
From: Bernhard Beschow
Also print the QOM canonical path when tracing which allows for distinguishing
the many instances a typical i.MX SoC has.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
Message-ID: <2025083711.2338-12-shen...@gm
On reset:
"All PSW bits except the M bit is reset. The M bit is set."
Commit 1a19da0da44 ("target/hppa: Fill in hppa_cpu_do_interrupt /
hppa_cpu_exec_interrupt") inadvertently set the W bit at RESET,
remove it and set the M bit.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Helge Deller
Me
From: Helge Deller
Although the hppa_is_pa20() helper is costly due to string comparisons
in object_dynamic_cast(), it is called quite often during memory lookups
and at each start of a block of instruction translations.
Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at
CPU cr
From: Phil Dennis-Jordan
The XHCI specification, section 4.17.1 specifies that "If the
Number of Interrupters (MaxIntrs) field is greater than 1, then
Interrupter Mapping shall be supported." and "If Interrupter
Mapping is not supported, the Interrupter Target field shall be
ignored by the xHC an
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250108092538.11474-11-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/timer/imx_gpt.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/
Having all its address range mapped by subregions,
s->mmio MemoryRegion effectively became a container.
Rename it as 'container' for clarity.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20241112181044.92193-21-phi...@linaro.org>
---
hw/net/xilinx_ethlite.c
Add quick firmware boot tests (less than 1sec) for the
B160L (32-bit) and C3700 (64-bit) HPPA machines:
$ make check-functional-hppa
...
4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabiosOK 0.22s 2 subtests
passed
Remove the duplicated B160L test in qtest/boot-serial-test.c.
Sugge
Follow the assumed QOM type definition style, prefixing with
'TYPE_', and dropping the '_DEVICE' suffix which doesn't add
any value.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Marc-André Lureau
Message-Id: <20250102132624.53443-1-phi...@linaro.org>
---
include/hw/misc/vmcoreinfo.h | 7 +
From: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Bernhard Beschow
Message-ID: <2025083711.2338-9-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/char/imx_serial.c | 58 +---
From: Helge Deller
Rather than manually (and incompletely) resetting vCPUs,
call resettable_reset() which will fully reset the vCPUs.
Remove redundant assignations.
Signed-off-by: Helge Deller
Co-developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <202412311
Commit 7df6f751176 ("hw/hppa: Split out machine creation")
renamed the 'hppa' machine as 'B160L', but forgot to update
the boot serial test, which ended being skipped.
Cc: qemu-sta...@nongnu.org
Fixes: 7df6f751176 ("hw/hppa: Split out machine creation")
Reported-by: Thomas Huth
Signed-off-by: Phi
From: Akihiko Odaki
Commit 8b46d7e2dc8e ("audio: Rename coreaudio extension to use
Objective-C compiler") renamed coreaudio.c to coreaudio.m.
Signed-off-by: Akihiko Odaki
Reviewed-by: Christian Schoenebeck
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250111-maintainers-v1-1-faebe6ef0...
From: Jiaxun Yang
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting differences on scripting.
Examples of b4:
```
$ b4 prep --check
Checking patches using
Rather than using I/O registers for RAM buffer, having to
swap endianness back and forth (because the core memory layer
automatically swaps endiannes for us), declare the buffers
as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have
any more I/O regions. Remove the now unused s->regs[] array.
Add TX_CTRL to the TX registers MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3 (prio 0, i/o): ethlite.mdio
81
Inline the 3 uses of usb_new().
Reviewed-by: Zhao Liu
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20240216110313.17039-11-phi...@linaro.org>
---
include/hw/usb.h| 7 +--
hw/usb/bus.c| 3 ++-
hw/usb/dev-serial.c | 2 +-
3 files changed, 4 insertions(+), 8 deletions(-)
dif
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Fabiano Rosas
Message-ID: <20250108092538.11474-12-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
tests/qtest/libqos/arm-imx25-pdk-machine.
rxbuf_ptr() points to the beginning of a (RAM) RX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Message-Id: <20241112181044.92193-11-phi...@linaro.org>
---
hw/net/xilinx_ethlite.c | 39 +--
1 file changed
From: Alexander Graf
The documentation says that Nitro Enclaves are based on Firecracker.
AWS has never made that statement.
This patch nudges the wording to instead say it "looks like a
Firecracker microvm".
Signed-off-by: Alexander Graf
Reviewed-by: Dorjoy Chowdhury
Message-ID: <20241211222
From: Akihiko Odaki
The renamed state will not only represent powering state of PFs, but
also represent SR-IOV VF enablement in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20250109-reuse-v19-1-f541e82ca...@daynix.com>
Signed-off-by: Philippe Mathie
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_CTRL. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now
unused. Not a concern, this array will soon
From: Marcin Juszkiewicz
I am ending my time with Linaro and do not have plans to continue
working on SBSA Reference Platform anymore.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Leif Lindholm
Message-ID: <20241218123055.11220-1-marcin.juszkiew...@linaro
Rather than handling the MDIO registers as RAM, map them
as unimplemented I/O within the device MR.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-
From: Helge Deller
hppa_cpu_initfn() is called once when a HPPA CPU instance is
initialized, but it sets fields which should be set each time
a CPU resets. Rename it as a reset handler, having it matching
the ResettablePhases::hold() signature, and register it as
ResettableClass handler.
Since o
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