Now that we've got a find_free_port() function in the functional
test framework, we can convert the migration test, too.
While the original avocado test was only meant to run on aarch64,
ppc64 and x86, we can turn this into a more generic test by now
and run it on all architectures that have a mach
On 02/01/2025 06.49, Liu Jaloo wrote:
in qemu branch statble-9.2
$ ./build/qemu-system-arm -M microbit -device loader,file=/path/to/
heart-hearts-makecode.hex
Segmentation fault
That's a bug of course - a segfault should never happen...
...
according to docs/system/arm/nrf.rst
Code cleanup with directory hw/loongarch/, removing errors from
command "scripts/checkpatch.pl hw/loongarch/*"
Signed-off-by: Bibo Mao
---
hw/loongarch/acpi-build.c | 3 ++-
hw/loongarch/boot.c | 4 ++--
hw/loongarch/virt.c | 10 ++
3 files changed, 10 insertions(+), 7 dele
Merry Christmas and a Happy New Year!
And kindly ping...
On 13/12/2024 17:36, Li Zhijian wrote:
> This assertion always happens when we sanitize the CXL memory device.
> $ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
>
> It is incorrect to register an MSIX number beyond the device's ca
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
Signed-off-by: dan
The handling of the following two registers are added to POWER10 -
- DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
- DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
Signed-off-by: dan tan
---
ver 2 summary:
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
From: dan tan
*** BLURB HERE ***
Version 2 summary:
(DAWR1,DAWRX1):
- spec reference: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
- corrected commit message format
- combine DAWR(0/1) handling into a single function
- add DAWR1 & DAWRX1 to init_proc_PO
On 2025/1/3 上午6:47, Jiaxun Yang wrote:
Support booting such image by parsing header as per Linux's
specification [1].
This enabled booting vmlinux.efi/vmlinuz.efi shipped by
distros without supplying BIOS.
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
Liu Jaloo writes:
> in qemu branch statble-9.2
>
> $ ./build/qemu-system-arm -M microbit -device
> loader,file=/path/to/heart-hearts-makecode.hex
>
> Segmentation fault
Is it really a hex file?
The code in question is generic_loader_realize() and it falls back
through a series of steps:
b4 [1] is a convenient tool to manage patch series with mailing list
working flow.
Add a project default config file to match QEMU's mailing list conventions
as well as adopting differences on scripting.
Examples of b4:
```
$ b4 prep --check
Checking patches using:
scripts/checkpatch.pl -q --t
Peter Xu writes:
> On Thu, Jan 02, 2025 at 03:58:31PM -0300, Fabiano Rosas wrote:
>> The analyze-migration script was seen failing in s390x in misterious
>> ways. It seems we're reaching the subsection constructor without any
>
> It might be a good idea to add some debug lines indeed. Though are
Signed-off-by: Jiaxun Yang
---
Changes in v3:
- Added PATCH 1 (Richard)
- Link to v2:
https://lore.kernel.org/r/20241224-la-direct-kernel-boot-v2-1-3e8336c54...@flygoat.com
Changes in v2:
- Use extract API for getting bit fields (philmd)
- Mimic arm's load_aarch64_image to handle vmlinuz.efi
- L
Support booting such image by parsing header as per Linux's
specification [1].
This enabled booting vmlinux.efi/vmlinuz.efi shipped by
distros without supplying BIOS.
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 69 ++
Convert to use sszie_t to represent size internally to avoid
large image overflowing the size.
Suggested-by: Richard Henderson
Signed-off-by: Jiaxun Yang
---
hw/arm/boot.c | 2 +-
hw/core/loader.c| 4 ++--
include/hw/loader.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
d
Valgrind complains about the probe_o_direct_support() function reading
from an uninitialized buffer. For probing O_DIRECT support we don't
actually need to write to the file, just make sure the pwrite call
doesn't reject the write. Still, write zeroes to the buffer to
suppress the warning.
Reviewe
Valgrind complains about:
Use of uninitialised value of size 8
&
Conditional jump or move depends on uninitialised value(s)
both at:
at 0x5265931: _itoa_word (_itoa.c:180)
by 0x527EEC7: __vfprintf_internal (vfprintf-internal.c:1687)
by 0x528C8B0: __vsprintf_internal (iovsprintf.c:96)
Postcopy tests have been inadvertently disabled since commit
124a3c58b8 ("tests/qtest/migration: Move ufd_version_check to
utils"). That commit moved the ufd_version_check() function to another
file but failed to make sense of the ifdefs and includes:
The include was incorrectly dropped. It is ne
From: Ani Sinha
Remove code that is already compiled out. This prevents confusion.
CC: qemu-triv...@nongnu.org
Signed-off-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20250101081555.1050736-1-anisi...@redhat.com>
Signed-off-by: Fabiano Rosas
---
tests/qtest/fw_cfg-test.c |
The dump_aml_files() function calls load_expected_aml() to allocate
the tables but never frees it. Add the missing call to
free_test_data().
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20241209204427.17763-4-faro...@suse.de>
Signed-off-by: Fabiano Rosas
---
tests/qtest/bios-tables-test.c |
The following changes since commit 8b70d7f2071e2db51b1910502bfb7f84ebf926be:
Merge tag 'hw-misc-20241231' of https://github.com/philmd/qemu into staging
(2025-01-01 15:17:08 -0500)
are available in the Git repository at:
https://gitlab.com/farosas/qemu.git tags/qtest-20250102-pu
From: Peter Xu
Coverity complained about them. These two variables are never used now
after commit 832c732c5d ("migration-test: Create arch_opts"), and/or commit
34cc54fb35 ("tests/qtest/migration-test: Use custom asm bios for ppc64").
Resolves: Coverity CID 1568379
Resolves: Coverity CID 156838
From: Shameer Kolothum
Removes accidental inclusion of unrelated functions within CONFIG_UADK
as this causes compile errors like:
error: redefinition of ‘migrate_hook_start_xbzrle’
Fixes: 932f74f3fe6e ("tests/qtest/migration: Split compression tests from
migration-test.c")
Signed-off-by: Shame
The dirty_limit test does two migrations in a row and is leaking the
first 'to' instance. Do proper cleanup.
Reviewed-by: Peter Xu
Message-Id: <20241209204427.17763-2-faro...@suse.de>
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration/precopy-tests.c | 5 +
1 file changed, 5 insertions(
On Thu, Jan 02, 2025 at 10:17:53PM +0100, Philippe Mathieu-Daudé wrote:
> When a QDev instance is realized, qdev_get_machine() ends up called.
> In the next commit, qdev_get_machine() will require a "machine"
> container to be always present. To satisfy this QOM containers design,
> Implement qdev_
On Thu, Jan 02, 2025 at 03:58:31PM -0300, Fabiano Rosas wrote:
> The analyze-migration script was seen failing in s390x in misterious
> ways. It seems we're reaching the subsection constructor without any
It might be a good idea to add some debug lines indeed. Though are you sure
it's from parsing
On 1/2/2025 4:14 PM, Peter Xu wrote:
On Thu, Jan 02, 2025 at 12:34:50PM -0800, Steve Sistare wrote:
qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
it uses the existing space and verifies it is large enough, but the
verification was broken when the offset parameter was in
qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
it uses the existing space and verifies it is large enough, but the
verification was broken when the offset parameter was introduced. As
a result, a file smaller than offset passes the verification and causes
errors later. Fi
From: Peter Xu
Add a helper to fetch a root container (under object_get_root()). Sanity
check on the type of the object.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Peter Xu
Message-ID: <20241121192202.4155849-12-pet...@redhat.com>
Signed-off-by: Philip
From: Peter Xu
Use object_get_container() whenever applicable across the tree.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-13-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
backends/cryptodev.c | 4 ++--
chardev/char.c |
When a QDev instance is realized, qdev_get_machine() ends up called.
In the next commit, qdev_get_machine() will require a "machine"
container to be always present. To satisfy this QOM containers design,
Implement qdev_create_fake_machine() which creates a fake "machine"
container for user emulatio
Only qemu_create_machine_containers() uses the
machine_containers[] array, restrict the scope
to this single user.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Peter Xu
---
system/vl.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/system/vl.c b/system/v
Hi Gustavo,
On 31/12/24 21:22, Philippe Mathieu-Daudé wrote:
From: Gustavo Romero
Add a new device, ivshmem-flat, which is similar to the ivshmem PCI but
does not require a PCI bus. It's meant to be used on machines like those
with Cortex-M MCUs, which usually lack a PCI/PCIe bus, e.g. lm3s696
Respin of Peter's v2:
https://lore.kernel.org/qemu-devel/20241121192202.4155849-1-pet...@redhat.com/
'The series is about container_get() and its removal.'
(See v2's cover).
Since v3:
- Implement qdev_create_fake_machine() in single patch (peterx)
Since v2:
- Create fake machine container for us
From: Peter Xu
Add a helper to fetch machine containers. Add some sanity check around.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Xu
Message-ID: <20241121192202.4155849-10-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 10 ++
hw/c
From: Peter Xu
Currently, qdev_get_machine() has a slight misuse on container_get(), as
the helper says "get a container" but in reality the goal is to get the
machine object. It is still a "container" but not strictly.
Note that it _may_ get a container (at "/machine") in our current unit test
From: Peter Xu
Now there's no user of container_get(), remove it.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-14-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 11 ---
qom/container.c | 23 -
From: Peter Xu
Use machine_get_container() whenever applicable across the tree.
Signed-off-by: Peter Xu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20241121192202.4155849-11-pet...@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/gpio.c| 3 +--
hw/core/qdev.c
On 2/1/25 18:29, Peter Xu wrote:
On Thu, Jan 02, 2025 at 04:12:34PM +0100, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (4):
qdev: Expose qemu_create_machine()
qdev: Implement qemu_create_machine() for user emulation
qdev: Call qemu_create_machine() on user emulation
qdev: In
On Thu, Jan 02, 2025 at 12:34:50PM -0800, Steve Sistare wrote:
> qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
> it uses the existing space and verifies it is large enough, but the
> verification was broken when the offset parameter was introduced. As
> a result, a file s
qemu_ram_alloc_from_fd allocates space if file_size == 0. If non-zero,
it uses the existing space and verifies it is large enough, but the
verification was broken when the offset parameter was introduced. As
a result, a file smaller than offset passes the verification and causes
errors later. Fi
On Tue, Dec 24, 2024 at 08:17:07AM -0800, Steve Sistare wrote:
> Add a migration test for cpr-transfer mode. Defer the connection to the
> target monitor, else the test hangs because in cpr-transfer mode QEMU does
> not listen for monitor connections until we send the migrate command to
> source Q
On Thu, Jan 02, 2025 at 01:35:22PM -0500, Steven Sistare wrote:
> > > > +MigrateCommon args = {
> > > > +.start.opts_source = opts,
> > > > +.start.opts_target = opts_target,
> > > > +.start.defer_target_connect = true,
> >
> > One more comment: maybe we can even drop d
On Thu, Jan 02, 2025 at 01:35:01PM -0500, Steven Sistare wrote:
> On 12/24/2024 3:01 PM, Peter Xu wrote:
> > On Tue, Dec 24, 2024 at 08:17:07AM -0800, Steve Sistare wrote:
> > > Add a migration test for cpr-transfer mode. Defer the connection to the
> > > target monitor, else the test hangs becaus
On 1/2/2025 2:57 PM, Peter Xu wrote:
On Thu, Jan 02, 2025 at 02:21:13PM -0500, Steven Sistare wrote:
On 12/24/2024 2:24 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:17:00AM -0800, Steve Sistare wrote:
Add the cpr-transfer migration mode, which allows the user to transfer
a guest to a new QEM
On 1/2/2025 2:48 PM, Peter Xu wrote:
On Thu, Jan 02, 2025 at 01:36:01PM -0500, Steven Sistare wrote:
On 12/24/2024 12:18 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:16:47AM -0800, Steve Sistare wrote:
Extend qemu_ram_alloc_from_fd to support resizable ram, and define
qemu_ram_resize_cb to c
Philippe Mathieu-Daudé writes:
> From: Philippe Mathieu-Daudé
>
> AMSAT closed its email service [*] so my personal email
> address is now defunct. Remove it to avoid bouncing emails.
>
> [*]
> https://forum.amsat-dl.org/index.php?thread/4581-amsat-mail-alias-service-to-end-august-1-2024/
>
> S
On Thu, Jan 02, 2025 at 01:36:01PM -0500, Steven Sistare wrote:
> On 12/24/2024 12:18 PM, Peter Xu wrote:
> > On Tue, Dec 24, 2024 at 08:16:47AM -0800, Steve Sistare wrote:
> > > Extend qemu_ram_alloc_from_fd to support resizable ram, and define
> > > qemu_ram_resize_cb to clean up the API.
> > >
On Thu, Jan 02, 2025 at 02:21:13PM -0500, Steven Sistare wrote:
> On 12/24/2024 2:24 PM, Peter Xu wrote:
> > On Tue, Dec 24, 2024 at 08:17:00AM -0800, Steve Sistare wrote:
> > > Add the cpr-transfer migration mode, which allows the user to transfer
> > > a guest to a new QEMU instance on the same h
On 12/24/2024 2:24 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:17:00AM -0800, Steve Sistare wrote:
Add the cpr-transfer migration mode, which allows the user to transfer
a guest to a new QEMU instance on the same host with minimal guest pause
time, by preserving guest RAM in place, albeit wit
The analyze-migration script was seen failing in s390x in misterious
ways. It seems we're reaching the subsection constructor without any
fields, which would indicate an empty .subsection entry in the vmstate
definition. We don't have any of those, at least not without the
unmigratable flag set, so
On 12/24/2024 12:18 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:16:47AM -0800, Steve Sistare wrote:
Extend qemu_ram_alloc_from_fd to support resizable ram, and define
qemu_ram_resize_cb to clean up the API.
Add a grow parameter to extend the file if necessary. However, if
grow is false, a z
On 12/24/2024 2:54 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:17:06AM -0800, Steve Sistare wrote:
Set qmp_ready when the handshake is complete, and assert it when we
communicate with the monitor.
Suggested-by: Peter Xu
Signed-off-by: Steve Sistare
---
tests/qtest/libqtest.c | 20 +++
On 12/24/2024 3:06 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 03:01:34PM -0500, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:17:07AM -0800, Steve Sistare wrote:
Add a migration test for cpr-transfer mode. Defer the connection to the
target monitor, else the test hangs because in cpr-transfer mo
On 12/24/2024 12:27 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:16:48AM -0800, Steve Sistare wrote:
@@ -2079,6 +2100,41 @@ RAMBlock *qemu_ram_alloc_internal(ram_addr_t size,
ram_addr_t max_size,
assert((ram_flags & ~(RAM_SHARED | RAM_RESIZEABLE | RAM_PREALLOC |
On 12/24/2024 3:01 PM, Peter Xu wrote:
On Tue, Dec 24, 2024 at 08:17:07AM -0800, Steve Sistare wrote:
Add a migration test for cpr-transfer mode. Defer the connection to the
target monitor, else the test hangs because in cpr-transfer mode QEMU does
not listen for monitor connections until we se
Fix a bug reported by Ilya in:
https://lore.kernel.org/qemu-devel/uuuk6a2vo24yrrqrchjxaeko3utqshrdu6txcnqziokpg7dkom@4l4kd3dqh6jc/
Commit bb6cf6f0168 ("accel/tcg: Factor tcg_cpu_reset_hold()
out") wanted to restrict tlb_flush() to system emulation,
but inadvertently also restricted tcg_flush_jmp_c
Only the integer opcodes handled here; the vector rotates
are left for a future patch, as they are split by immediate,
scalar, and vector shift count.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8
tcg/aarch64/tcg-target-has.h | 3 +--
tcg/arm/tcg-targe
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 5 +
tcg/optimize.c | 10 +-
tcg/tcg-op.c | 4 ++--
tcg/tcg.c| 6 ++
target/i386/tcg/emit.c.inc | 12 +---
tcg/aarch64/tcg-target.c.inc | 6 ++
t
Very few source files require to access "exec/tb-flush.h"
declarations, and except a pair, they all include it
explicitly. No need to overload the generic "user-internals.h".
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/user-internals.h | 1 -
linux-user/mmap.c | 1 +
linux-use
Since c68d5b7a6af, we assume the distinct-operands facility, and check
for it at startup with HAVE_FACILITY(45). While LA, ARK and AGRK are
the same size, the latter are more exactly the operation we wish to
perform, and ARK may have a different register rename path through the
microcode, ignoring
This plugs an odd hole in which a TCGv_i64 may be cast to
a TCGv_i32 for a move. We already support this opcode for
x86_64, loongarch64, mips64, riscv64. Implement it for
aarch64, ppc64, s390x, sparc64 and tci.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8 ++--
Since tcg_cpu_reset_hold() is a system emulation specific
helper, factor tcg_exec_reset() out so we can use it from
user emulation, similarly to the [un]realize() handlers.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/internal-common.h | 1 +
accel/tcg/cpu-exec-common.c | 6 ++
accel/
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 11 ++---
tcg/riscv/tcg-target-con-set.h | 2 +-
tcg/riscv/tcg-target-con-str.h | 1 -
tcg/tci/tcg-target-has.h | 6 +--
tcg/optimize.c | 38 ++--
tcg/tcg-op.c
Commit bb6cf6f0168 ("accel/tcg: Factor tcg_cpu_reset_hold()
out") wanted to restrict tlb_flush() to system emulation,
but inadvertently also restricted tcg_flush_jmp_cache(),
which was before called on user emulation via:
Realize -> Reset -> cpu_common_reset_hold()
Since threads (vCPUs) use a c
Signed-off-by: Richard Henderson
---
host/include/riscv/host/cpuinfo.h | 5 +++--
util/cpuinfo-riscv.c | 18 --
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/host/include/riscv/host/cpuinfo.h
b/host/include/riscv/host/cpuinfo.h
index cdc784e7b6..b2
Make extract and sextract "unconditional" in the sense
that the opcodes are always present. Rely instead on
TCG_TARGET_HAS_{s}extract_valid, now always defined.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8
tcg/aarch64/tcg-target-has.h | 4
tcg/a
Use the fully general extract opcodes instead.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 10 -
tcg/aarch64/tcg-target-has.h | 11 -
tcg/arm/tcg-target-has.h | 6 -
tcg/i386/tcg-target-has.h| 11 -
tcg/loongarch64/tcg-target-has.h | 16 --
t
We already have these assertions during opcode creation.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 20 ++--
1 file changed, 2 insertions(+), 18 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index b7c58671f0..dbffbeff5f 100644
For TCI, we're losing type information from the interpreter.
Limit the opcodes to the host register size; on 64-bit host
it's just as easy to reconstruct 64-bit operands for normal add/sub.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 6 +--
tcg/tci/tcg-target-has.h |
Test each vector type, not just lumping them all together.
Add tests for I32 (always true) and I64 (64-bit hosts).
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 66 ---
1 file changed, 43 insertions(+), 23 deletions(-)
diff --git a/tcg/tcg.
Based-on: 20250102180654.1420056-1-richard.hender...@linaro.org
("[PATCH 00/73] tcg: Merge *_i32 and *_i64 opcodes")
While riscv does not yet have a completely general extract,
the Zbs extension added a single-bit extract.
Tested on cfarm95, a Banana Pi BPI-F3.
r~
Richard Henderson (2):
uti
Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint
arrays based on those. Only afterward process the TCGOpcodes and
share those TCGArgConstraint arrays.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 +-
tcg/tcg.c | 273 +++
We can now handle the awkward i686 register constraints
by examining the MemOpIdx operand to qemu_st_*_i32.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 6 --
tcg/aarch64/tcg-target-has.h | 2 --
tcg/arm/tcg-target-has.h | 1 -
tcg/i386/tcg-target-co
This is and, or, xor, andc, orc, eqv, nand, nor, not.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 27 ++--
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/translate-sve.c | 2 +-
target/sh4/translate.c | 14 +-
target/tricore/translate.c
Allow the backend to make constraint choices based on
the entire TCGOp. The type and vector element fields
within the main TCGOp structure are valid to inspect,
as well as any constant operands, e.g. a MemOp.
We lose the ability to assert the correctness of the map
from TCGOpcode to constraint se
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-has.h | 22 --
tcg/s390x/tcg-target.c.inc | 37 +
2 files changed,
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 12 --
tcg/optimize.c | 6 ++---
tcg/tcg-op.c | 38
tcg/tcg.c| 29 ++--
tcg/tci.c
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 9 +--
target/sh4/translate.c | 6 +-
tcg/optimize.c | 50
tcg/tcg-op.c | 12 +--
tcg/tcg.c| 19 ++---
tcg/tci.c
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-has.h | 8 +++-
tcg/riscv/tcg-target.c.inc | 13 +++--
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 10e61edc45..ea38ee5cbb 100644
--- a/tcg/riscv
Begin to rely on TCGOp.type to discriminate operations,
rather than two different opcodes. Convert mov first.
Introduce TCG_OPF_INT in order to keep opcode dumps the same.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 4 ++--
include/tcg/tcg.h| 2 ++
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 9 -
tcg/optimize.c | 20 +---
tcg/tcg-op.c | 10 +-
tcg/tcg.c| 19 +++
tcg/tci.c| 14
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 4 ++--
tcg/aarch64/tcg-target-has.h | 3 +--
tcg/arm/tcg-target-has.h | 2 +-
tcg/i386/tcg-target-has.h| 3 +--
tcg/loongarch64/tcg-target-has.h | 3 +--
tcg/mips/tcg-target-has.h| 4 +---
tcg/ppc
The same type information is now present in TCGOp.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 119 ++---
1 file changed, 53 insertions(+), 66 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c591f93090..75c37d1148 100644
---
When we generalize {s}extract_i32, we'll lose the
specific register constraints on ext8u and ext8s.
It's just as easy to emit a couple of insns instead.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
For TCI, we're losing type information from the interpreter. Limit the
opcodes to the host register size; on 64-bit host use an extra opcode to
emulate right shift and let tcg-op.c expand a 32-bit rotate.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 15 ++--
tcg/tci/
These defines are not required outside of tcg/tcg.c,
which includes tcg-target.c.inc before use.
Reduces the exported symbol set of tcg-target.h.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 13 -
tcg/arm/tcg-target.h | 8
tcg/i386/tcg
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target-has.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index d6073dc743..41eb530d9b 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci
Use the functional interface to query whether the opcode is supported,
and skip argument constraint assignment. This means that we can drop
the TCG_OPF_NOT_PRESENT bit mapping from TCG_TARGET_HAS_foo in tcg-opc.h.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 301 +
Don't reference TCG_TARGET_MAYBE_vec in a public header.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 ---
tcg/tcg.c | 4
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 01605f30c7..a3bef9c280 100644
--- a/
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 3 +--
tcg/optimize.c | 2 +-
tcg/tcg-op.c | 8
tcg/tcg.c| 3 +--
tcg/tci.c| 12
tcg/aarch64/tcg-target.c.inc
Add a 4th argument containing a MemOp operand which
specifies the memory operation within the type.
This mirrors what we already to for qemu_{ld,st},
except that alignment, endianness, and atomicity are
not supported.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 23 +-
We now get this information from the stored TCGOp.type.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 114 +-
include/tcg/tcg.h | 2 -
2 files changed, 57 insertions(+), 59 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg
For TCI, we're losing type information from the interpreter.
Limit the opcodes to the host register size; on 64-bit host
it's just as easy to reconstruct 64-bit operands for normal
multiply and divide.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 36 ++-
tcg/tci/t
Rely on tcg-op-vec.c to expand the opcode if missing.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sve.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 49d32fabc9..73
Now that we're no longer assigning to TCGOpDef.args_ct,
we can make the array constant.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +-
tcg/tcg-common.c | 2 +-
tcg/tcg.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/tcg/tcg.h b/include/
Extracts which abut bit 32 may use 32-bit shifts.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-has.h | 9 +++--
tcg/sparc64/tcg-target.c.inc | 11 +++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-has.h | 49 +++
tcg/tcg-has.h | 12 +---
tcg/optimize.c| 8 +++--
We're about to change canonicalization of masks as extract
instead of and. Retain the andi expansion here.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-t
Return C_NotImplemented instead of asserting for opcodes
not implemented by the backend.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 ++--
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc|
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