[PATCH] target/loongarch: Fix index calculation for variable length pte

2024-12-29 Thread Miao Hao
Signed-off-by: Miao Hao --- target/loongarch/tcg/tlb_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 97f38fc391..a57ddfe8ad 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target

[PATCH v2] feat: add loongarch page table walker support for debugger memory access

2024-12-29 Thread Miao Hao
Signed-off-by: Miao Hao --- v1 -> v2: 1. Addressed review comments. 2. Fix the assignment of variable shift. target/loongarch/cpu_helper.c | 106 -- target/loongarch/internals.h | 4 +- target/loongarch/tcg/tlb_helper.c | 4 +- 3 files changed,

Re: [PATCH] feat: add loongarch page table walker support for debugger memory access

2024-12-29 Thread Miao Hao
Hi Bibo, Thanks for your review. I apologize for my late respond due to some personal reasons. On 2024/12/19 17:57, bibo mao wrote: Hi Miao, Thanks for doing this. It is useful to debug VM. On 2024/12/19 上午11:24, Miao Hao wrote: Signed-off-by: Miao Hao ---   target/loongarch/cpu_helper.c 

[PATCH v2 0/5] hw/intc/loongarch_ipi: Enhance multiple CPU irq routing

2024-12-29 Thread Bibo Mao
LoongArch IPI can send intterrupt to multiple CPUs, physical cpu id is used to route interrupt for CPUs. With cpu hotplug feature in future, logic cpu index depends on CPUState::cpu_index heavily. Here add cpu hotplug notification interface in IPI driver, cpu mapping logic is created inside. CPUSt

[PATCH v2 1/5] hw/intc/loongson_ipi: Add more output parameter for cpu_by_arch_id

2024-12-29 Thread Bibo Mao
Add logic cpu index output parameter for function cpu_by_arch_id, CPUState::cpu_index is logic cpu slot index for possible_cpus. However it is logic cpu index with LoongsonIPICommonState::IPICore, here hide access for CPUState::cpu_index directly, it comes from function cpu_by_arch_id(). Signed-of

[PATCH v2 2/5] hw/intc/loongarch_ipi: Add basic hotplug framework

2024-12-29 Thread Bibo Mao
LoongArch ipi can send interrupt to multiple CPUs, interrupt routing to CPU comes from destination physical cpu id. Here hotplug interface is added for IPI object, sot that logic cpu mapping from physical cpu id can be setup. Here only basic hotplug framework is added, it is stub function. Signed

[PATCH v2 4/5] hw/intc/loongarch_ipi: Implment cpu hotplug interface

2024-12-29 Thread Bibo Mao
Add logic cpu allocation and cpu mapping with cpu hotplug interface. When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin. Also use hotplug_handler_plug() to nofity ipi object when cold-plug is created. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 46 +

[PATCH v2 5/5] hw/intc/loongarch_ipi: Optimize function cpu_by_arch_id

2024-12-29 Thread Bibo Mao
There is cpu mapping from physical cpu id inside, cpu_by_arch_id can be optimized from cpu mapping table. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 47 ++--- 1 file changed, 11 insertions(+), 36 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/

[PATCH v2 3/5] hw/intc/loongarch_ipi: Add cpu map table from physical cpu id

2024-12-29 Thread Bibo Mao
Bitmap table present_cpu_map is added, it is to allocate logical cpu when CPU object is created. Also present_cpu array is added to get logical cpu from physical cpu id. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 24 include/hw/intc/loongarch_ipi.h | 1

[PULL 0/2] Hppa updates

2024-12-29 Thread deller
From: Helge Deller The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7: Update version for v9.2.0 release (2024-12-10 16:20:54 +) are available in the Git repository at: https://github.com/hdeller/qemu-hppa.git tags/hppa-updates-for-v9.2-v3-pull-request for yo

[PULL 1/2] target/hppa: Add CPU reset method

2024-12-29 Thread deller
From: Helge Deller Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf004. Although we currently want to zero out all values in the CPUHPPAState struct, add the end_rese

[PULL 2/2] target/hppa: Speed up hppa_is_pa20()

2024-12-29 Thread deller
From: Helge Deller Although the hppa_is_pa20() helper is costly due to string comparisons in object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at CPU cr

Re: [PATCH v2] target/m68k: Handle EXCP_SEMIHOSTING for m68k class CPU

2024-12-29 Thread Jiaxun Yang
f161e723fdfd ("target/m68k: Perform the semihosting test during >>>> translate") >>>> Cc: qemu-sta...@nongnu.org >>>> Signed-off-by: Jiaxun Yang >>>> --- >>>> Changes in v2: >>>> - hoist both calls to do_i

Re: [PATCH 2/2] target/hppa: Speed up hppa_is_pa20()

2024-12-29 Thread Richard Henderson
On 12/29/24 15:41, del...@kernel.org wrote: From: Helge Deller Although the hppa_is_pa20() helper is costly due to string comparisons in object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up by call

Re: [PATCH 1/2] target/hppa: Add CPU reset method

2024-12-29 Thread Richard Henderson
On 12/29/24 15:41, del...@kernel.org wrote: From: Helge Deller Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf004. Although we currently want to zero out all values

[PATCH 2/2] target/hppa: Speed up hppa_is_pa20()

2024-12-29 Thread deller
From: Helge Deller Although the hppa_is_pa20() helper is costly due to string comparisons in object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at CPU cr

[PATCH 1/2] target/hppa: Add CPU reset method

2024-12-29 Thread deller
From: Helge Deller Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf004. Although we currently want to zero out all values in the CPUHPPAState struct, add the end_rese

[PATCH 0/2] hppa CPU reset and speedup

2024-12-29 Thread deller
From: Helge Deller Add CPU reset function and speed up runtime and translataion. Helge Deller (2): target/hppa: Add CPU reset method target/hppa: Speed up hppa_is_pa20() hw/hppa/machine.c | 6 +++--- target/hppa/cpu.c | 27 +-- target/hppa/cpu.h | 9 - 3 f

Re: [PATCH v2] target/m68k: Handle EXCP_SEMIHOSTING for m68k class CPU

2024-12-29 Thread BALATON Zoltan
d) - Link to v1: https://lore.kernel.org/r/20241229-m68k-semihosting-v1-1-db131e2b5...@flygoat.com --- target/m68k/op_helper.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 15bad5dd46518c6e86b6273d4

[PATCH] Revert "vvfat: fix ubsan issue in create_long_filename"

2024-12-29 Thread Michael Tokarev
This reverts commit 0cb3ff7c22671aa1e1e227318799ccf6762c3bea. The original code was right in that long name in LFN directory entry uses other parts of the entry for the name too, not just the original "name" field. So it is wrong to limit the offset to be within the name field. Some other mechan

Re: [PATCH] Revert "vvfat: fix ubsan issue in create_long_filename"

2024-12-29 Thread Philippe Mathieu-Daudé
On 29/12/24 22:12, Michael Tokarev wrote: This reverts commit 0cb3ff7c22671aa1e1e227318799ccf6762c3bea. The original code was right in that long name in LFN directory entry uses other parts of the entry for the name too, not just the original "name" field. So it is wrong to limit the offset to

Re: [PULL 04/11] vvfat: fix ubsan issue in create_long_filename

2024-12-29 Thread Michael Tokarev
29.12.2024 12:24, Volker Rümelin wrote: Found with test sbsaref introduced in [1]. [1] https://patchew.org/QEMU/20241203213629.2482806-1-pierrick.bouv...@linaro.org/ ../block/vvfat.c:433:24: runtime error: index 14 out of bounds for type 'uint8_t [11]' #0 0x56151a66b93a in create_long_fi

Re: [PATCH v2] target/hppa: Speed up hppa_is_pa20()

2024-12-29 Thread Philippe Mathieu-Daudé
On 28/12/24 22:08, Helge Deller wrote: Although the hppa_is_pa20() helper is costly due to string comparisms in "comparisms" -> "comparison"? object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up

Re: [PATCH] tests/functional/test_rx_gdbsim: Use stable URL for test_linux_sash

2024-12-29 Thread Philippe Mathieu-Daudé
On 29/12/24 17:31, Alex Bennée wrote: Thomas Huth writes: From: Philippe Mathieu-Daudé Yoshinori said [*] URL references on OSDN were stable, but they appear not to be. Mirror the artifacts on GitHub to avoid failures while testing on CI. [*] https://www.mail-archive.com/qemu-devel@nongnu.o

Re: [PATCH v2] target/m68k: Handle EXCP_SEMIHOSTING for m68k class CPU

2024-12-29 Thread Alex Bennée
--- >> Changes in v2: >> - hoist both calls to do_interrupt_all (Richard) >> - Link to v1: >> https://lore.kernel.org/r/20241229-m68k-semihosting-v1-1-db131e2b5...@flygoat.com >> --- >> target/m68k/op_helper.c | 12 +--- &g

Re: [PATCH v2 0/9] vfio/igd: Enable legacy mode on more devices

2024-12-29 Thread Tomita Moeko
On 12/4/24 23:08, Tomita Moeko wrote: > On 12/4/24 04:12, Alex Williamson wrote: >> On Tue, 3 Dec 2024 21:35:39 +0800 >> Tomita Moeko wrote: >> >>> This patchset extends the support of legacy mode igd passthrough to >>> all Intel Gen 11 and 12 devices (including Ice Lake, Jasper Lake, >>> Rocket

Re: [PATCH] tests/functional/test_rx_gdbsim: Use stable URL for test_linux_sash

2024-12-29 Thread Alex Bennée
Thomas Huth writes: > From: Philippe Mathieu-Daudé > > Yoshinori said [*] URL references on OSDN were stable, but they > appear not to be. Mirror the artifacts on GitHub to avoid failures > while testing on CI. > > [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg686487.html > > Cc: Yos

Re: [PATCH v3] target/hppa: Add CPU reset method

2024-12-29 Thread Richard Henderson
On 12/28/24 18:44, Helge Deller wrote: On 12/29/24 02:58, Richard Henderson wrote: On 12/27/24 15:17, Helge Deller wrote: Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0

Re: [PATCH v2] target/m68k: Handle EXCP_SEMIHOSTING for m68k class CPU

2024-12-29 Thread Jiaxun Yang
在2024年12月29日十二月 下午3:15,BALATON Zoltan写道: [...] > > Also why use switch for a single case? Why not write > > if (!is_hw && cs->exception_index == EXCP_SEMIHOSTING) Mostly for clarity and matching the style above, see: if (!is_hw) { switch (cs->exception_index) { case EXCP_RT

Re: [PATCH v2] target/m68k: Handle EXCP_SEMIHOSTING for m68k class CPU

2024-12-29 Thread BALATON Zoltan
h CPU classes. Fixes: f161e723fdfd ("target/m68k: Perform the semihosting test during translate") Cc: qemu-sta...@nongnu.org Signed-off-by: Jiaxun Yang --- Changes in v2: - hoist both calls to do_interrupt_all (Richard) - Link to v1: https://lore.kernel.org/r/20241229-m68k-semihosting

[PATCH v2] target/m68k: Handle EXCP_SEMIHOSTING for m68k class CPU

2024-12-29 Thread Jiaxun Yang
arget/m68k: Perform the semihosting test during translate") Cc: qemu-sta...@nongnu.org Signed-off-by: Jiaxun Yang --- Changes in v2: - hoist both calls to do_interrupt_all (Richard) - Link to v1: https://lore.kernel.org/r/20241229-m68k-semihosting-v1-1-db131e2b5...@flygoat.com --- target/m

Re: [PULL 04/11] vvfat: fix ubsan issue in create_long_filename

2024-12-29 Thread Volker Rümelin
> Found with test sbsaref introduced in [1]. > > [1] > https://patchew.org/QEMU/20241203213629.2482806-1-pierrick.bouv...@linaro.org/ > > ../block/vvfat.c:433:24: runtime error: index 14 out of bounds for type > 'uint8_t [11]' > #0 0x56151a66b93a in create_long_filename ../block/vvfat.c:433 >

[PATCH] tests/functional/test_rx_gdbsim: Use stable URL for test_linux_sash

2024-12-29 Thread Thomas Huth
From: Philippe Mathieu-Daudé Yoshinori said [*] URL references on OSDN were stable, but they appear not to be. Mirror the artifacts on GitHub to avoid failures while testing on CI. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg686487.html Cc: Yoshinori Sato Reported-by: Alex Bennée