Re: [PULL v2 00/42] Rust, qdev, target/i386 changes for 2024-12-19

Il gio 19 dic 2024, 21:06 Stefan Hajnoczi ha scritto: > Hi Paolo, > Will there be a v3? It wasn't clear to me from Richard and your replies > to v2 whether another revision is needed. > Yes, I will send it now. Paolo > Thanks, > Stefan >

Re: [RFC v4 0/5] Add packed virtqueue to shadow virtqueue

On Thu, Dec 19, 2024 at 8:37 PM Sahil Siddiq wrote: > > Hi, > > On 12/17/24 1:20 PM, Eugenio Perez Martin wrote: > > On Tue, Dec 17, 2024 at 6:45 AM Sahil Siddiq wrote: > >> On 12/16/24 2:09 PM, Eugenio Perez Martin wrote: > >>> On Sun, Dec 15, 2024 at 6:27 PM Sahil Siddiq > >>> wrote: > O

Re: [External] Re: [PATCH v8 09/12] migration/multifd: Enable DSA offloading in multifd sender path.

On Tue, Dec 17, 2024 at 9:56 AM Fabiano Rosas wrote: > > Yichen Wang writes: > > > From: Hao Xiang > > > > Multifd sender path gets an array of pages queued by the migration > > thread. It performs zero page checking on every page in the array. > > The pages are classfied as either a zero page o

[PATCH v2 41/51] tcg/optimize: Use fold_masks_zs, fold_masks_s in fold_shift

Avoid the use of the OptContext slots. Find TempOptInfo once. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 27 ++- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 8735dc0c9c..da

[PATCH v2 18/51] tcg/optimize: Use finish_folding in fold_extract2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 6f7166414f..30bce33ca6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1789,7 +1789,7 @@ static bool fo

[PATCH v2 02/51] tcg/optimize: Split out fold_affected_mask

There are only a few logical operations which can compute an "affected" mask. Split out handling of this optimization to a separate function, only to be called when applicable. Remove the a_mask field from OptContext, as the mask is no longer stored anywhere. Signed-off-by: Richard Henderson --

[PATCH v2 37/51] tcg/optimize: Use finish_folding in fold_cmp_vec

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index a7f37a1e6e..9ce90eee7f 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2497,7 +2497,7 @@ static bool fo

[PATCH v2 42/51] tcg/optimize: Simplify sign bit test in fold_shift

Merge the two conditions, sign != 0 && !(z_mask & sign), by testing ~z_mask & sign. If sign == 0, the logical and will produce false. Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index da

[PATCH v2 25/51] tcg/optimize: Use fold_masks_s in fold_nor

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index baf545df24..04f0f8b9d2 100644 --- a/tcg/optimize.c +++ b/tcg

[PATCH v2 51/51] tcg/optimize: Move fold_cmp_vec, fold_cmpsel_vec into alphabetic sort

The big comment just above says functions should be sorted. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 60 +- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c

[PATCH v2 43/51] tcg/optimize: Use finish_folding in fold_sub, fold_sub_vec

Duplicate fold_sub_vec into fold_sub instead of calling it, now that fold_sub_vec always returns true. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c i

[PATCH v2 46/51] tcg/optimize: Use fold_masks_zs in fold_xor

Avoid the use of the OptContext slots. Find TempOptInfo once. Remove fold_masks as the function becomes unused. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 18 -- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/tcg/optimize

[PATCH v2 23/51] tcg/optimize: Use fold_masks_s in fold_nand

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5b71a98cc7..c206c0f40d 100644 --- a/tcg/optimize.c +++ b/tcg

[PATCH v2 00/51] tcg: Remove in-flight mask data from OptContext

The desire is to start re-using some of the fold_* functions while lowering or simplifying operations during tcg_optmize. Many of these fold_* functions set z_mask, s_mask, and a_mask, which hang around until the end of the tcg_optmize loop and are applied by finish_folding. This disconnect betwe

[PATCH v2 10/51] tcg/optimize: Use fold_masks_zs in fold_count_zeros

Avoid the use of the OptContext slots. Find TempOptInfo once. Compute s_mask from the union of the maximum count and the op2 fallback for op1 being zero. Signed-off-by: Richard Henderson --- tcg/optimize.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tcg/o

[PATCH v2 30/51] tcg/optimize: Return true from fold_qemu_st, fold_tcg_st

Stores have no output operands, and so need no further work. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index b01929fccf..a5a57bb914 100644 ---

[PATCH v2 40/51] tcg/optimize: Canonicalize s_mask in fold_exts, fold_sextract

Simply or'ing the an input s_mask with the mask implied by the sign extension operation may leave disconnected bits to the right. Use smask_from_smask to canonicalize. Signed-off-by: Richard Henderson --- tcg/optimize.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tcg/optimize.c b/

[PATCH v2 16/51] tcg/optimize: Use fold_masks_s in fold_eqv

Add fold_masks_s as a trivial wrapper around fold_masks_zs. Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c

[PATCH v2 04/51] tcg/optimize: Split out fold_masks_zs

Add a routine to which masks can be passed directly, rather than storing them into OptContext. To be used in upcoming patches. Signed-off-by: Richard Henderson --- tcg/optimize.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c

[PATCH v2 38/51] tcg/optimize: Use finish_folding in fold_cmpsel_vec

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9ce90eee7f..fae6a29685 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2518,7 +2518,7 @@ static bool fo

[PATCH v2 07/51] tcg/optimize: Use fold_masks_zs in fold_and

Avoid the use of the OptContext slots. Find TempOptInfo once. Sink mask computation below fold_affected_mask early exit. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 30 -- 1 file changed, 16 insertions(+), 14 deletions(-) dif

[PATCH v2 45/51] tcg/optimize: Use finish_folding in fold_tcg_ld_memcopy

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 56bf3c1aaa..0a84959f4c 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2713,7 +2713,7 @@ static bool fo

[PATCH v2 49/51] tcg/optimize: Remove z_mask, s_mask from OptContext

All mask setting is now done with parameters via fold_masks_*. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 14 -- 1 file changed, 14 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 94be844ee5..2b64b8a0ec 100644 --- a/tcg/optim

[PATCH v2 48/51] tcg/optimize: Use finish_folding as default in tcg_optimize

All non-default cases now finish folding within each function. Do the same with the default case and assert it is done after. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.

[PATCH v2 47/51] tcg/optimize: Use finish_folding in fold_bitsel_vec

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 6f81d2e831..74d1ca7484 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2861,7 +2861,7 @@ static bool fo

[PATCH v2 33/51] tcg/optimize: Use fold_masks_z in fold_setcond

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9c4bb1fb91..079b5b82ba 100644 --- a/tcg/optimize.c +++ b/tcg/optim

[PATCH v2 01/51] tcg/optimize: Split out finish_bb, finish_ebb

Call them directly from the opcode switch statement in tcg_optimize, rather than in finish_folding based on opcode flags. Adjust folding of conditional branches to match. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 47 +++-

[PATCH v2 50/51] tcg/optimize: Move fold_bitsel_vec into alphabetic sort

The big comment just above says functions should be sorted. Add forward declarations as needed. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 114 + 1 file changed, 59 insertions(+), 55 deletions(-) diff --gi

[PATCH v2 14/51] tcg/optimize: Use finish_folding in fold_divide

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index e4f68241ce..0ae96f34e5 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1704,7 +1704,7 @@ static bool fo

[PATCH v2 22/51] tcg/optimize: Use finish_folding in fold_mul*

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index e00d86ab2c..5b71a98cc7 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1986,7 +1986,7 @@ static b

[PATCH v2 13/51] tcg/optimize: Compute sign mask in fold_deposit

The input which overlaps the sign bit of the output can have its input s_mask propagated to the output s_mask. Signed-off-by: Richard Henderson --- tcg/optimize.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index de32cc0323.

[PATCH v2 27/51] tcg/optimize: Use fold_masks_zs in fold_or

Avoid the use of the OptContext slots. Find TempOptInfo once. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 6af23f8512..9b351f0521 100644

[PATCH v2 05/51] tcg/optimize: Augment s_mask from z_mask in fold_masks_zs

Consider the passed s_mask to be a minimum deduced from either existing s_mask or from a sign-extension operation. We may be able to deduce more from the set of known zeros. Remove identical logic from several opcode folders. Signed-off-by: Richard Henderson --- tcg/optimize.c | 12 +++-

[PATCH v2 44/51] tcg/optimize: Use fold_masks_zs in fold_tcg_ld

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index bfce2dcf60..56bf3c1aaa 100644 --- a/tcg/opt

[PATCH v2 39/51] tcg/optimize: Use fold_masks_zs in fold_sextract

Avoid the use of the OptContext slots. Find TempOptInfo once. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index fae6a29685..d0a9ea1ee4

[PATCH v2 36/51] tcg/optimize: Use fold_masks_z in fold_setcond2

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 63f80efeec..a7f37a1e6e 100644 --- a/tcg/optimize.c +++ b/tcg/optim

[PATCH v2 19/51] tcg/optimize: Use fold_masks_zs in fold_exts

Avoid the use of the OptContext slots. Find TempOptInfo once. Explicitly sign-extend z_mask instead of doing that manually. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 20 1 file changed, 8 insertions(+), 12 deletions(-) diff --git

[PATCH v2 06/51] tcg/optimize: Use finish_folding in fold_add, fold_add_vec, fold_addsub2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 17b72fe759..41fd69365b 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -977,7 +977,7 @@ static

[PATCH v2 29/51] tcg/optimize: Use fold_masks_zs in fold_qemu_ld

Avoid the use of the OptContext slots. Be careful not to call fold_masks_zs when the memory operation is wide enough to require multiple outputs, so split into two functions: fold_qemu_ld_1reg and fold_qemu_ld_2reg. Signed-off-by: Richard Henderson --- tcg/optimize.c | 28 ++

[PATCH v2 31/51] tcg/optimize: Use finish_folding in fold_remainder

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index a5a57bb914..868da884f1 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2169,7 +2169,7 @@ static bool fo

[PATCH v2 03/51] tcg/optimize: Copy mask writeback to fold_masks

Use of fold_masks should be restricted to those opcodes that can reliably make use of it -- those with a single output, and from higher-level folders that set up the masks. Prepare for conversion of each folder in turn. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/opti

[PATCH v2 26/51] tcg/optimize: Use fold_masks_s in fold_not

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 04f0f8b9d2..6af23f8512 100644 --- a/tcg/optimize.c +++ b/tcg/o

[PATCH v2 28/51] tcg/optimize: Use fold_masks_zs in fold_orc

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 9b351f0521..da9c8c4669 100644 --- a/tcg/optimize.c +++ b/tcg

[PATCH v2 35/51] tcg/optimize: Fix sign mask in fold_negsetcond

The sign mask is about repetitions, a la clrsb64(), so the lsb itself can never be a repetition. Thus ~1 not -1 is correct. Signed-off-by: Richard Henderson --- tcg/optimize.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5bfcb22a0

[PATCH v2 20/51] tcg/optimize: Use fold_masks_z in fold_extu

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 659190dcd8..85e6dcdb26 100644 --- a/tcg/optimize.c +++ b/tcg/opt

[PATCH v2 32/51] tcg/optimize: Distinguish simplification in fold_setcond_zmask

Change return from bool to int; distinguish between complete folding, simplification, and no change. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/optimize.c b/tcg

[PATCH v2 21/51] tcg/optimize: Use fold_masks_zs in fold_movcond

Avoid the use of the OptContext slots. Find TempOptInfo once. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 85e6dcdb26..e00d86ab2c

[PATCH v2 34/51] tcg/optimize: Use fold_masks_s in fold_negsetcond

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 079b5b82ba..5bfcb22a0e 100644 --- a/tcg/optimize.c +++ b/tcg/optim

[PATCH v2 11/51] tcg/optimize: Use fold_masks_z in fold_ctpop

Add fold_masks_z as a trivial wrapper around fold_masks_zs. Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c

[PATCH v2 08/51] tcg/optimize: Use fold_masks_zs in fold_andc

Avoid the use of the OptContext slots. Find TempOptInfo once. Avoid double inversion of the value of second const operand. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git

[PATCH v2 17/51] tcg/optimize: Use fold_masks_z in fold_extract

Avoid the use of the OptContext slots. Find TempOptInfo once. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 56043a02e0..6f7166414f 10064

[PATCH v2 24/51] tcg/optimize: Use fold_masks_z in fold_neg_no_const

Avoid the use of the OptContext slots. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c206c0f40d..baf545df24 100644 --- a/tcg/optimize.c +++ b/tc

[PATCH v2 15/51] tcg/optimize: Use finish_folding in fold_dup, fold_dup2

Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 0ae96f34e5..0232fa852e 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1714,7 +1714,7 @@ static boo

[PATCH v2 09/51] tcg/optimize: Use fold_masks_zs in fold_bswap

Avoid the use of the OptContext slots. Find TempOptInfo once. Always set s_mask along the BSWAP_OS path, since the result is being explicitly sign-extended. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 20 +--- 1 file changed, 9 insertions

[PATCH v2 12/51] tcg/optimize: Use fold_and and fold_masks_z in fold_deposit

Avoid the use of the OptContext slots. Find TempOptInfo once. When we fold to and, use fold_and. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tcg/optimize.c | 34 -- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/tcg/optimi

[PATCH 2/4] tests/functional/test_ppc64_hv: Simplify console handling

Since functional tests have character-based console output parsing, there is no need for strange hacks to work around old line-based. Signed-off-by: Nicholas Piggin --- tests/functional/test_ppc64_hv.py | 43 ++- 1 file changed, 19 insertions(+), 24 deletions(-) diff

[PATCH 0/4] tests/functional: ppc update and download fail fix

This updates test_ppc64_hv to the character-based console handling, tidies up repo handling, and updates the image. Also add a patch that keeps other functional tests working when some assets can't be pre-cached because test_rx_gdbsim started failing for me. Thanks, Nick Nicholas Piggin (4): t

[PATCH 4/4] tests/functional/test_ppc64_hv: Update to Alpine 3.21.0

Signed-off-by: Nicholas Piggin --- tests/functional/test_ppc64_hv.py | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_ppc64_hv.py b/tests/functional/test_ppc64_hv.py index 62e1a0f3a2d..f5ff0993ff5 100755 --- a/tests/functional/test_ppc64_hv.py +++

[PATCH 1/4] tests/functional: Don't fail the whole test if a pre-cache fetch fails

If any pre-cache downloads fail, the entire functional test run is failed. Signed-off-by: Nicholas Piggin --- tests/functional/qemu_test/asset.py | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tests/functional/qemu_test/asset.py b/tests/functional/qemu_test/asse

[PATCH 3/4] tests/functional/test_ppc64_hv: Update repo management

`setup-apkrepos` can be used to set repos rather than open-coding URLs. Signed-off-by: Nicholas Piggin --- tests/functional/test_ppc64_hv.py | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/functional/test_ppc64_hv.py b/tests/functional/test_ppc64_hv.py index afc

Re: (Proposal) New TDX Global Metadata To Report FIXED0 and FIXED1 CPUID Bits

On 12/19/2024 10:33 AM, Sean Christopherson wrote: For all other CPUID bits, what the TDX Module thinks and/or presents to the guest is completely irrelevant, at least as far as KVM cares, and to some extent as far as QEMU cares. This includes the TDX Module's FEATURE_PARAVIRT_CTRL, which fra

[PULL v2 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support

From: Daniel Henrique Barboza Also add a new page, docs/specs/riscv-aia.rst, where we're documenting the state of AIA support in QEMU w.r.t the controllers being emulated or not depending on the AIA and accelerator settings. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis

[PULL v2 04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS

From: Daniel Henrique Barboza Interrupt Generation Support (IGS) is a capability that is tied to the interrupt deliver mechanism, not with the core IOMMU emulation. We should allow device implementations to set IGS as they wish. A new helper is added to make it easier for device impls to set IGS

[PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver

From: Daniel Henrique Barboza Commit 68c9e54bea handled a situation where a warning was being shown when using the 'sifive_e' cpu when disabling the named extension zic64b. It makes little sense to show user warnings for named extensions that users can't control, and the solution taken was to dis

[PULL v2 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic

From: Daniel Henrique Barboza The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configur

[PULL v2 36/39] target/riscv: Include missing headers in 'internals.h'

From: Philippe Mathieu-Daudé Rather than relying on implicit includes, explicit them, in order to avoid when refactoring unrelated headers: target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S' 49 | ret = PRV_S; | ^ target/riscv/intern

Re: [PULL 00/39] riscv-to-apply queue

On Fri, Dec 20, 2024 at 6:45 AM Stefan Hajnoczi wrote: > > Hi Alistair, > Please take a look at the following CI failure: > > x86_64-w64-mingw32-gcc -m64 -Ilibqemuutil.a.p -I. -I.. -Iqapi -Itrace -Iui > -Iui/shader -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 > -I/usr/x86_64-w64-min

[PULL v2 08/39] hw/riscv/riscv-iommu: implement reset protocol

From: Daniel Henrique Barboza Add a riscv_iommu_reset() helper in the base emulation code that implements the expected reset behavior as defined by the riscv-iommu spec. Devices can then use this helper in their own reset callbacks. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Fra

[PULL v2 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

From: "Fea.Wang" Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be supported when the svukte extension is enabled. When senvcfg[UKTE] bit is set, the memory access from U-mode should do the svukte check only except HLV/HLVX/HSV H-mode instructions which depend on hstatus[HUKT

[PULL v2 17/39] target/riscv/kvm: remove irqchip_split() restriction

From: Daniel Henrique Barboza Remove the 'irqchip_split()' restriction in kvm_arch_init() now that we have support for "-accel kvm,kernel-irqchip=split". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241119191706.718860-8-dbarb...@ventanamicro.com> Signed-

[PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd

From: Jim Shu DTB is placed to the end of memory, so we will check if the start address of DTB overlaps to the address of kernel/initrd. Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20241120153935.24706-4-jim@sifive.com> Signed-off

[PULL v2 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format

From: Sia Jee Heng Update the SPCR table to accommodate the SPCR Table revision 4 [1]. The SPCR table has been modified to adhere to the revision 4 format [2]. [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table [2]: https://github.com/

[PULL v2 15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers

From: Daniel Henrique Barboza The current logic to determine if we don't need an emulated APLIC controller, i.e. KVM will provide for us, is to determine if we're running KVM, with in-kernel irqchip support, and running aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and virt_

[PULL v2 33/39] target/riscv: Expose svukte ISA extension

From: "Fea.Wang" Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis Message-ID: <20241203034932.25185-6-fea.w...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cp

[PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32

From: "Fea.Wang" The spec explicitly says svukte doesn't support RV32. So check that it is not enabled in RV32. Signed-off-by: Fea.Wang Reviewed-by: Alistair Francis Message-ID: <20241203034932.25185-7-fea.w...@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 5 ++

[PULL v2 29/39] target/riscv: Add svukte extension capability variable

From: "Fea.Wang" Refer to the draft of svukte extension from: https://github.com/riscv/riscv-isa-manual/pull/1564 Svukte provides a means to make user-mode accesses to supervisor memory raise page faults in constant time, mitigating attacks that attempt to discover the supervisor software's addr

[PULL v2 38/39] target/riscv: add ssstateen

From: Daniel Henrique Barboza ssstateen is defined in RVA22 as: "Supervisor-mode view of the state-enable extension. The supervisor-mode (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers must be provided." Add ssstateen as a named feature that is available if we also have s

[PULL v2 10/39] target/riscv: Add Tenstorrent Ascalon CPU

From: Anton Blanchard Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to 8 wide RV64 cores. More details can be found at https://tenstorrent.com/ip/tt-ascalon Signed-off-by: Anton Blanchard Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <202411

[PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

From: "Fea.Wang" Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed

[PULL v2 24/39] hw/char/riscv_htif: Explicit little-endian implementation

From: Philippe Mathieu-Daudé Since our RISC-V system emulation is only built for little endian, the HTIF device aims to interface with little endian memory accesses, thus we can explicit htif_mm_ops:endianness being DEVICE_LITTLE_ENDIAN. In that case tswap64() is equivalent to le64_to_cpu(), as

[PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo

From: Jim Shu Add a new struct RISCVBootInfo to sync boot information between multiple boot functions. Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20241120153935.24706-3-jim@sifive.com> Signed-off-by: Alistair Francis --- includ

[PULL v2 23/39] MAINTAINERS: Cover RISC-V HTIF interface

From: Philippe Mathieu-Daudé The HTIF interface is RISC-V specific, add it within the MAINTAINERS section covering hw/riscv/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20241129154304.34946-2-phi...@linaro.org> Signed-

[PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU

From: MollyChen Add a CPU entry for the RV64 XiangShan NANHU CPU which supports single-core and dual-core configurations. More details can be found at https://docs.xiangshan.cc/zh-cn/latest/integration/overview Signed-off-by: MollyChen Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Ba

[PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

From: Jim Shu Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <202411

[PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h'

From: Philippe Mathieu-Daudé Rather than relying on implicit includes, explicit them, in order to avoid when refactoring unrelated headers: target/riscv/vector_internals.h:36:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations

[PULL v2 32/39] target/riscv: Check memory access to meet svukte rule

From: "Fea.Wang" Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLVX, HSV and execute from U

[PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses

From: Philippe Mathieu-Daudé Looking at htif_mm_ops[] read/write handlers, we notice they expect 32-bit values to accumulate into to the 'fromhost' and 'tohost' 64-bit variables. Explicit by setting the .impl min/max fields. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Revi

[PULL v2 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V

From: Sia Jee Heng Update the virt SPCR golden reference file for RISC-V to accommodate the SPCR Table revision 4 [1], utilizing the iasl binary compiled from the latest ACPICA repository. The SPCR table has been modified to adhere to the revision 4 format [2]. [1]: https://learn.microsoft.com/

[PULL v2 03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()

From: Daniel Henrique Barboza Move all the static initializion of the device to an init() function, leaving only the dynamic initialization to be done during realize. With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during init(), and realize() will increment s->cap with the extra

[PULL v2 00/39] riscv-to-apply queue

The following changes since commit 3e9793ab01904144c204589811e0e879109a9713: Merge tag 'qga-pull-2024-12-18' of https://github.com/kostyanf14/qemu into staging (2024-12-18 20:24:59 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply

[PULL v2 11/39] hw/intc/riscv_aplic: rename is_kvm_aia()

From: Daniel Henrique Barboza The helper is_kvm_aia() is checking not only for AIA, but for aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an in-kernel chip present. Rename it to be a bit clear what the helper is doing since we'll add more AIA helpers in the next patches. Ma

[PULL v2 13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()

From: Daniel Henrique Barboza Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c, the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with in-kernel irqchip enabled. It is not checking for a generic AIA support. Rename the helper to virt_use_kvm_aia_aplic_imsi

[PULL v2 07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support

From: Daniel Henrique Barboza MSIx support is added in the RISC-V IOMMU platform device by including the required MSIx facilities to alow software to properly setup the MSIx subsystem. We took inspiration of what is being done in the riscv-iommu-pci device, mainly msix_init() and msix_notify(),

[PULL v2 14/39] target/riscv/kvm: consider irqchip_split() in aia_create()

From: Daniel Henrique Barboza Before adding support to kernel-irqchip=split when using KVM AIA we need to change how we create the in-kernel AIA device. In the use case we have so far, i.e. in-kernel irqchip without split mode, both the s-mode APLIC and IMSIC controllers are provided by the irqc

[PULL v2 09/39] docs/specs: add riscv-iommu-sys information

From: Daniel Henrique Barboza Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20241106133407.604587-8-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- docs/specs/riscv-iommu.rst | 30 +++--- docs/system/riscv/virt.rst | 1

[PULL v2 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage

From: Daniel Henrique Barboza In create_fdt_sockets() we have the following pattern: if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do stuff ...) } else { (... do other stuff ...) } if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do more stuff ...)

[PULL v2 05/39] hw/riscv: add riscv-iommu-sys platform device

From: Tomasz Jeznach This device models the RISC-V IOMMU as a sysbus device. The same design decisions taken in the riscv-iommu-pci device were kept, namely the existence of 4 vectors are available for each interrupt cause. The WSIs are emitted using the input of the s->notify() callback as a in

[PULL v2 20/39] qtest: allow SPCR acpi table changes

From: Sia Jee Heng Signed-off-by: Sia Jee Heng Reviewed-by: Sunil V L Acked-by: Alistair Francis Message-ID: <20241028015744.624943-2-jeeheng@starfivetech.com> Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --gi

[PULL v2 01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova

From: Jason Chien >From RISCV IOMMU spec section 2.1.3: When SXL is 1, the following rules apply: - If the first-stage is not Bare, then a page fault corresponding to the original access type occurs if the IOVA has bits beyond bit 31 set to 1. - If the second-stage is not Bare, then a guest page

[PULL v2 19/39] hw/riscv: Add Microblaze V generic board

From: Sai Pavan Boddu Add a basic board with interrupt controller (intc), timer, serial (uartlite), small memory called LMB@0 (128kB) and DDR@0x8000 (configured via command line eg. -m 2g). This is basic configuration which matches HW generated out of AMD Vivado (design tools). But initial co

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