FYI. The following data comes from the first ping-pong mlx VF
migration after rebooting the host.
1. Test for multifd=0:
1.1 Outgoing migration:
VF number: 1 VF 4 VF
Time elapsed: 10194 ms 10650 ms
Memory processed:
For loongarch extioi emulation driver, add unrealize interface and
remove instance_finalize interface and move the code to unrealize
interface.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
separately. Also remove unnecessary header files.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 24 ++--
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
its own realize() function.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c| 38 --
hw/intc
With some structure such as vmstate and property, rename LoongArchExtIOI
with LoongArchExtIOICommonState, these common structure will be moved
to common file.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c | 41 +++---
1 file changed
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
to file loongarch_extioi_common.h.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_extioi.h| 26 --
include/hw/intc/loongarch_extioi_common.h | 27
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
since it is defined in file loongarch_extioi_common.h
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_extioi.h| 1 +
include/hw/intc/loongarch_extioi_common.h | 2 +-
2 files changed, 2 inserti
Add common header file hw/intc/loongarch_pic_common.h, and move
some macro definition from hw/intc/loongarch_pch_pic.h to the common
header file.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_pch_pic.h| 36 +++---
include/hw/intc/loongarch_pic_c
With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
vmstate_loongarch_pic_common, and with pic property rename
loongarch_pch_pic_properties with loongarch_pic_common_properties.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 52 +++
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
to file loongarch_pic_common.h, and rename structure name with
LoongArchPICCommonState.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_pch_pic.h| 27 +
include/hw/intc/lo
Add common realize function, it is only to check validity of property.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_extioi.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index
Add vmstate pre_save and post_load interfaces, which can be used
by pic kvm driver in future.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pic_common.c | 26 ++
include/hw/intc/loongarch_pic_common.h | 2 ++
2 files changed, 28 insertions(
Memory region is created in instance_init(), merge it into function
realize(). There is no special class_init() for loongarch_pch object.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_pic.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --
The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu
into staging (2024-12-16 14:20:33 -0500)
are available in the Git repository at:
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch
Move some common functions to file loongarch_pic_common.c, the common
functions include loongarch_pic_common_realize(), property structure
loongarch_pic_common_properties and vmstate structure
vmstate_loongarch_pic_common.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
hw/intc/loongarch_pch_
Add common header file include/hw/intc/loongarch_extioi_common.h, and
move some macro definition from include/hw/intc/loongarch_extioi.h to
the common header file.
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
---
include/hw/intc/loongarch_extioi.h| 50 +--
include/hw/in
On Thu, Dec 12, 2024 at 06:22:04PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:22:04 +0100
> From: Paolo Bonzini
> Subject: [PATCH 7/7] rust: pl011: simplify handling of the FIFO enabled bit
> in LCR
> X-Mailer: git-send-email 2.47.1
>
> Use ==/!= instead of going through bool and xo
On Thu, Dec 12, 2024 at 06:22:03PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:22:03 +0100
> From: Paolo Bonzini
> Subject: [PATCH 6/7] rust: pl011: fix migration stream
> X-Mailer: git-send-email 2.47.1
>
> The Rust vmstate macros lack the type-safety of their C equivalents (so
> saf
On Thu, Dec 12, 2024 at 06:22:02PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:22:02 +0100
> From: Paolo Bonzini
> Subject: [PATCH 5/7] rust: pl011: extend registers to 32 bits
> X-Mailer: git-send-email 2.47.1
>
> The PL011 Technical Reference Manual lists the "real" size of the
> re
On Thu, Dec 12, 2024 at 06:22:01PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:22:01 +0100
> From: Paolo Bonzini
> Subject: [PATCH 4/7] rust: pl011: fix break errors and definition of Data
> struct
> X-Mailer: git-send-email 2.47.1
>
> The Data struct is wrong, and does not show how
On 12/18/24 23:51, Philippe Mathieu-Daudé wrote:
Convert CLEAN_HPTE() macro as hpte_set_clean() method.
Since sPAPR is in big endian configuration at reset,
use the big endian LD/ST API to access the HPTEs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 15 ++-
1 f
Hi Philippe,
Similar issue here as with patch 2 ..
On 12/18/24 23:51, Philippe Mathieu-Daudé wrote:
Convert HPTE_DIRTY() macro as hpte_is_dirty() method.
Since sPAPR is in big endian configuration at reset,
use the big endian LD/ST API to access the HPTEs.
Signed-off-by: Philippe Mathieu-Daudé
On Thu, Dec 12, 2024 at 06:22:00PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:22:00 +0100
> From: Paolo Bonzini
> Subject: [PATCH 3/7] rust: pl011: always use reset() method on registers
> X-Mailer: git-send-email 2.47.1
>
> For CR, the ugly-ish "0.into()" idiom is already hidden wit
Il gio 19 dic 2024, 05:20 Zhao Liu ha scritto:
> But when I double-check where to set up the rsr, I realized that the
> rust version and the C version seem to be inconsistent?
>
> IIUC, I guess Rust should uses to_be_bytes()[2].
Yes, that's patch 4 in this series. :)
Paolo
[*]: https://doc.ru
Hi Philippe,
On 12/18/24 23:51, Philippe Mathieu-Daudé wrote:
Convert HPTE() macro as hpte_get() method.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr.c | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/
From: Andrew Yuan
As in the Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev: R1p12
- Doc Rev: 1.3 User Guide,
if the DISABLE_MASK bit in type2_compare_x_word_1 is set,
mask_value in type2_compare_x_word_0 is used as an additional 2 byte Compare
Value
Signed-off-by: Andrew Yuan
Signed-off-by: Miao Hao
---
target/loongarch/cpu_helper.c | 104 --
target/loongarch/internals.h | 4 +-
target/loongarch/tcg/tlb_helper.c | 4 +-
3 files changed, 104 insertions(+), 8 deletions(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loong
On Thu, Dec 12, 2024 at 06:21:59PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:21:59 +0100
> From: Paolo Bonzini
> Subject: [PATCH 2/7] rust: pl011: match break logic of C version
> X-Mailer: git-send-email 2.47.1
>
> Check loopback_enabled(), not fifo_enabled(), like the C code.
>
>
Sorry,
I made a mistake. I sent an incorrect patch.
-邮件原件-
发件人: andrew Yuan
发送时间: 2024年12月19日 11:43
收件人: phi...@linaro.org; edgar.igles...@gmail.com; alist...@alistair23.me;
jasow...@redhat.com; peter.mayd...@linaro.org; qemu-...@nongnu.org;
qemu-devel@nongnu.org
抄送: andrew Yuan
主题: [
From: Andrew Yuan
As in the Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev: R1p12
- Doc Rev: 1.3 User Guide,
if the DISABLE_MASK bit in type2_compare_x_word_1 is set,
mask_value in type2_compare_x_word_0 is used as an additional 2 byte Compare
Value
Signed-off-by: Andrew Yuan
These are a bunch of small fixes and improvements for ppc. I've
posted these before so I'll just end up merging them this cycle.
Thanks,
Nick
Nicholas Piggin (5):
target/ppc: fix timebase register reset state
spapr: Fix vpa dispatch count for record-replay
spapr: Generate random HASHPKEYR f
(H)DEC and PURR get reset before icount does, which causes them to be
skewed and not match the init state. This can cause replay to not
match the recorded trace exactly. For DEC and HDEC this is usually not
noticable since they tend to get programmed before affecting the
target machine. PURR has be
The hypervisor is expected to create a value for the HASHPKEY SPR for
each partition. Currently it uses zero for all partitions, use a
random number instead, which in theory might make kernel ROP protection
more secure.
Signed-of-by: Nicholas Piggin
---
include/hw/ppc/spapr.h | 1 +
hw/ppc/spap
The dispatch count is a field in guest memory that the hypervisor
increments when preempting and dispatching the guest. This was not
being done deterministically with respect to icount, because tcg
exec exit is not deterministic (e.g., an async event could cause it).
Change vpa dispatch count incr
A translation that encounters a process table entry that is zero is
something that Linux does to cause certain kernel NULL pointer
dereferences to fault. It is not itself a programming error, so avoid
the guest error log.
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-radix64.c | 14 +
>From the Freescale PowerPC Architecture Primer:
Alternate time base APU. This APU, implemented on the e500v2, defines
a 64-bit time base counter that differs from the PowerPC defined time
base in that it is not writable and counts at a different, and
typically much higher, frequency. The
On Thu, Dec 12, 2024 at 06:21:58PM +0100, Paolo Bonzini wrote:
> Date: Thu, 12 Dec 2024 18:21:58 +0100
> From: Paolo Bonzini
> Subject: [PATCH 1/7] rust: pl011: fix declaration of LineControl bits
> X-Mailer: git-send-email 2.47.1
>
> The bits in the LineControl struct were backwards. :(
>
> Sig
On Thu, Dec 19, 2024, Rick P Edgecombe wrote:
> On Tue, 2024-12-17 at 16:08 -0800, Sean Christopherson wrote:
> > On Tue, Dec 17, 2024, Rick P Edgecombe wrote:
> > > Some options discussed on the call:
> > >
> > > 1. If we got a promise to require any new CPUID bits that clobber host
> > > state
I tested this series v2 with regression tests, due to this series
changing some files about virtio-net, everything works fine.
Tested-by: Lei Yang
On Wed, Dec 18, 2024 at 9:44 PM Richard Henderson
wrote:
>
> - Missed constifying two arrays.
> - Eliminate all empty Property lists.
> - Detect bot
On Tue, 2024-12-17 at 16:08 -0800, Sean Christopherson wrote:
> On Tue, Dec 17, 2024, Rick P Edgecombe wrote:
> > It seems like an anti-pattern to have KVM maintaining any code to defend
> > against
> > TDX module changes that could instead be handled with a promise.
>
> I disagree, sanity check
On Thu Dec 19, 2024 at 1:08 AM AEST, Phil Dennis-Jordan wrote:
> This looks sensible to me overall.
>
> For the new symbolic constants for MMIO register offsets such as
> XHCI_OPER_*, XHCI_INTR_* and so on, I'm wondering if it would be clearer to
> give them all an _OFFSET suffix. It's not perfectl
On Thu, 19 Dec 2024, Nicholas Piggin wrote:
On Thu Dec 19, 2024 at 5:18 AM AEST, BALATON Zoltan wrote:
On Wed, 18 Dec 2024, Philippe Mathieu-Daudé wrote:
The ePAPR magic value in $r6 doesn't need to be byte swapped.
See ePAPR-v1.1.pdf chapter 5.4.1 "Boot CPU Initial Register State"
and the fol
I tested this patch with virtio-net regression tests,everything works fine.
Tested-by: Lei Yang
On Wed, Dec 18, 2024 at 10:36 PM Laurent Vivier wrote:
>
> Add support of VHOST_USER_PROTOCOL_F_DEVICE_STATE in virtio-net
> with vhost-user backend.
>
> Cc: Hanna Czenczek
> Signed-off-by: Laurent
Hi,
Some time ago, I wrote a Gist [1] outlining what I believe to be the
ideal environment for debugging 16-bit code in real mode on Qemu. Based
on the feedback I've received, I decided to share it here to gather more
opinions.
It is commonly known that Qemu does not handle real/16-bit mode wel
On Thu Dec 19, 2024 at 7:06 AM AEST, Phil Dennis-Jordan wrote:
> On Wed, 18 Dec 2024 at 02:19, Nicholas Piggin wrote:
>
> > On Thu Dec 12, 2024 at 8:41 PM AEST, Phil Dennis-Jordan wrote:
[...]
> > > > @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice
> > > > *dev, Error **e
Am 12. Dezember 2024 08:52:07 UTC schrieb Nicholas Piggin :
>The TI TUSB73X0 controller has some interesting differences from NEC,
>notably a separate BAR for MSIX, and PM capabilities. The spec is freely
>available without sign-up.
>
>This controller is accepted by IBM Power proprietary firmwar
On Thu Dec 19, 2024 at 4:21 AM AEST, Philippe Mathieu-Daudé wrote:
> When running Clang static analyzer on macOS I'm getting:
>
> include/qemu/osdep.h:634:8: error: redefinition of 'iovec'
> 634 | struct iovec {
> |^
>
> /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/u
On Thu Dec 19, 2024 at 5:18 AM AEST, BALATON Zoltan wrote:
> On Wed, 18 Dec 2024, Philippe Mathieu-Daudé wrote:
> > The ePAPR magic value in $r6 doesn't need to be byte swapped.
> >
> > See ePAPR-v1.1.pdf chapter 5.4.1 "Boot CPU Initial Register State"
> > and the following mailing-list thread:
> >
On Thu Dec 19, 2024 at 4:21 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert HPTE_VALID() macro as hpte_is_valid() method.
> Since sPAPR is in big endian configuration at reset,
> use the big endian LD/ST API to access the hash PTEs.
My knowlege of old platforms isn't great here, but I believe sPA
On Thu Dec 19, 2024 at 4:21 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert HPTE_DIRTY() macro as hpte_is_dirty() method.
> Since sPAPR is in big endian configuration at reset,
> use the big endian LD/ST API to access the HPTEs.
>
> Signed-off-by: Philippe Mathieu-Daudé
All the other helper chan
On Thu Dec 19, 2024 at 4:21 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert CLEAN_HPTE() macro as hpte_set_clean() method.
> Since sPAPR is in big endian configuration at reset,
> use the big endian LD/ST API to access the HPTEs.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: Philippe Mathieu-
On Thu Dec 19, 2024 at 4:21 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert DIRTY_HPTE() macro as hpte_set_dirty() method.
> Since sPAPR is in big endian configuration at reset,
> use the big endian LD/ST API to access the HPTEs.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Philippe Mathieu-
在 2024/12/19 06:37, Qu Wenruo 写道:
在 2024/12/19 02:22, Naresh Kamboju 写道:
On Wed, 18 Dec 2024 at 17:33, Naresh Kamboju
wrote:
The following kernel crash noticed on qemu-arm64 while running the
Linux next-20241210 tag (to next-20241218) kernel built with
- CONFIG_ARM64_64K_PAGES=y
On Thu Dec 19, 2024 at 4:21 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert HPTE() macro as hpte_get() method.
>
> Signed-off-by: Philippe Mathieu-Daudé
Nitpick, could we call this hpte_ptr() or hpte_get_ptr()?
Reviewed-by: Nicholas Piggin
> ---
> hw/ppc/spapr.c | 38 ++--
On 18.12.24 22:09, Stefan Hajnoczi wrote:
On Wed, 18 Dec 2024 at 05:55, David Hildenbrand wrote:
The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu
into staging (2024-12-16 14:20:33 -050
From: "Fea.Wang"
The spec explicitly says svukte doesn't support RV32. So check that it
is not enabled in RV32.
Signed-off-by: Fea.Wang
Reviewed-by: Alistair Francis
Message-ID: <20241203034932.25185-7-fea.w...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/tcg/tcg-cpu.c | 5 ++
From: Jim Shu
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241120153935.24706-3-jim@sifive.com>
Signed-off-by: Alistair Francis
---
includ
From: Daniel Henrique Barboza
ssstateen is defined in RVA22 as:
"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."
Add ssstateen as a named feature that is available if we also have
s
From: Jason Chien
>From RISCV IOMMU spec section 2.1.3:
When SXL is 1, the following rules apply:
- If the first-stage is not Bare, then a page fault corresponding to the
original access type occurs if the IOVA has bits beyond bit 31 set to 1.
- If the second-stage is not Bare, then a guest page
From: Daniel Henrique Barboza
Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to dis
From: Philippe Mathieu-Daudé
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/vector_internals.h:36:12: error: call to undeclared function
'FIELD_EX32'; ISO C99 and later do not support implicit function declarations
From: MollyChen
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Ba
From: Philippe Mathieu-Daudé
Looking at htif_mm_ops[] read/write handlers, we notice they
expect 32-bit values to accumulate into to the 'fromhost' and
'tohost' 64-bit variables. Explicit by setting the .impl
min/max fields.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Revi
From: Daniel Henrique Barboza
Also add a new page, docs/specs/riscv-aia.rst, where we're documenting
the state of AIA support in QEMU w.r.t the controllers being emulated or
not depending on the AIA and accelerator settings.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
From: Sai Pavan Boddu
Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x8000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial co
From: Jim Shu
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241120153935.24706-4-jim@sifive.com>
Signed-off
From: Daniel Henrique Barboza
Remove the 'irqchip_split()' restriction in kvm_arch_init() now that
we have support for "-accel kvm,kernel-irqchip=split".
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241119191706.718860-8-dbarb...@ventanamicro.com>
Signed-
From: "Fea.Wang"
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Message-ID: <20241203034932.25185-6-fea.w...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cp
From: Daniel Henrique Barboza
The helper is_kvm_aia() is checking not only for AIA, but for
aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an
in-kernel chip present.
Rename it to be a bit clear what the helper is doing since we'll add
more AIA helpers in the next patches.
Ma
From: "Fea.Wang"
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's addr
From: Philippe Mathieu-Daudé
The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20241129154304.34946-2-phi...@linaro.org>
Signed-
From: Philippe Mathieu-Daudé
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
49 | ret = PRV_S;
| ^
target/riscv/intern
From: Philippe Mathieu-Daudé
Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.
In that case tswap64() is equivalent to le64_to_cpu(), as
From: "Fea.Wang"
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed
From: Sia Jee Heng
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/
From: "Fea.Wang"
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKT
From: Sunil V L
Add a new machine option called 'iommu-sys' that enables a
riscv-iommu-sys platform device for the 'virt' machine. The option is
default 'off'.
The device will use IRQs 36 to 39.
We will not support both riscv-iommu-sys and riscv-iommu-pci devices in
the same board in this first
From: "Fea.Wang"
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U
From: Tomasz Jeznach
This device models the RISC-V IOMMU as a sysbus device. The same design
decisions taken in the riscv-iommu-pci device were kept, namely the
existence of 4 vectors are available for each interrupt cause.
The WSIs are emitted using the input of the s->notify() callback as a
in
From: Daniel Henrique Barboza
Add a riscv_iommu_reset() helper in the base emulation code that
implements the expected reset behavior as defined by the riscv-iommu
spec.
Devices can then use this helper in their own reset callbacks.
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Fra
From: Sia Jee Heng
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/
From: Daniel Henrique Barboza
Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c,
the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with
in-kernel irqchip enabled. It is not checking for a generic AIA support.
Rename the helper to virt_use_kvm_aia_aplic_imsi
From: Jim Shu
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <202411
From: Anton Blanchard
Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon
Signed-off-by: Anton Blanchard
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <202411
From: Yong-Xuan Wang
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectif
On Wed, Dec 18, 2024 at 06:32:05PM +0100, Markus Armbruster wrote:
> Michael Roth writes:
>
> > The GHCB specification[1] defines a VMGEXIT-based Guest Request
> > hypercall to allow an SNP guest to issue encrypted requests directly to
> > SNP firmware to do things like query the attestation repo
On Wed, Dec 18, 2024 at 05:50:52PM +, Daniel P. Berrangé wrote:
> On Wed, Dec 18, 2024 at 09:49:39AM -0600, Michael Roth wrote:
> > The GHCB specification[1] defines a VMGEXIT-based Guest Request
> > hypercall to allow an SNP guest to issue encrypted requests directly to
> > SNP firmware to do
From: Daniel Henrique Barboza
In create_fdt_sockets() we have the following pattern:
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do stuff ...)
} else {
(... do other stuff ...)
}
if (kvm_enabled() && virt_use_kvm_aia(s)) {
(... do more stuff ...)
From: Daniel Henrique Barboza
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20241106133407.604587-8-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
---
docs/specs/riscv-iommu.rst | 30 +++---
docs/system/riscv/virt.rst | 1
From: Sia Jee Heng
Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID: <20241028015744.624943-2-jeeheng@starfivetech.com>
Signed-off-by: Alistair Francis
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --gi
From: Daniel Henrique Barboza
The current logic to determine if we don't need an emulated APLIC
controller, i.e. KVM will provide for us, is to determine if we're
running KVM, with in-kernel irqchip support, and running
aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and
virt_
From: Daniel Henrique Barboza
The last step to enable KVM AIA aplic-imsic with irqchip in split mode
is to deal with how MSIs are going to be sent. In our current design we
don't allow an APLIC controller to send MSIs unless it's on m-mode. And
we also do not allow Supervisor MSI address configur
From: Daniel Henrique Barboza
Before adding support to kernel-irqchip=split when using KVM AIA we need
to change how we create the in-kernel AIA device.
In the use case we have so far, i.e. in-kernel irqchip without split
mode, both the s-mode APLIC and IMSIC controllers are provided by the
irqc
From: Daniel Henrique Barboza
MSIx support is added in the RISC-V IOMMU platform device by including
the required MSIx facilities to alow software to properly setup the MSIx
subsystem.
We took inspiration of what is being done in the riscv-iommu-pci device,
mainly msix_init() and msix_notify(),
From: Daniel Henrique Barboza
Move all the static initializion of the device to an init() function,
leaving only the dynamic initialization to be done during realize.
With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
init(), and realize() will increment s->cap with the extra
From: Daniel Henrique Barboza
Interrupt Generation Support (IGS) is a capability that is tied to the
interrupt deliver mechanism, not with the core IOMMU emulation. We
should allow device implementations to set IGS as they wish.
A new helper is added to make it easier for device impls to set IGS
The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu
into staging (2024-12-16 14:20:33 -0500)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-t
On Wed, 2024-12-18 at 16:54 +0100, Thomas Huth wrote:
> On 18/12/2024 12.48, David Woodhouse wrote:
> > On 18 December 2024 12:32:49 CET, Thomas Huth wrote:
> > > Use the serial console to execute the commands in the guest instead
> > > of using ssh since we don't have ssh support in the functiona
On Wed, 2024-12-18 at 22:42 +0100, David Woodhouse wrote:
>
> It seems like it's because of the way QEMU handles shared level-
> triggered interrupts.
Yeah, this hack seems to confirm it. As I said, PCI INTx manages to
demux correctly, but any time you have non-PCI interrupt sharing, it's
hosed b
On Wed, Dec 18, 2024 at 06:08:01PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Wed, Dec 18, 2024 at 03:13:08PM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Wed, Nov 13, 2024 at 04:46:27PM -0300, Fabiano Rosas wrote:
> >> >> diff --git a/tests/qtest/migration-test
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