Re: [PATCH 06/26] rust: add a bit operation module

On Mon, Dec 09, 2024 at 01:36:57PM +0100, Paolo Bonzini wrote: > Date: Mon, 9 Dec 2024 13:36:57 +0100 > From: Paolo Bonzini > Subject: [PATCH 06/26] rust: add a bit operation module > X-Mailer: git-send-email 2.47.1 > > The bindgen supports `static inline` function binding since v0.64.0 as > an

Re: [RFC PATCH v2 03/15] s390x/cpumodel: add msa12 changes

On 12/9/24 4:54 PM, Hendrik Brueckner wrote: On Mon, Dec 09, 2024 at 04:45:25PM +0100, Janosch Frank wrote: On 12/9/24 4:24 PM, Hendrik Brueckner wrote: On Mon, Dec 09, 2024 at 03:48:11PM +0100, Janosch Frank wrote: On 12/6/24 1:27 PM, Hendrik Brueckner wrote: MSA12 changes the KIMD/KLMD inst

Re: [QEMU PATCH v10] xen/passthrough: use gsi to map pirq when dom0 is PVH

On 2024/11/19 00:05, Anthony PERARD wrote: > On Wed, Nov 06, 2024 at 02:14:18PM +0800, Jiqian Chen wrote: >> In PVH dom0, when passthrough a device to domU, QEMU code >> xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes >> the gsi number is got from file /sys/bus/pci/device

[PATCH] ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5

Each non-core chiplet on a chip has a "pervasive chiplet" unit and its xscom register set. This adds support for PHB4/5. skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(), which shows up as unimplemented xscom reads. Set a value in PCI CONF1 register's link-width field to demo

Re: [PATCH 05/26] rust: add bindings for interrupt sources

On Mon, Dec 09, 2024 at 01:36:56PM +0100, Paolo Bonzini wrote: > Date: Mon, 9 Dec 2024 13:36:56 +0100 > From: Paolo Bonzini > Subject: [PATCH 05/26] rust: add bindings for interrupt sources > X-Mailer: git-send-email 2.47.1 > > The InterruptSource bindings let us call qemu_set_irq() and sysbus_i

Re: [PATCH 04/26] rust: define prelude

On Mon, Dec 09, 2024 at 01:36:55PM +0100, Paolo Bonzini wrote: > Date: Mon, 9 Dec 2024 13:36:55 +0100 > From: Paolo Bonzini > Subject: [PATCH 04/26] rust: define prelude > X-Mailer: git-send-email 2.47.1 > > Add a module that will contain frequently used traits and > occasionally structs. They

[PATCH] qemu-ga-win: Fix a typo error

There is a typo error for api 'guest-get-osinfo', the win2025's version in WIN_10_0_SERVER_VERSION_MATRIX should be adjusted. Signed-off-by: Dehan Meng --- qga/commands-win32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qga/commands-win32.c b/qga/commands-win32.c index 0

Re: [PATCH] hw/misc/vmfwupdate: Introduce hypervisor fw-cfg interface support

On Mon, Dec 2, 2024 at 1:17 PM Ani Sinha wrote: > > > > > On 29 Nov 2024, at 3:42 PM, Philippe Mathieu-Daudé > > wrote: > > > > On 29/11/24 10:16, Ani Sinha wrote: > >> VM firmware update is a mechanism where the virtual machines can use their > >> preferred and trusted firmware image in their e

Re: (Proposal) New TDX Global Metadata To Report FIXED0 and FIXED1 CPUID Bits

On 12/7/2024 2:41 AM, Edgecombe, Rick P wrote: On Fri, 2024-12-06 at 10:42 +0800, Xiaoyao Li wrote: # Interaction with TDX_FEATURES0.VE_REDUCTION TDX introduces a new feature VE_REDUCTION[2]. From the perspective of host VMM, VE_REDUCTION turns several CPUID bits from fixed1 to configurable, e.

[PATCH 7/9] ppc/pnv/occ: Update pstate frequency tables

Make each pstate have a different frequency, because that's easier to observe and test. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 918b08ba2ff..5567fbf008e 100644 --- a/

[PATCH 4/9] ppc/pnv/homer: class-based base and size

Put HOMER memory region base and size into the class, to allow more code-reuse between different machines in later changes. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv.h | 6 ++--- include/hw/ppc/pnv_homer.h | 7 +- hw/ppc/pnv_homer.c | 46 ++

[PATCH 5/9] ppc/pnv/occ: Better document OCCMISC bits

Use defines for the OCCMISC register bits, and add a comment about the IRQ request bit, which QEMU may not model quite correctly. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_o

[PATCH 6/9] ppc/pnv: Make HOMER memory a RAM region

The HOMER is a region of memory used by host and firmware and microconrollers. It has very little logic by itself, just some BAR registers. Users of this memory should operate on it rather than have HOMER implement them with MMIO registers, which is not the right model. This change switches the im

[PATCH 9/9] ppc/pnv/occ: Implement a basic dynamic OCC model

The OCC is an On Chip Controller that handles various thermal and power management. It is a PPC405 microcontroller that runs its own firmware which is out of scope of the powernv machine model. Some dynamic behaviour and interfaces that are important for host CPU testing can be implemented with a m

[PATCH 8/9] ppc/pnv/occ: Add POWER10 OCC-OPAL data format

Add POWER10 OCC-OPAL data format. POWER10 changes major version and adds a few fields. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 43 ++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 556

[PATCH 1/9] ppc/pnv/homer: Fix OCC registers

The HOMER OCC registers seem to have bitrotted and fail for various reasons on powernv8, 9, and 10. The major problems are that POWER8 has the wrong version value and its pstate ordering is incorrect. POWER9/10 have not set the OCC state to active. Non-zero chips are also set to OCC slaves for POW

[PATCH 3/9] ppc/pnv/occ: Fix common area sensor offsets

The commit to fix the OCC common area sensor mappings didn't update the register offsets to match. Before this change, skiboot reports: [0.347100086,3] OCC: Chip 0 sensor data invalid Afterward, there is no error and the sensor_groups directory appears under /sys/firmware/opal/. The SLW_IMA

[PATCH 0/9] ppc/pnv: HOMER and OCC fixes and improvements

This series makes a bunch of fixes and improvements to the HOMER and OCC unit models for powernv. It gets OPAL OCC code happier again, but requires this series of skiboot fixes (which I will hope to get upstream and then into QEMU in the same release as this series is merged. https://lists.ozlabs.

[PATCH 2/9] ppc/pnv/homer: Make dummy reads return 0

HOMER memory implements some dummy registers that return a nonsense value to satisfy skiboot accesses caused by "SLW" init and register save/restore programming that has never worked under QEMU: [0.265000943,3] SLW: Failed to set HRMOR for CPU 0,RC=0x1 [0.265356988,3] Disabling deep stop s

Re: [PATCH 00/26] rust: bundle of prerequisites for HPET implementation

On Mon, Dec 09, 2024 at 06:23:21PM +0100, Paolo Bonzini wrote: > Date: Mon, 9 Dec 2024 18:23:21 +0100 > From: Paolo Bonzini > Subject: Re: [PATCH 00/26] rust: bundle of prerequisites for HPET > implementation > > On Mon, Dec 9, 2024 at 5:24 PM Philippe Mathieu-Daudé > wrote: > > > > On 9/12/24

Re: [PATCH 16/17] target/hexagon: Use mulu64 for int128_mul_6464

On 12/8/2024 4:48 PM, Richard Henderson wrote: No need to open-code 64x64->128-bit multiplication. Signed-off-by: Richard Henderson --- target/hexagon/fma_emu.c | 32 +++- 1 file changed, 3 insertions(+), 29 deletions(-) diff --git a/target/hexagon/fma_emu.c b/

Re: [PATCH 17/17] target/hexagon: Simplify internal_mpyhh setup

On 12/8/2024 4:48 PM, Richard Henderson wrote: Initialize x with accumulated via direct assignment, rather than multiplying by 1. Signed-off-by: Richard Henderson --- target/hexagon/fma_emu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/fma_emu.c b/tar

Re: [PATCH 10/17] target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc

On 12/8/2024 4:48 PM, Richard Henderson wrote: This instruction has a special case that 0 * x + c returns c without the normal sign folding that comes with 0 + -0. Use the new float_muladd_suppress_add_product_zero to describe this. Signed-off-by: Richard Henderson --- target/hexagon/op_hel

Re: [PATCH 09/17] target/hexagon: Use float32_muladd for helper_sffms

On 12/8/2024 4:48 PM, Richard Henderson wrote: There are no special cases for this instruction. Since hexagon always uses default-nan mode, explicitly negating the first input is unnecessary. Use float_muladd_negate_product instead. Signed-off-by: Richard Henderson --- target/hexagon/op_h

Re: [PATCH 08/17] target/hexagon: Use float32_muladd for helper_sffma

On 12/8/2024 4:48 PM, Richard Henderson wrote: There are no special cases for this instruction. Signed-off-by: Richard Henderson --- target/hexagon/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index

Re: [PATCH 07/17] target/hexagon: Use float32_mul in helper_sfmpy

On 12/8/2024 4:48 PM, Richard Henderson wrote: There are no special cases for this instruction. Remove internal_mpyf as unused. Signed-off-by: Richard Henderson --- target/hexagon/fma_emu.h | 1 - target/hexagon/fma_emu.c | 8 target/hexagon/op_helper.c | 2 +- 3 files chang

Re: [External] : Re: [RFC PATCH 0/1] ACPI: Fix missing CPU hotplug/hotunplug events with > 255 vCPUs

On Mon, 9 Dec 2024 15:36:06 +0100 Igor Mammedov imamm...@redhat.com wrote: > On Tue, 3 Dec 2024 16:56:35 -0800 > Eric Mackay eric.mac...@oracle.com wrote: > >> ACPI hotplug with 255 or less vCPUs can use the legacy CPU hotplug >> interf

[PATCH v2 03/14] ppc/xive2: Support group-matching when looking for target

From: Frederic Barrat If an END has the 'i' bit set (ignore), then it targets a group of VPs. The size of the group depends on the VP index of the target (first 0 found when looking at the least significant bits of the index) so a mask is applied on the VP index of a running thread to know if we

[PATCH v2 07/14] ppc/xive2: Process group backlog when updating the CPPR

From: Frederic Barrat When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB value is lower than the new CPPR value, there could be a pending group interrupt in the backlog, so it needs to be scanned. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/p

[PATCH v2 13/14] pnv/xive: Fix problem with treating NVGC as a NVP

From: Glenn Miles When booting with PHYP, the blk/index for a NVGC was being mistakenly treated as the blk/index for a NVP. Renamed nvp_blk/nvp_idx throughout the code to nvx_blk/nvx_idx to prevent confusion in the future and now we delay loading the NVP until the point where we know that the bl

[PATCH v2 10/14] ppc/xive2: Support crowd-matching when looking for target

From: Frederic Barrat XIVE crowd sizes are encoded into a 2-bit field as follows: 0: 0b00 2: 0b01 4: 0b10 16: 0b11 A crowd size of 8 is not supported. If an END is defined with the 'crowd' bit set, then a target can be running on different blocks. It means that some bits from the block V

[PATCH v2 05/14] ppc/xive2: Add undelivered group interrupt to backlog

From: Frederic Barrat When a group interrupt cannot be delivered, we need to: - increment the backlog counter for the group in the NVG table (if the END is configured to keep a backlog). - start a broadcast operation to set the LSMFB field on matching CPUs which can't take the interrupt now b

[PATCH v2 11/14] pnv/xive: Only support crowd size of 0, 2, 4 and 16

From: Glenn Miles XIVE crowd sizes are encoded into a 2-bit field as follows: 0: 0b00 2: 0b01 4: 0b10 16: 0b11 A crowd size of 8 is not supported. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal --- hw/intc/xive.c | 21 - 1 file changed, 20 insertions(+), 1

[PATCH v2 14/14] qtest/xive: Add test of pool interrupts

From: Glenn Miles Added new test for pool interrupts. Removed all printfs from pnv-xive2-* qtests. Signed-off-by: Glenn Miles Signed-off-by: Michael Kowal --- tests/qtest/pnv-xive2-flush-sync.c | 6 +- tests/qtest/pnv-xive2-nvpg_bar.c | 7 +-- tests/qtest/pnv-xive2-test.c | 98 +++

[PATCH v2 09/14] ppc/xive2: Support crowd-matching when looking for target

From: Frederic Barrat If an END is defined with the 'crowd' bit set, then a target can be running on different blocks. It means that some bits from the block VP are masked when looking for a match. It is similar to groups, but on the block instead of the VP index. Most of the changes are due to

[PATCH v2 09/14] ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR

From: Frederic Barrat Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment the counter. Also added qtests for the same. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2.h

[PATCH v2 06/14] ppc/xive2: Process group backlog when updating the CPPR

From: Frederic Barrat When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB value is lower than the new CPPR value, there could be a pending group interrupt in the backlog, so it needs to be scanned. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/p

[PATCH v2 04/14] ppc/xive2: Support group-matching when looking for target

From: Frederic Barrat If an END has the 'i' bit set (ignore), then it targets a group of VPs. The size of the group depends on the VP index of the target (first 0 found when looking at the least significant bits of the index) so a mask is applied on the VP index of a running thread to know if we

[PATCH v2 12/14] pnv/xive: Support ESB Escalation

From: Glenn Miles END notification processing has an escalation path. The escalation is not always an END escalation but can be an ESB escalation. Also added a check for 'resume' processing which log a message stating it needs to be implemented. This is not needed at the time but is part of th

[PATCH v2 10/14] ppc/xive2: Check crowd backlog when scanning group backlog

From: Frederic Barrat When processing a backlog scan for group interrupts, also take into account crowd interrupts. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2_regs.h | 4 ++ hw/intc/xive2.c | 82 + 2 fi

[PATCH v2 08/14] qtest/xive: Add group-interrupt test

From: Frederic Barrat Add XIVE2 tests for group interrupts and group interrupts that have been backlogged. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- tests/qtest/pnv-xive2-test.c | 160 +++ 1 file changed, 160 insertions(+) diff --git a/te

[PATCH v2 11/14] ppc/xive2: Check crowd backlog when scanning group backlog

From: Frederic Barrat When processing a backlog scan for group interrupts, also take into account crowd interrupts. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2_regs.h | 4 ++ hw/intc/xive2.c | 82 + 2 fi

[PATCH v2 08/14] Add support for MMIO operations on the NVPG/NVC BAR

From: Frederic Barrat Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment the counter. Also added qtests for the same. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2.h

[PATCH v2 07/14] qtest/xive: Add group-interrupt test

From: Frederic Barrat Add XIVE2 tests for group interrupts and group interrupts that have been backlogged. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- tests/qtest/pnv-xive2-test.c | 160 +++ 1 file changed, 160 insertions(+) diff --git a/te

[PATCH v2 05/14] ppc/xive2: Process group backlog when pushing an OS context

From: Frederic Barrat When pushing an OS context, we were already checking if there was a pending interrupt in the IPB and sending a notification if needed. We also need to check if there is a pending group interrupt stored in the NVG table. To avoid useless backlog scans, we only scan if the NV

[PATCH v2 02/14] ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr()

Renamed function to follow the convention of the other function names. Signed-off-by: Michael Kowal --- include/hw/ppc/xive.h | 16 hw/intc/xive.c| 22 ++ 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/include/hw/ppc/xive.h b/include

[PATCH v2 06/14] ppc/xive2: Process group backlog when pushing an OS context

From: Frederic Barrat When pushing an OS context, we were already checking if there was a pending interrupt in the IPB and sending a notification if needed. We also need to check if there is a pending group interrupt stored in the NVG table. To avoid useless backlog scans, we only scan if the NV

[PATCH v2 02/14] ppc/xive2: Add grouping level to notification

From: Frederic Barrat The NSR has a (so far unused) grouping level field. When a interrupt is presented, that field tells the hypervisor or OS if the interrupt is for an individual VP or for a VP-group/crowd. This patch reworks the presentation API to allow to set/unset the level when raising/acc

[PATCH v2 03/14] ppc/xive2: Add grouping level to notification

From: Frederic Barrat The NSR has a (so far unused) grouping level field. When a interrupt is presented, that field tells the hypervisor or OS if the interrupt is for an individual VP or for a VP-group/crowd. This patch reworks the presentation API to allow to set/unset the level when raising/acc

[PATCH v2 04/14] ppc/xive2: Add undelivered group interrupt to backlog

From: Frederic Barrat When a group interrupt cannot be delivered, we need to: - increment the backlog counter for the group in the NVG table (if the END is configured to keep a backlog). - start a broadcast operation to set the LSMFB field on matching CPUs which can't take the interrupt now b

[PATCH v2 01/14] ppc/xive2: Update NVP save/restore for group attributes

From: Frederic Barrat If the 'H' attribute is set on the NVP structure, the hardware automatically saves and restores some attributes from the TIMA in the NVP structure. The group-specific attributes LSMFB, LGS and T have an extra flag to individually control what is saved/restored. Signed-off-b

[PATCH v2 00/14] XIVE2 changes to support Group and Crowd operations

XIVE2 has the concepts of a Group of interrupts and a Crowd of interrupts (where a crowd is a group of Groups). These patch sets are associated with: - NVGC tables - Group/Crowd level notification - Incrementing backlog countets - Backlog processing - NVPG and NVC Bar MMIO operations - Group/

[RFC 3/3] hw/net/can: WIP CTU CAN FD add parameter to specify IRQ controller on command line

From: Pavel Pisa Signed-off-by: Pavel Pisa --- hw/net/can/ctucan_mm.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/net/can/ctucan_mm.c b/hw/net/can/ctucan_mm.c index 6d6b8aecb8..e599df18be 100644 --- a/hw/net/can/ctucan_mm.c +++ b/hw/net/can/ctucan

[RFC 2/3] hw/net/can: WIP CTU CAN FD mapping of IRQ for platform device solved.

From: Pavel Pisa Signed-off-by: Pavel Pisa --- hw/net/can/ctucan_mm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/net/can/ctucan_mm.c b/hw/net/can/ctucan_mm.c index 43e6823b73..6d6b8aecb8 100644 --- a/hw/net/can/ctucan_mm.c +++ b/hw/net/can/ctucan_mm.c @@ -160,6 +160,9 @@ static v

[RFC 1/3] hw/net/can: WIP CTU CAN FD IP core mapping to the platform bus

From: Pavel Pisa It is initial attempt (IRQ not working yet) to provide alternative to PCIe mapping. In this case, the platform bus is used to match FPGA design for Xilinx Zynq MZ_APO education kit with four CTU CAN FD cores on branch mz_apo-2x-xcan-4x-ctu of repo https://gitlab.fel.cvut.cz/ca

[RFC/WIP 0/3] WIP CTU CAN FD IP core mapping to the platform bus

From: Pavel Pisa Hello Peter, Gustavo and others, our CTU CAN FD IP core is used on many FPGA platforms and has been even tapeout on some other university and even prototypes of the massive production chips (support for that organized by our former student in his company). But actual QEMU emula

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 12/9/24 5:09 PM, David Hildenbrand wrote: > On 09.12.24 22:45, Matthew Rosato wrote: >> On 12/9/24 4:01 PM, David Hildenbrand wrote: >>> On 09.12.24 20:29, Matthew Rosato wrote: >>> >>> Hi, >>> >>> Trying to wrap my head around that ... you mention that "pin the entirety >>> of guest memory". >

Re: [RFC PATCH v3 23/26] hw/tpm: Add TPM event log

On 11/25/24 2:56 PM, Jean-Philippe Brucker wrote: Provide a library allowing the VMM to create an event log that describes what is loaded into memory. During remote attestation in confidential computing this helps an independent verifier reconstruct the initial measurements of a VM, which cont

Re: [PATCH v3 2/3] docs/devel/style: add a section about bitfield, and disallow them for packed structures

Hi Philippe, On 12/9/24 12:33, Philippe Mathieu-Daudé wrote: On 28/11/24 21:15, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- docs/devel/style.rst | 20 1 file changed, 20 insertions(+) diff --git a/docs/devel/style.rst b/docs/devel/style.rst index 2f68

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 09.12.24 22:45, Matthew Rosato wrote: On 12/9/24 4:01 PM, David Hildenbrand wrote: On 09.12.24 20:29, Matthew Rosato wrote: Hi, Trying to wrap my head around that ... you mention that "pin the entirety of guest memory". Do you mean that we will actually end up longterm pinning all guest R

Re: [RFC PATCH v3 25/26] target/arm/kvm-rme: Add measurement log

On 11/25/24 2:56 PM, Jean-Philippe Brucker wrote: Create an event log, in the format defined by Trusted Computing Group s/,// for TPM2. It contains information about the VMM, the Realm parameters, any data loaded into guest memory before boot and the initial vCPU s/ and/ ,and/ [move com

Re: [PATCH-for-10.0] system/qtest: Access memory using cpu_physical_memory_rw() API

On 9/12/24 21:34, Fabiano Rosas wrote: Fabiano Rosas writes: Philippe Mathieu-Daudé writes: There is no vCPU within the QTest accelerator (well, they are stubs doing nothing, see dummy_cpu_thread_fn). Directly use the cpu_physical_memory_rw() API -- which amusingly prefixed 'cpu_' does not

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 12/9/24 4:01 PM, David Hildenbrand wrote: > On 09.12.24 20:29, Matthew Rosato wrote: > > Hi, > > Trying to wrap my head around that ... you mention that "pin the entirety of > guest memory". > > Do you mean that we will actually end up longterm pinning all guest RAM in > the kernel, similar

Re: [PATCH v3 0/7] hugetlbfs memory HW error fixes

On 06.12.24 19:26, William Roche wrote: On 12/3/24 16:00, David Hildenbrand wrote: On 03.12.24 15:39, William Roche wrote: [...] Our new Qemu code is testing first the fallocate+MADV_DONTNEED procedure for standard sized pages (in ram_block_discard_range()) and only folds back to the mmap() use

Re: [PATCH 2/6] tests/qtest/migration: Initialize buffer in probe_o_direct_support

On Mon, Dec 09, 2024 at 05:44:23PM -0300, Fabiano Rosas wrote: > Valgrind complains about the probe_o_direct_support() function reading > from an uninitialized buffer. For probing O_DIRECT support we don't > actually need to write to the file, just make sure the pwrite call > doesn't reject the wri

Re: [PATCH 03/11] i386/hvf: Don't send signal to thread when kicking

On 9/12/24 21:36, p...@philjordan.eu wrote: From: Phil Dennis-Jordan This seems to be entirely superfluous and is costly enough to show up in So the pthread_kill(cpu->thread, SIG_IPI) is entirely superfluous? profiling. hv_vcpu_interrupt() has been demonstrated to very reliably cause VM exi

Re: [PATCH v2 1/3] migration/multifd: move macros to multifd header

Prasad Pandit writes: > From: Prasad Pandit > > Move MULTIFD_ macros to the header file so that > they are accessible from other source files. > > Signed-off-by: Prasad Pandit Reviewed-by: Fabiano Rosas

Re: [PATCH 1/6] tests/qtest/migration: Do proper cleanup in the dirty_limit test

On Mon, Dec 09, 2024 at 05:44:22PM -0300, Fabiano Rosas wrote: > The dirty_limit test does two migrations in a row and is leaking the > first 'to' instance. Do proper cleanup. > > Signed-off-by: Fabiano Rosas Reviewed-by: Peter Xu -- Peter Xu

Re: [PATCH] hostmem-file: add the 'hmem' option

On 06.12.24 18:58, Luo, Zhigang wrote: [AMD Official Use Only - AMD Internal Distribution Only] Hi David, Hi! Thanks for your comments. Let me give you some background for this patch. I am currently engaged in a project that requires to pass the EFI_MEMORY_SP (Special Purpose Memory) type

Re: [PATCH 4/6] tests/qtest/virtio-iommu-test: Don't pass uninitialized data into qtest_memwrite

On 9/12/24 21:44, Fabiano Rosas wrote: Valgrind complains about: Use of uninitialised value of size 8 & Conditional jump or move depends on uninitialised value(s) both at: at 0x5265931: _itoa_word (_itoa.c:180) by 0x527EEC7: __vfprintf_internal (vfprintf-internal.c:1687) by 0x528C8B

Re: [PATCH 3/6] tests/qtest/bios-tables-test: Free tables at dump_aml_files

On 9/12/24 21:44, Fabiano Rosas wrote: The dump_aml_files() function calls load_expected_aml() to allocate the tables but never frees it. Add the missing call to free_test_data(). This is also Coverity CID 1549449 (RESOURCE_LEAK) Signed-off-by: Fabiano Rosas --- tests/qtest/bios-tables-te

Re: [PATCH 2/6] tests/qtest/migration: Initialize buffer in probe_o_direct_support

On 9/12/24 21:44, Fabiano Rosas wrote: Valgrind complains about the probe_o_direct_support() function reading from an uninitialized buffer. For probing O_DIRECT support we don't actually need to write to the file, just make sure the pwrite call doesn't reject the write. Still, write zeroes to the

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 09.12.24 20:29, Matthew Rosato wrote: When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T bit set, treat this as a request to perform direct mapping instead of address translation. In order to facilitiate this, pin the entirety of guest memory into the host iommu. Subsequ

Re: [PATCH v3 7/7] migration/multifd: Document the reason to sync for save_setup()

Peter Xu writes: > It's not straightforward to see why src QEMU needs to sync multifd during > setup() phase. After all, there's no page queued at that point. > > For old QEMUs, there's a solid reason: EOS requires it to work. While it's > clueless on the new QEMUs which do not take EOS message

Re: [PATCH v3 6/7] migration/multifd: Cleanup src flushes on condition check

Peter Xu writes: > The src flush condition check is over complicated, and it's getting more > out of control if postcopy will be involved. > > In general, we have two modes to do the sync: legacy or modern ways. > Legacy uses per-section flush, modern uses per-round flush. > > Mapped-ram always u

Re: [PATCH 10/11] hw/intc/apic: Fixes magic number use, removes outdated comment

On 9/12/24 21:36, p...@philjordan.eu wrote: From: Phil Dennis-Jordan This changes replaces the use of an explicit literal constant for the APIC base address mask with the existing symbolic constant intended for this purpose. Additionally, we remove the comment about not being able to re-enable

Re: [PATCH 09/11] i386/hvf: Print hex pairs for each opcode byte in decode error

On 9/12/24 21:36, p...@philjordan.eu wrote: From: Phil Dennis-Jordan Printing a sequence of bytes as hex with leading zeroes omitted just looks odd. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/x86_decode.c | 2 +- 1 file changed, 1 inserti

Re: [PATCH v3 2/7] migration/multifd: Allow to sync with sender threads only

Peter Xu writes: > Teach multifd_send_sync_main() to sync with threads only. > > We already have such requests, which is when mapped-ram is enabled with > multifd. In that case, no SYNC messages will be pushed to the stream when > multifd syncs the sender threads because there's no destination t

[PATCH 4/6] tests/qtest/virtio-iommu-test: Don't pass uninitialized data into qtest_memwrite

Valgrind complains about: Use of uninitialised value of size 8 & Conditional jump or move depends on uninitialised value(s) both at: at 0x5265931: _itoa_word (_itoa.c:180) by 0x527EEC7: __vfprintf_internal (vfprintf-internal.c:1687) by 0x528C8B0: __vsprintf_internal (iovsprintf.c:96)

Re: [PATCH 08/11] i386/hvf: Variable type fixup in decoder

On 9/12/24 21:36, p...@philjordan.eu wrote: From: Phil Dennis-Jordan decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Fixes: ff2de1668c9 ("i386: hvf: remove addr_t") Reviewed-by: Philippe Mathieu-Daudé Signed-of

[PATCH 00/11] hvf and APIC fixes, improvements, and optimisations

From: Phil Dennis-Jordan These patches are a loosely related series of changes that I've collected while working on the VMApple/PVG patch set and my doomed project of integrating Hypervisor.framework's APIC implementation. (The latter turns out to suffer from a number of serious bugs which preven

[PATCH 07/11] i386/hvf: Enables APIC_ACCESS VM exits by setting APICBASE

From: Phil Dennis-Jordan This change activates virtualised APIC access VM exits so the new fast-pathed implementation will be taken. Two parts are required for enabling APIC_ACCESS exits rather than falling back to "regular" MMIO EPT faults: Hypervisor.framework needs to know the current APIC ba

[PATCH 01/11] hvf: Add facility for initialisation code prior to first vCPU run

From: Phil Dennis-Jordan Some VM state required for fully configuring vCPUs is only available after all devices have been through their init phase. This extra function, called just before each vCPU makes its first VM entry, allows us to perform such architecture-specific initialisation. Signed-o

[PATCH 1/6] tests/qtest/migration: Do proper cleanup in the dirty_limit test

The dirty_limit test does two migrations in a row and is leaking the first 'to' instance. Do proper cleanup. Signed-off-by: Fabiano Rosas --- tests/qtest/migration-test.c | 5 + 1 file changed, 5 insertions(+) diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index 74

[PATCH 0/6] qtest: Fix some memory issues

I'm trying to get the qtests to run with asan/valgrind without any warnings so I can run a test before every PR. Here are a few fixes. CI run: https://gitlab.com/farosas/qemu/-/pipelines/1580782506 Fabiano Rosas (6): tests/qtest/migration: Do proper cleanup in the dirty_limit test tests/qtest

[PATCH 6/6] tests/qtest/test-x86-cpuid-compat: Free allocated memory

Free the test arguments after test execution. Signed-off-by: Fabiano Rosas --- tests/qtest/test-x86-cpuid-compat.c | 4 1 file changed, 4 insertions(+) diff --git a/tests/qtest/test-x86-cpuid-compat.c b/tests/qtest/test-x86-cpuid-compat.c index b9e7e5ef7b..45f35ab9b0 100644 --- a/tests/qt

[PATCH 2/6] tests/qtest/migration: Initialize buffer in probe_o_direct_support

Valgrind complains about the probe_o_direct_support() function reading from an uninitialized buffer. For probing O_DIRECT support we don't actually need to write to the file, just make sure the pwrite call doesn't reject the write. Still, write zeroes to the buffer to suppress the warning. Signed-

[PATCH 3/6] tests/qtest/bios-tables-test: Free tables at dump_aml_files

The dump_aml_files() function calls load_expected_aml() to allocate the tables but never frees it. Add the missing call to free_test_data(). Signed-off-by: Fabiano Rosas --- tests/qtest/bios-tables-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/

[PATCH 5/6] tests/qtest/qos-test: Plug a couple of leaks

The walk_path() function of qos-test.c, which walks the graph and adds tests to the test suite uses GLib's g_test_add_data_func_full() function: g_test_add_data_func_full (const char *testpath, gpointertest_data, GTestDataFunc tes

[PATCH 04/11] i386/hvf: Pre-fetch emulated instructions

From: Phil Dennis-Jordan The HVF x86 instruction decoder has previously read each instruction component a few bytes at a time. The HVF vCPU VM exit reports the length of the faulted instruction, so we can just pre-fetch the memory for the whole thing in one go, saving extra round-trips for most i

[PATCH 06/11] i386/hvf: APIC access exit with fast-path for common mov cases

From: Phil Dennis-Jordan The implementation of the EXIT_REASON_APIC_ACCESS vm exit handler has so far been essentially the same as a regular EPT fault handler, performing a full simulation of the faulted instruction. The code path has also not been used at all because the APIC base address setter

[PATCH 09/11] i386/hvf: Print hex pairs for each opcode byte in decode error

From: Phil Dennis-Jordan Printing a sequence of bytes as hex with leading zeroes omitted just looks odd. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/x86_decode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_dec

Re: [PATCH-for-10.0] system/qtest: Access memory using cpu_physical_memory_rw() API

Fabiano Rosas writes: > Philippe Mathieu-Daudé writes: > >> There is no vCPU within the QTest accelerator (well, they >> are stubs doing nothing, see dummy_cpu_thread_fn). >> Directly use the cpu_physical_memory_rw() API -- which >> amusingly prefixed 'cpu_' does not use vCPU -- to access >> mem

[PATCH 08/11] i386/hvf: Variable type fixup in decoder

From: Phil Dennis-Jordan decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/x86_decode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tar

[PATCH 02/11] arm/hvf: Initialise GICv3 state just before first vCPU run

From: Phil Dennis-Jordan Initialising the vCPU PFR0_EL1 system register with the GIC flag in hvf_arch_init_vcpu() does not actually work because the GIC state is not yet available at that time. If we set this flag just before running each vCPU for the first time, the GIC will definitely be fully

[PATCH 11/11] hw/intc/apic: Raise exception when setting reserved APICBASE bits

From: Phil Dennis-Jordan Signed-off-by: Phil Dennis-Jordan --- hw/intc/apic.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index d72cbb2a8f..83e626a45e 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -309,6 +309,11 @@ bool is_x2apic_mode(DeviceSta

[PATCH 03/11] i386/hvf: Don't send signal to thread when kicking

From: Phil Dennis-Jordan This seems to be entirely superfluous and is costly enough to show up in profiling. hv_vcpu_interrupt() has been demonstrated to very reliably cause VM exits - even if the target vCPU isn't even running, it will immediately exit on entry. Signed-off-by: Phil Dennis-Jorda

[PATCH 10/11] hw/intc/apic: Fixes magic number use, removes outdated comment

From: Phil Dennis-Jordan This changes replaces the use of an explicit literal constant for the APIC base address mask with the existing symbolic constant intended for this purpose. Additionally, we remove the comment about not being able to re-enable the APIC after disabling it. This is no longe

[PATCH 05/11] i386/hvf: Decode APIC access x86 instruction outside BQL

From: Phil Dennis-Jordan The HVF accelerator suffers from severe BQL contention under common practical workloads. x86 instruction decoding for software-emulating faulted instructions is a somewhat expensive operation, and there is no need to hold the BQL while performing it. Except in very unusua

Re: [PATCH v3 2/3] docs/devel/style: add a section about bitfield, and disallow them for packed structures

On 28/11/24 21:15, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- docs/devel/style.rst | 20 1 file changed, 20 insertions(+) diff --git a/docs/devel/style.rst b/docs/devel/style.rst index 2f68b500798..2d73e6a8f7a 100644 --- a/docs/devel/style.rst +++ b/docs

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