Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 29 +
I'm also very sorry, but I have a slightly different opinion...
> accel/tcg/user-exec-stub.c | 4 +++
> hw/core/cpu-common.c | 2 +-
> include/hw/core/cpu.h | 8 +
> system/cpus.c | 6 +++-
> target/alpha/cpu.c | 2 ++
> target/arm/cpu.c | 2 ++
Hi Xiaoyao,
Sorry for late reply.
> @@ -7490,6 +7489,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
> void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
> {
> CPUX86State *env = &cpu->env;
> +CPUState *cs = CPU(cpu);
> FeatureWord w;
> int i;
> GList
> After making empty promises for many months, I have finally written the
> Rust version of HPET :-) I'm also very grateful for the help from Paolo,
> Manos, and Junjie!
>
> Overall, HPET in Rust maintains the same logic as the original C
> version, adhering to the IA-HPET spec v1.0a [1]. While ke
Define HPETFwEntry structure with the same memory layout as
hpet_fw_entry in C.
Further, define the global hpet_fw_cfg variable in Rust which is the
same as the C version. This hpet_fw_cfg variable in Rust will replace
the C version one and allows both Rust code and C code to access it.
The Rust
Hi,
After making empty promises for many months, I have finally written the
Rust version of HPET :-) I'm also very grateful for the help from Paolo,
Manos, and Junjie!
Overall, HPET in Rust maintains the same logic as the original C
version, adhering to the IA-HPET spec v1.0a [1]. While keeping t
From: Paolo Bonzini
Similar to the existing BqlCell, introduce a custom interior mutability
primitive that resembles RefCell but accounts for QEMU's threading model.
Borrowing the RefCell requires proving that the BQL is held, and
attempting to access without the BQL is a runtime panic.
Almost a
HPET device (Rust device) needs to define the bit type property.
Add a variant of define_property macro to define bit type property.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/qdev.rs | 12
1 file changed, 12 insertions(+)
diff --git a/rust/qemu-api/src/qdev.rs b/rust/qemu-api/
The MemTxAttrs structure is composed of bitfield members, and bindgen is
unable to generate an equivalent macro definition for
MEMTXATTRS_UNSPECIFIED.
Therefore, we have to manually define a global constant variable
MEMTXATTRS_UNSPECIFIED to support calls from Rust code.
However, the binding meth
The bindgen supports `static inline` function binding since v0.64.0 as
an experimental feature (`--wrap-static-fns`), and stabilizes it after
v0.70.0.
But the oldest version of bindgen supported by QEMU is v0.60.1, so
there's no way to generate the bindings for timer_new() and its variants
which a
Add the HPETTimer and HPETState (HPET timer block), along with their
basic methods and register definitions.
This is in preparation for supporting the QAPI interfaces.
Note, wrap all items in HPETState that may be changed in the callback
called by C code into the BqlCell/BqlRefCell.
Signed-off-b
The get_mut() is useful when doing compound assignment operations, e.g.,
*c.get_mut() += 1.
Implement get_mut() for BqlCell by referring to Cell.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/cell.rs | 25 +
1 file changed, 25 insertions(+)
diff --git a/rust/qemu-api/sr
Add HPET configuration in PC's Kconfig options, and select HPET device
(Rust version) if Rust is supported.
Signed-off-by: Zhao Liu
---
hw/i386/Kconfig | 2 ++
hw/timer/Kconfig | 1 -
rust/hw/Kconfig | 1 +
rust/hw/timer/Kconfig | 2 ++
4 files changed, 5 insertions(+), 1 deleti
From: Paolo Bonzini
The Big QEMU Lock (BQL) is used to provide interior mutability to Rust
code. While BqlCell performs indivisible accesses, an equivalent of
RefCell will allow the borrower to hold to the interior content for a
long time. If the BQL is dropped, another thread could come and mu
Implement QAPI support for HPET device in qdev.rs.
Additionally, wrap the handling of HPET internal details as traits to be
specifically implemented in hpet.rs.
Signed-off-by: Zhao Liu
---
rust/hw/timer/hpet/src/fw_cfg.rs | 2 -
rust/hw/timer/hpet/src/hpet.rs | 232 +
The bindgen supports `static inline` function binding since v0.64.0 as
an experimental feature (`--wrap-static-fns`), and stabilizes it after
v0.70.0.
But the oldest version of bindgen supported by QEMU is v0.60.1, so
there's no way to generate the binding for deposit64() which is `static
inline`
HPET device needs to access and update hpet_cfg variable, but now it is
defined in hw/i386/fw_cfg.c and Rust code can't access it.
Move hpet_cfg definition to hpet.c (and rename it to hpet_fw_cfg). This
allows Rust HPET device implements its own global hpet_fw_cfg variable,
and will further reduce
The qdev_init_gpio_{in|out} are qdev interfaces, so that it's natural to
wrap them as DeviceState's methods in Rust API, which could eliminate
unsafe cases in the device lib.
Wrap qdev_init_gpio_{in|out} as methods in a new trait DeviceGPIOImpl.
In addition, for qdev_init_gpio_in(), to convert th
On Wed, 2024-12-04 at 12:39 -0800, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
> ---
> docs/system/arm/fby35.rst | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
> index bf6da6baa2a..ed9faef363c 100644
> --- a/docs/sy
On Wed, 2024-12-04 at 17:03 +0100, Mario Fleischmann wrote:
> Hi everyone,
>
> I'd like to chime in here because we are sitting on a similar patch
> which I wanted to send to the mailing list as soon as riscv-debug-spec
> v1.0.0 becomes ratified.
>
> For hypervisor support, `(qemu) info registe
I tested this patch with virtio-net regression tests, these changes
are working fine related to the virtio-net part.
Tested-by: Lei Yang
On Wed, Dec 4, 2024 at 2:27 AM Richard Henderson
wrote:
>
> On 12/3/24 11:24, Philippe Mathieu-Daudé wrote:
> > Headers in include/sysemu/ are not only relate
On 12/4/24 14:41, Philippe Mathieu-Daudé wrote:
Rather than manually copying each register, use
the libc memcpy(), which is well optimized.
Signed-off-by: Philippe Mathieu-Daudé
---
Worth renaming as reg8cpy()?
---
target/sparc/win_helper.c | 9 +
1 file changed, 1 insertion(+), 8 de
On 12/4/24 14:26, Philippe Mathieu-Daudé wrote:
Rather that using the binary endianness, use the vCPU one.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/generic-loader.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-
On 12/4/24 14:25, Philippe Mathieu-Daudé wrote:
Rather that using the binary endianness, use the vCPU one.
Signed-off-by: Philippe Mathieu-Daudé
---
disas/disas-common.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/disas/disas-common.c b/disas/disas-common.c
index 73
On 12/4/24 14:25, Philippe Mathieu-Daudé wrote:
arm_cpu_virtio_is_big_endian() already returns whether
the data path is in big endian. Re-use that.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
No, this is wrong.
(1)
On 12/4/24 14:25, Philippe Mathieu-Daudé wrote:
target_words_bigendian() doesn't return whether a target vCPU
expects data in big-endian order, but whether the*binary* has
been compiled with big-endian flavor by default. Rename it
appropriately to reduce confusion. Mechanical change doing:
$
On 12/2/24 11:41, Julian Ganz wrote:
We recently introduced plugin API for the registration of callbacks for
discontinuity events, specifically for interrupts, exceptions and host
call events. The callback receives, among other information, the VCPU
index and the PC after the event. This change i
On 12/2/24 11:26, Julian Ganz wrote:
We recently introduced new plugin API for registration of discontinuity
related callbacks. This change introduces a minimal plugin showcasing
the new API. It simply counts the occurances of interrupts, exceptions
and host calls per CPU and reports the counts w
On 12/3/24 00:36, Julian Ganz wrote:
Hi,
I just realized that I forgot to run the checkpatch script on the
patches again before sending and did not include the Sign-Off. Sorry
about that.
Regards,
Julian Ganz
No worries, it's pretty frequent that people forgot those.
While at it, you can fi
On Wed, Nov 27, 2024 at 09:16:49PM +0100, Maciej S. Szmigiero wrote:
> On 27.11.2024 10:13, Cédric Le Goater wrote:
> > On 11/17/24 20:20, Maciej S. Szmigiero wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > Some drivers might want to make use of auxiliary helper threads during VM
> > > state
On 12/2/24 11:26, Julian Ganz wrote:
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for Alpha targ
On 12/2/24 11:26, Julian Ganz wrote:
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. In addition, we
recently introduced API for registering callbacks for discontinuity
events, specifically for interrupts, exceptions and h
On 12/2/24 11:26, Julian Ganz wrote:
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. In addition to
those events, we recently defined discontinuity events, which include
traps.
This change introduces a function to registe
On Tue, 3 Dec 2024 21:35:45 +0800
Tomita Moeko wrote:
> igd devices have multipe registers mirroring mmio address and pci
> config space, more than a single BDSM register. To support this,
> the read/write functions are made common and a macro is defined to
> simplify the declaration of MemoryRe
Hi Julian,
thanks for the update!
Comments below.
On 12/2/24 11:26, Julian Ganz wrote:
The plugin API allows registration of callbacks for a variety of VCPU
related events, such as VCPU reset, idle and resume. However, traps of
any kind, i.e. interrupts or exceptions, were previously not covere
On Thu, Nov 28, 2024 at 01:11:53PM +0100, Maciej S. Szmigiero wrote:
> > > +static int qemu_loadvm_load_thread(void *thread_opaque)
> > > +{
> > > + struct LoadThreadData *data = thread_opaque;
> > > + int ret;
> > > +
> > > + ret = data->function(&load_threads_abort, data->opaque);
> > >
Pointer authentication on aarch64 is pretty expensive (up to 50% of
execution time) when running a virtual machine with tcg and -cpu max
(which enables pauth=on).
The advice is always: use pauth-impdef=on.
Our documentation even mentions it "by default" in
docs/system/introduction.rst.
Thus, we c
On 12/3/24 00:45, Julian Ganz wrote:
Hi,
December 2, 2024 at 8:26 PM, "Julian Ganz" wrote:
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
index 0fba36ae02..9c67374b7e 100644
--- a/include/qemu/qemu-plugin.h
+++ b/include/qemu/qemu-plugin.h
@@ -154,6 +154,49 @@ typedef void
On Tue, 3 Dec 2024 21:35:46 +0800
Tomita Moeko wrote:
> The GGC register at 0x50 of pci config space is a mirror of the same
> register at 0x108040 of mmio bar0 [1]. i915 driver also reads that
> register from mmio bar0 instead of config space. As GGC is programmed
> and emulated by qemu, the mm
On Tue, 3 Dec 2024 16:30:56 +
Corvin Köhne wrote:
> On Tue, 2024-12-03 at 21:35 +0800, Tomita Moeko wrote:
> > CAUTION: External Email!!
> > DSM region is likely to store framebuffer in Windows, a small DSM
> > region may cause display issues (e.g. half of the screen is black).
> > By defaul
On Tue, 3 Dec 2024 21:35:42 +0800
Tomita Moeko wrote:
> Add helper functions igd_gtt_memory_size() and igd_stolen_size() for
> calculating GTT stolen memory and Data stolen memory size in bytes,
> and use macros to replace the hardware-related magic numbers for
> better readability.
>
> Signed-
On Tue, 3 Dec 2024 21:35:41 +0800
Tomita Moeko wrote:
> Define the igd device generations according to i915 kernel driver to
> avoid confusion, and adjust comment placement to clearly reflect the
> relationship between ids and devices.
>
> The condition of how GTT stolen memory size is calculat
On Sun, Nov 17, 2024 at 08:20:02PM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> Some of these SaveVMHandlers were missing the BQL behavior annotation,
> making people wonder what it exactly is.
>
> Signed-off-by: Maciej S. Szmigiero
> ---
> include/migration/register.h |
On Sun, Nov 17, 2024 at 08:20:01PM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> qemu_loadvm_load_state_buffer() and its load_state_buffer
> SaveVMHandler allow providing device state buffer to explicitly
> specified device via its idstr and instance id.
>
> Reviewed-by: Fa
On Sun, Nov 17, 2024 at 08:20:00PM +0100, Maciej S. Szmigiero wrote:
> diff --git a/migration/colo.c b/migration/colo.c
> index 9590f281d0f1..a75c2c41b464 100644
> --- a/migration/colo.c
> +++ b/migration/colo.c
> @@ -452,6 +452,9 @@ static int colo_do_checkpoint_transaction(MigrationState
> *s,
>
On Thu, Nov 21, 2024 at 03:48:12PM +, Daniel P. Berrangé wrote:
> On Tue, Nov 19, 2024 at 02:54:29PM -0500, Stefan Hajnoczi wrote:
> > On Fri, Nov 15, 2024 at 07:38:06PM +, Daniel P. Berrangé wrote:
> > > On Fri, Nov 15, 2024 at 02:21:12PM -0500, Stefan Hajnoczi wrote:
> > > > On Fri, 15 No
While the SPARC data endianness can be changed at runtime,
we do not implement that; only big endianness is used.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index dd7af8
On 12/4/24 12:41, Philippe Mathieu-Daudé wrote:
Rather than manually copying each register, use
the libc memcpy(), which is well optimized.
Signed-off-by: Philippe Mathieu-Daudé
---
Worth renaming as reg8cpy()?
---
target/sparc/win_helper.c | 9 +
1 file changed, 1 insertion(+), 8 de
On 12/4/24 12:56, Philippe Mathieu-Daudé wrote:
We are working on adding RME support to SBSA Reference Platform.
When RME is enabled then RMM (Realm Managment Monitor) takes 1072MB of
memory for own use. Which ends with firmware panic on 1GB machine.
Report an error so users directly start with
Before changing default pauth algorithm, we need to make sure current
default one (QARMA5) can still be selected.
$ qemu-system-aarch64 -cpu max,pauth-qarma5=on ...
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/cpu-features.rst | 5 -
target/arm/cpu.h | 1 +
target/a
qemu-system-aarch64 default pointer authentication (QARMA5) is expensive, we
spent up to 50% of the emulation time running it (when using TCG).
Switching to pauth-impdef=on is often given as a solution to speed up execution.
Thus we talked about making it the new default.
The first patch introduc
On Wed, Dec 04, 2024 at 06:01:39PM -0300, Fabiano Rosas wrote:
> > Considering it's confusing to mostly everyone, and tons of people asked me
> > about this.. maybe I should send a patch to remove yank from migration?
>
> Take a look at my suggestion in the other thread, it might make yank
> make
Previously, maintainer role was paused due to inactive email id. Commit id:
c009d715721861984c4987bcc78b7ee183e86d75.
Signed-off-by: Vikram Garhwal
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aaf0505a21..b4723eecde 100644
--- a/MAINTAINER
Peter Xu writes:
> On Wed, Dec 04, 2024 at 08:02:31PM +, Daniel P. Berrangé wrote:
>> On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote:
>> > On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote:
>> > > Peter Xu writes:
>> > >
>> > > > On Mon, Dec 02, 2024 at 07:01:33PM -030
On Tue, Dec 03, 2024 at 10:14:28AM +0100, Christian Schoenebeck wrote:
> 'Twalk' is the most important request type in the 9p protocol to look out
> for when debugging 9p communication. That's because it is the only part
> of the 9p protocol which actually deals with human-readable path names,
> wh
On Wed, Dec 04, 2024 at 05:40:17PM -0300, Fabiano Rosas wrote:
> To be clear, I'm not arguing against cancel. I'm just pointing out that
> it's silly because it's just like pressing C-c in the shell in the
> middle of something. What's the expected end state? Completely
> unspecified. I don't find
Hi all,
this is finally a look at what the PL011 device model would look like
in Rust, without having to write unsafe so often. The attached file is
a synopsis of the C code, the Rust code and my commentary (the C code is
partly rearranged to match the ordering of the Rust code).
The code compi
We are working on adding RME support to SBSA Reference Platform.
When RME is enabled then RMM (Realm Managment Monitor) takes 1072MB of
memory for own use. Which ends with firmware panic on 1GB machine.
Report an error so users directly start with more RAM in this case:
$ qemu-system-aarch64 -M
On Wed, Dec 04, 2024 at 08:02:31PM +, Daniel P. Berrangé wrote:
> On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote:
> > On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote:
> > > Peter Xu writes:
> > >
> > > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote:
>
On 4/12/24 13:17, Leif Lindholm wrote:
On 2024-12-02 10:53, Marcin Juszkiewicz wrote:
W dniu 26.11.2024 o 14:14, Peter Maydell pisze:
On Tue, 26 Nov 2024 at 08:49, Marcin Juszkiewicz
wrote:
We are working on adding RME support to SBSA Reference Platform.
When RME is enabled then RMM (Realm M
Rather than manually copying each register, use
the libc memcpy(), which is well optimized.
Signed-off-by: Philippe Mathieu-Daudé
---
Worth renaming as reg8cpy()?
---
target/sparc/win_helper.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/sparc/win_helper.c b
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/virt.rst | 16
1 file changed, 16 insertions(+)
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 11ceb898264..d25275c27ce 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -169,10 +16
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/xlnx-versal-virt.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs/system/arm/xlnx-versal-virt.rst
index 0bafc76469d..c5f35f28e4f 100644
--- a/docs/system/arm/xlnx-versal-virt.rst
+++ b/docs/
Daniel P. Berrangé writes:
> On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote:
>> On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote:
>> > Peter Xu writes:
>> >
>> > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote:
>> > >> Make sure postcopy threads are releas
Reviewed following things:
- system/arm/cpu-features (options)
- system/arm/virt (options)
- boards documented and listed with -machine help (arm and aarch64)
- grep object_class_property_set_description hw/arm: ensure all options are
documented
- reviewed boards description
- reviewed all Arm fe
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/fby35.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
index bf6da6baa2a..ed9faef363c 100644
--- a/docs/system/arm/fby35.rst
+++ b/docs/system/arm/fby35.rst
@@ -45,3 +45,6 @@ proces
www.orangepi.org does not support https, it's expected to stick to http.
Reviewed-by: Niek Linnenbank
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/orangepi.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.
Rather that using the binary endianness, use the vCPU one.
The target affected by this change are MIPS, MicroBlaze, SH-4
and Xtensa. SPARC, RISC-V and RX could be affected later if
their CPUClass::datapath_is_big_endian() handler is fully
implemented.
Signed-off-by: Philippe Mathieu-Daudé
---
h
For all targets which have endianness architecturally
predefined as big endian (built using TARGET_BIG_ENDIAN=y),
their datapath_is_big_endian() handler simply returns %true.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 ++
target/hppa/cpu.c | 6 ++
target/m68k
On 4/12/24 20:48, Daniel P. Berrangé wrote:
Uploading artifacts in Cirrus CI requires sufficient disk space to
create a tarball of the artifact files. IOW, whatever size the
artifacts are, double that. This results in space pressure on the
FreeBSD jobs due to limited disk size. Purging the .o fil
Rather that using the binary endianness, use the vCPU one.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/generic-loader.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index abdd4c08a38..7b3b5f06565 100644
--- a
Implement MIPS datapath_is_big_endian() handler using
the already existing mips_env_is_bigendian() method.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d0a43b6d5c7..13d0ceaa8af
While on RX the endianness can be set at RESET, we
do not implement that; only little endianness is used.
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 65a74ce720f..391f3214168 100
Rather that using the binary endianness, use the vCPU one.
Signed-off-by: Philippe Mathieu-Daudé
---
disas/disas-common.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/disas/disas-common.c b/disas/disas-common.c
index 7377de0715c..ef91c43449e 100644
--- a/disas/disas-comm
For all targets which have endianness architecturally
predefined as little endian (built using TARGET_BIG_ENDIAN=n),
their datapath_is_big_endian() handler simply returns %false.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 6 ++
target/avr/cpu.c | 7 ++-
targ
On 4/12/24 20:48, Daniel P. Berrangé wrote:
By default ccache checks the compiler 'mtime' to determine if it should
invalidate the cache. On FreeBSD the 'mtime' reflects when the compiler
package was installed, rather than when it was built. IOW, on throwaway
CI VMs, the 'mtime' changes on every
While the RISC-V data endianness can be changed at runtime,
we do not implement that. The current translation code assumes
little-endian memory accesses (See commit a2f827ff4f4 "target/riscv:
accessors to registers upper part and 128-bit load/store").
Signed-off-by: Philippe Mathieu-Daudé
---
ta
Introduce the CPUClass::datapath_is_big_endian() handler,
which returns whether a vCPU expects data in memory to be
in big endian order or not.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/
ppc_cpu_is_big_endian() already returns whether
the data path is in big endian. Re-use that,
exposing this helper for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu_init.c
SH4 CPUs endianness is set with an external pin in a power-on reset.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.h | 6 ++
target/sh4/cpu.c | 8
2 files changed, 14 insertions(+)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index d928bcf0067..2502ddba102 100644
---
There are no more calls to cpu_virtio_is_big_endian().
Remove the method and the SysemuCPUOps::virtio_is_big_endian
helpers altogether.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h| 9 -
include/hw/core/sysemu-cpu-ops.h | 8
hw/core/cpu-sysemu.c
All target implement their CPUClass::datapath_is_big_endian()
helper, we can expose the generic cpu_datapath_is_big_endian()
method.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8
hw/core/cpu-common.c | 7 +++
2 files changed, 15 insertions(+)
diff --git a/in
Implement SH4 datapath_is_big_endian() helper, returning
the 'little_endian' property set at reset.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index f54005644c9..69108c1676e 100644
---
Implement the MicroBlaze datapath_is_big_endian() handler,
returning the value of the ENDI bit.
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.h | 2 ++
target/microblaze/cpu.c | 11 +++
2 files changed, 13 insertions(+)
diff --git a/target/microblaze/cpu.h b/target/mi
Implement Xtensa datapath_is_big_endian() helper via libisa.
Signed-off-by: Philippe Mathieu-Daudé
---
Other accesses to xtensa_isa_internal fields don't
call cpu_synchronize_state(), and the libisa doesn't
provide a way to switch endianness from translation
code. Should we add a sync just in cas
Xtensa internal fields are opaque, only accessible by
the Xtensa libisa. Implement xtensa_isa_is_big_endian()
to get vCPU endianness. This should be implemented in
libisa, not QEMU, but I couldn't figure out where to
contribute this.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/xtensa/xt
The long term goal is to remove endianness knowledge from
QEMU system binaries, allowing them to run vCPU in any
endianness. For that target_words_bigendian(), TARGET_BIG_ENDIAN
and few other things (like MO_TE) must be removed.
Have each target implement a datapath_is_big_endian() handler
to expr
target_words_bigendian() doesn't return whether a target vCPU
expects data in big-endian order, but whether the *binary* has
been compiled with big-endian flavor by default. Rename it
appropriately to reduce confusion. Mechanical change doing:
$ sed -i -e s/target_words_bigendian/qemu_binary_is_
arm_cpu_virtio_is_big_endian() already returns whether
the data path is in big endian. Re-use that.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6938161b954..3061b2ac1
On Sun, Nov 17, 2024 at 08:19:59PM +0100, Maciej S. Szmigiero wrote:
> From: "Maciej S. Szmigiero"
>
> Migration code wants to manage device data sending threads in one place.
>
> QEMU has an existing thread pool implementation, however it is limited
> to queuing AIO operations only and essentia
On 12/4/24 01:38, Alex Bennée wrote:
Pierrick Bouvier writes:
This boot an OP-TEE environment, and launch a nested guest VM inside it
using the Realms feature. We do it for virt and sbsa-ref platforms.
Signed-off-by: Pierrick Bouvier
Queued to testing/next, thanks.
Thanks Alex.
FYI, th
On Wed, Dec 04, 2024 at 02:39:12PM -0500, Peter Xu wrote:
> On Wed, Dec 04, 2024 at 04:02:36PM -0300, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> > > On Mon, Dec 02, 2024 at 07:01:33PM -0300, Fabiano Rosas wrote:
> > >> Make sure postcopy threads are released when migrate_cancel is
> > >> iss
On 11/5/2024 10:27 AM, Taylor Simpson wrote:
All Hexagon debugging is now done with QEMU mechanisms
(e.g., -d in_asm) or with a connected debugger (lldb).
Signed-off-by: Taylor Simpson
Reviewed-by: Matheus Tavares Bernardino
---
I was wondering why I didn't see an update on this patch. So
Found with test sbsaref introduced in [1].
[1]
https://patchew.org/QEMU/20241203213629.2482806-1-pierrick.bouv...@linaro.org/
../block/vvfat.c:433:24: runtime error: index 14 out of bounds for type
'uint8_t [11]'
#0 0x56151a66b93a in create_long_filename ../block/vvfat.c:433
#1 0x56151a
Uploading artifacts in Cirrus CI requires sufficient disk space to
create a tarball of the artifact files. IOW, whatever size the
artifacts are, double that. This results in space pressure on the
FreeBSD jobs due to limited disk size. Purging the .o files from
the meson build directory reclaims sig
Rather than a giant sed command with a hardcoded list of env var name,
we can now use the new(ish) cirrus-vars command that libvirt has added
to the 'cirrus-run' container.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/cirrus.yml | 23 +++
.gitlab-ci.d/cirrus/build
By default ccache checks the compiler 'mtime' to determine if it should
invalidate the cache. On FreeBSD the 'mtime' reflects when the compiler
package was installed, rather than when it was built. IOW, on throwaway
CI VMs, the 'mtime' changes on every single job and is thus useless.
It could vali
Add rules to configure the use of ccache with Cirrus CI jobs,
and preserve the cache across jobs.
The HomeBrew PATH was already present, but incorrect, while
the FreeBSD PATH was missing.
About 1 GB is enough to get a 99% hit rate on a pristine rebuild
with no code changes. Setting it much higher
The FreeBSD VM is somewhat low on disk space after all QEMU build deps
are installed and a full QEMU build performed. Purging the package
manager cache is a simple thing that reclaims about 1 GB of space.
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/cirrus.yml | 2 ++
.gitlab-ci.d/ci
This update pulls in ccache4 for FreeBSD, to match other platforms
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/cirrus/freebsd-14.vars | 2 +-
tests/lcitool/libvirt-ci| 2 +-
tests/vm/generated/freebsd.json | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --gi
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