Re: [PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()

On Thu, Nov 28, 2024 at 7:39 PM Peter Maydell wrote: > > In riscv_cpu_do_interrupt() we use the 'cause' value we got out of > cs->exception as a shift value. However this value can be larger > than 31, which means that "1 << cause" is undefined behaviour, > because we do the shift on an 'int' typ

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

Hi Zhao， Thank you for your message. I appreciate your willingness to help push this fix. On 12/3/24 下午3:36, Zhao Liu wrote: Hi Chuang, Could I pick this fix in my later series (with another overflow fix)? I can help you push this fix forward :-). Regards, Zhao On Wed, Oct 09, 2024 at 11:5

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

Hi Chuang, Could I pick this fix in my later series (with another overflow fix)? I can help you push this fix forward :-). Regards, Zhao On Wed, Oct 09, 2024 at 11:56:38AM +0800, Chuang Xu wrote: > Date: Wed, 9 Oct 2024 11:56:38 +0800 > From: Chuang Xu > Subject: [PATCH v6] i386/cpu: fixup num

Re: [PATCH v6] i386/cpu: fixup number of addressable IDs for logical processors in the physical package

> However, back to the patch, I think we cannot change it as this patch > directly. Instead, we need a compat_props for the changed behavior, because > this isn't a bug fix and it introduces guest-visible differences. This is a fix, not a new feature, so compat_props is not needed. > For ancient

Re: [PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()

On 12/2/24 07:46, Peter Maydell wrote: On Thu, 28 Nov 2024 at 12:59, Richard Henderson wrote: On 11/28/24 04:38, Peter Maydell wrote: In riscv_cpu_do_interrupt() we use the 'cause' value we got out of cs->exception as a shift value. However this value can be larger than 31, which means that

Re: [PATCH 3/8] vfio/igd: remove unsupported device ids

On Sun, 2024-12-01 at 22:30 -0700, Alex Williamson wrote: > CAUTION: External Email!! > On Mon,  2 Dec 2024 00:09:33 +0800 > Tomita Moeko wrote: > > > Since e433f208973f ("vfio/igd: return an invalid generation for > > unknown > > devices"), the default return of igd_gen() was changed to > > unsu

Re: [PATCH v4 0/3] Support 64-bit address of initrd

On Thu, Nov 21, 2024 at 12:40 AM Jim Shu wrote: > > Support to load DTB after 3GB on RV64 system, so that larger initrd > doesn't be overlapped to DTB. DTB loading now will check if overlapping > to kernel/initrd and report this error. > > Verify the patch via running 4GB initramfs on the virt mac

Re: [PATCH] hw/ide/ahci: Check for PCI device once in ahci_init()

Am 21. November 2024 10:01:52 UTC schrieb "Philippe Mathieu-Daudé" : >object_dynamic_cast() is expensive; IRQ helpers are certainly >a bad place to call it. Since the device type won't change at >runtime, resolve it once when the AHCI context is initialized >in ahci_init(). > >Reported-by: Pete

Re: [PATCH 5/7] [BCM2835 AUX 5/7] Suffix constants

On Sun, 17 Nov 2024 at 23:02, Ioan-Cristian CÎRSTEA wrote: > > The constants defined through the preprocessor must be unsigned. Also, > unsigned integer constants are consistent across different bases (see > section 6.4.4.1 of the C99 standard draft). > > Signed-off-by: Ioan-Cristian CÎRSTEA > --

[PATCH v2 for-10.0 23/54] target/xtensa: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 2 files changed, 2 insertions(+), 8 deletions(-) diff

Re: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format

On Mon, Oct 28, 2024 at 10:59 AM Sia Jee Heng wrote: > > Update the SPCR table to accommodate the SPCR Table revision 4 [1]. > The SPCR table has been modified to adhere to the revision 4 format [2]. > > Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to > accommodate t

Re: [PATCH v4 3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd

On Thu, Nov 21, 2024 at 12:42 AM Jim Shu wrote: > > DTB is placed to the end of memory, so we will check if the start > address of DTB overlaps to the address of kernel/initrd. > > Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 25

Re: [PATCH v4 2/3] hw/riscv: Add a new struct RISCVBootInfo

On Thu, Nov 21, 2024 at 12:41 AM Jim Shu wrote: > > Add a new struct RISCVBootInfo to sync boot information between multiple > boot functions. > > Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c| 65 ++ > h

Re: [PULL 0/3] Functional test fixes for v9.2.0-rc3

On 02/12/2024 18.56, Peter Maydell wrote: On Mon, 2 Dec 2024 at 13:56, Thomas Huth wrote: Hi Peter! The following changes since commit 72b88908d12ee9347d13539c7dd9a252625158d1: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-11-29 10:09:05 +) are ava

Re: [PATCH v4 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

On Thu, Nov 21, 2024 at 12:41 AM Jim Shu wrote: > > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit > system doesn't have 32-bit addressable issue, we just load DTB to the end > of dram in 64-bit system. > > Signed-off-by: Jim Shu Reviewed-by: Alistair Francis Alistair >

Re: [PATCH-for-10.0 0/3] hw/char/riscv_htif: Remove tswap64() calls

On Sat, Nov 30, 2024 at 12:44 AM Philippe Mathieu-Daudé wrote: > > Trying to make sense of these tswap64 calls I > figured this device could be simplified. > > Tested using 'make check-{qtest,functional}' > on both big/little endian hosts, no failure but > I'm not sure the code path is covered. >

[PULL 4/4] hw/nvme: take a reference on the subsystem on vf realization

From: Klaus Jensen Make sure we grab a reference on the subsystem when a VF is realized. Otherwise, the subsytem will be unrealized automatically when the VFs are unregistered and unreffed. This fixes a latent bug but was not exposed until commit 08f632848008 ("pcie: Release references of virtua

[PULL 2/4] hw/nvme: fix use/unuse of msix vectors

From: Klaus Jensen Only call msix_{un,}use_vector() when interrupts are actually enabled for a completion queue. Reviewed-by: Jesper Wendel Devantier Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvm

[PULL 1/4] hw/nvme: fix msix_uninit with exclusive bar

From: Klaus Jensen Commit fa905f65c554 introduced a machine compatibility parameter to enable an exclusive bar for msix. It failed to account for this when cleaning up. Make sure that if an exclusive bar is enabled, we use the proper cleanup routine. Cc: qemu-sta...@nongnu.org Fixes: fa905f65c55

[PULL 3/4] hw/nvme: SR-IOV VFs must hardwire pci interrupt pin register to zero

From: Klaus Jensen The PCI Interrupt Pin Register does not apply to VFs and MUST be hardwired to zero. Fixes: 44c2c09488db ("hw/nvme: Add support for SR-IOV") Reviewed-by: Jesper Wendel Devantier Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 8 +++- 1 file changed, 7 insertions(+), 1 d

[PULL 0/4] nvme queue

From: Klaus Jensen Hi, The following changes since commit eb22a064455aeebc105cc89bf77f48aa18b52938: Merge tag 'pull-request-2024-12-02' of https://gitlab.com/thuth/qemu into staging (2024-12-02 16:16:15 +) are available in the Git repository at: https://gitlab.com/birkelund/qemu.git

Re: [PATCH-for-9.2? 0/2] tests/functional: Fix tests failing when TCG is not available on macOS

On 02/12/2024 22.01, Philippe Mathieu-Daudé wrote: On 2/12/24 21:56, Thomas Huth wrote: On 02/12/2024 21.40, Philippe Mathieu-Daudé wrote: Explicit the QTest accelerator to have these 2 tests pass on macOS when only HVF is built in. Could we maybe rather add something like this at the top of

[PATCH] hw/pci-host/pnv_phb4: Fix LSI irq source calculation overrun

PHB5 has big and small PHBs, that have 4k and 2k interrupt sources respective. The LSI interrupt sources are set with a 9-bit register field, that selects the aligned block of 8 irqs, giving a 4k range. This is initialized by hardware to 0x1ff in order to select the last 8 irq sources. The small P

Re: [PATCH-for-10.0 3/3] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses

On Sat, Nov 30, 2024 at 12:45 AM Philippe Mathieu-Daudé wrote: > > Looking at htif_mm_ops[] read/write handlers, we notice they > expect 32-bit values to accumulate into to the 'fromhost' and > 'tohost' 64-bit variables. Explicit by setting the .impl > min/max fields. > > Signed-off-by: Philippe M

Re: [PATCH-for-10.0 2/3] hw/char/riscv_htif: Explicit little-endian implementation

On Sat, Nov 30, 2024 at 12:43 AM Philippe Mathieu-Daudé wrote: > > Since our RISC-V system emulation is only built for little > endian, the HTIF device aims to interface with little endian > memory accesses, thus we can explicit htif_mm_ops:endianness > being DEVICE_LITTLE_ENDIAN. > > In that case

Re: [PATCH v1 3/4] migration: refactor ram_save_target_page functions

Hello Fabiano, On Mon, 2 Dec 2024 at 19:42, Fabiano Rosas wrote: > > ...multifd_send/_recv_sync_main();<= do the 'flush' and > > 'sync' mean the same thing here? > > No, that patch is indeed inconsistent in the terminology, good point. > Well, flush and sync are not reserved terms, we can u

Re: [PATCH 11/22] tests/functional: switch over to using self.data_file(...)

On Mon, Dec 2, 2024 at 3:02 PM Thomas Huth wrote: > > On 29/11/2024 18.31, Daniel P. Berrangé wrote: > > This removes direct path manipulation to figure out the source dir > > > > Signed-off-by: Daniel P. Berrangé > > --- > > tests/functional/test_acpi_bits.py | 22 +++--- > >

Re: [PATCH RFC-for-10.0] hw/usb/hcd-xhci-pci: Use event ring 0 if interrupter mapping unsupported

On 2024/12/02 18:49, Phil Dennis-Jordan wrote: On Mon, 2 Dec 2024 at 06:39, Akihiko Odaki > wrote: On 2024/12/02 1:03, Phil Dennis-Jordan wrote: > This change addresses an edge case that trips up macOS guest drivers > for PCI based XHCI controlle

Re: [PATCH-for-10.0 1/3] MAINTAINERS: Cover RISC-V HTIF interface

On Sat, Nov 30, 2024 at 12:44 AM Philippe Mathieu-Daudé wrote: > > The HTIF interface is RISC-V specific, add > it within the MAINTAINERS section covering > hw/riscv/. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > IMHO 'RISC-V TCG CPUs' should cover

Re: [PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()

On Thu, Nov 28, 2024 at 7:39 PM Peter Maydell wrote: > > In riscv_cpu_do_interrupt() we use the 'cause' value we got out of > cs->exception as a shift value. However this value can be larger > than 31, which means that "1 << cause" is undefined behaviour, > because we do the shift on an 'int' typ

Re: [RFC PATCH v3 09/11] target/riscv: call plugin trap callbacks

On Tue, Dec 3, 2024 at 4:30 AM Julian Ganz wrote: > > We recently introduced API for registering callbacks for trap related > events as well as the corresponding hook functions. Due to differences > between architectures, the latter need to be called from target specific > code. > > This change pl

[PATCH v2 for-10.0 00/54] fpu: Remove pickNaNMulAdd, default-NaN ifdefs

(Apologies for this patchset being both big and having a wide CC list; the good news is that this is the last lot of fpu ifdef cleanup that needs to touch all the targets.) This patchset does the same thing we already did for pickNaN() to pickNaNMulAdd() -- it replaces the compile-time ifdef ladde

Re: [PATCH v2 for-10.0 00/54] fpu: Remove pickNaNMulAdd, default-NaN ifdefs

On 12/2/24 07:12, Peter Maydell wrote: (Apologies for this patchset being both big and having a wide CC list; the good news is that this is the last lot of fpu ifdef cleanup that needs to touch all the targets.) This patchset does the same thing we already did for pickNaN() to pickNaNMulAdd() --

Re: [External] Re: [PATCH v7 09/12] migration/multifd: Enable DSA offloading in multifd sender path.

On Tue, Nov 26, 2024 at 5:23 AM Fabiano Rosas wrote: > > Yichen Wang writes: > > > On Thu, Nov 21, 2024 at 12:52 PM Fabiano Rosas wrote: > >> > >> Yichen Wang writes: > >> > >> > From: Hao Xiang > >> > > >> > Multifd sender path gets an array of pages queued by the migration > >> > thread. It

[PATCH v5 1/6] target/riscv: Add svukte extension capability variable

Refer to the draft of svukte extension from: https://github.com/riscv/riscv-isa-manual/pull/1564 Svukte provides a means to make user-mode accesses to supervisor memory raise page faults in constant time, mitigating attacks that attempt to discover the supervisor software's address-space layout.

[PATCH v5 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Revie

[PATCH v5 5/6] target/riscv: Expose svukte ISA extension

Add "svukte" in the ISA string when svukte extension is enabled. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8447a

[PATCH v5 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled

Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be supported when the svukte extension is enabled. When senvcfg[UKTE] bit is set, the memory access from U-mode should do the svukte check only except HLV/HLVX/HSV H-mode instructions which depend on hstatus[HUKTE]. Signed-off-by:

[PATCH v5 4/6] target/riscv: Check memory access to meet svukte rule

Follow the Svukte spec, do the memory access address checking 1. Include instruction fetches or explicit memory accesses 2. System run in effective privilege U or VU 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if instruction is HLV, HLVX, HSV and execute from U mode to VU mode 4.

[PATCH v5 6/6] target/riscv: Check svukte is not enabled in RV32

The spec explicitly says svukte doesn't support RV32. So check that it is not enabled in RV32. Signed-off-by: Fea.Wang --- target/riscv/tcg/tcg-cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..3b99c8c9e3 1006

[PATCH v5 0/6] Introduce svukte ISA extension

The Svukte ISA extension has been approved for fast-track development. https://lf-riscv.atlassian.net/browse/RVS-2977 And there are Linux patches for the Svukte that are under review. https://lore.kernel.org/kvm/20240920-dev-maxh-svukte-rebase-v1-0-7864a88a6...@sifive.com/T/#mf70fcb22cd2987ad268c0

Re: [PATCH v2 for-10.0 11/54] target/x86: Set FloatInfZeroNaNRule explicitly

On 12/2/24 07:13, Peter Maydell wrote: Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: Update the comment to give the info from the x86 spec rather than a TODO comment saying we need to check it... --- target/

[PATCH v2 for-10.0 35/54] tests/fp: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for the tests/fp code. Signed-off-by: Peter Maydell --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 39d80c9038f..

Re: [PATCH v2 for-10.0 32/54] target/sparc: Initialize local scratch float_status from env->fp_status

On 12/2/24 07:13, Peter Maydell wrote: In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env-

[PULL 3/3] tests/functional: increase timeouts for arm sx1 test

From: Daniel P. Berrangé When under high load the test VM does not complete running in the default 30 second timeout. Double it to give more headroom. Signed-off-by: Daniel P. Berrangé Message-ID: <20241129173120.761728-2-berra...@redhat.com> Reviewed-by: Thomas Huth Signed-off-by: Thomas Huth

Re: [PULL 0/2] chardev patches

On Mon, 2 Dec 2024 at 12:27, wrote: > > From: Marc-André Lureau > > The following changes since commit 72b88908d12ee9347d13539c7dd9a252625158d1: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging > (2024-11-29 10:09:05 +) > > are available in the Git repository at

Re: [PATCH v2 2/3] scripts: validate SPDX license choices

On Mon, Dec 02, 2024 at 04:41:48PM +, Peter Maydell wrote: > On Tue, 19 Nov 2024 at 11:29, Daniel P. Berrangé wrote: > > > > We expect all new code to be contributed with the "GPL-2.0-or-later" > > license tag. Divergance is permitted if the new file is derived from > > "divergence" > > > pr

[PATCH] hw/mem: support zero memory size CXL device

According to CXL 3.1 specification, 8.1.3.8 DVSEC CXL Range Registers "A CXL.mem-capable device is permitted to report zero memory size." This patch will allow a CXL type3 device to be initialized with zero memory size, when there is no memory device property provided ( neither volatile, persist

[PATCH v2 5/6] aspeed/soc: Support SDHCI for AST2700

Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1 slot and registers base address is start at 0x1408_ and its interrupt is connected to GICINT133_INTC at bit 1. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 20 1 file changed, 20 ins

[PATCH v2 3/6] hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers.

Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support for AST2700. Introduce a new "capareg"

[PATCH v2 1/6] hw/sd/aspeed_sdhci: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/sd/aspeed_sdhci.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index 98d5460905..acd6538261 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sd

[PATCH v2 0/6] Support SDHCI and eMMC for ast2700

change from v1: This patch series do not support boot from an eMMC. Only support eMMC and SD Slot 0 as storages. change from v2: - Add hw/sd/aspeed_sdhci: Fix coding style patch Jamin Lin (6): hw/sd/aspeed_sdhci: Fix coding style hw/arm/aspeed: Fix coding style hw:sdhci: Introduce a new "ca

[PATCH v2 4/6] hw/sd/aspeed_sdhci: Add AST2700 Support

Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class init function and set the value of capability register to "0x000719f80080". Signed-off-by: Jamin Lin --- hw/sd/aspeed_sdhci.c | 16 include/hw/sd/aspeed_sdhci.h | 1 + 2 files changed, 1

[PATCH v2 6/6] aspeed/soc: Support eMMC for AST2700

Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1 slot and registers base address is start at 0x1209_ and its interrupt is connected to GICINT 15. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 15 +++ 1 file changed, 15 insertions(+) diff --gi

[PATCH v2 2/6] hw/arm/aspeed: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast2600.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index be3eb70cdd..c40d3d8443 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/

RE: [PATCH v1 0/5] Support SDHCI and eMMC for ast2700

Hi all > Subject: [PATCH v1 0/5] Support SDHCI and eMMC for ast2700 > > change from v1: > This patch series do not support boot from an eMMC. > Only support eMMC and SD Slot 0 as storages. > > Jamin Lin (5): > hw/arm/aspeed: Fix coding style > hw:sdhci: Introduce a new "capareg" class member

Re: [PATCH v2 for-10.0 28/54] softfloat: Create floatx80 default NaN from parts64_default_nan

On 12/2/24 07:13, Peter Maydell wrote: We create our 128-bit default NaN by calling parts64_default_nan() and then adjusting the result. We can do the same trick for creating the floatx80 default NaN, which lets us drop a target ifdef. floatx80 is used only by: i386 m68k arm nwfpe old flo

Re: [PATCH 8/8] vfio/igd: add x-igd-gms option back to set DSM region size for guest

On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > DSM region is likely to store framebuffer in Windows, a small DSM > region may cause display issues (e.g. half of the screen is black). > By default, QEMU uses host's original value, which is determined by > DVMT

[PATCH v1 4/5] aspeed/soc: Support SDHCI for AST2700

Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1 slot and registers base address is start at 0x1408_ and its interrupt is connected to GICINT133_INTC at bit 1. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 20 1 file changed, 20 ins

[PATCH v1 3/5] hw/sd/aspeed_sdhci: Add AST2700 Support

Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class init function and set the value of capability register to "0x000719f80080". Signed-off-by: Jamin Lin --- hw/sd/aspeed_sdhci.c | 16 include/hw/sd/aspeed_sdhci.h | 1 + 2 files changed, 1

[PATCH v1 1/5] hw/arm/aspeed: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast2600.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index be3eb70cdd..c40d3d8443 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/

[PATCH v1 2/5] hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers.

Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support for AST2700. Introduce a new "capareg"

[PATCH v1 5/5] aspeed/soc: Support eMMC for AST2700

Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1 slot and registers base address is start at 0x1209_ and its interrupt is connected to GICINT 15. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 15 +++ 1 file changed, 15 insertions(+) diff --gi

[PATCH v1 0/5] Support SDHCI and eMMC for ast2700

change from v1: This patch series do not support boot from an eMMC. Only support eMMC and SD Slot 0 as storages. Jamin Lin (5): hw/arm/aspeed: Fix coding style hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers. hw/sd/aspeed_sdhci: Add AST2700 Supp

Re: [PATCH-for-9.2? v2 1/2] hw/display/vga: Do not reset 'big_endian_fb' in vga_common_reset()

It's been a long time, I only have vague memories of this :-) But I think it should be ok. It does definitely make sense in the virtio case and similar where the property is set once for the instance. For bochs and ati, there's a register to configure it as well, so there *may* be an expectation

Re: [PATCH v2 1/2] rust: add BQL-enforcing Cell variant

Paolo Bonzini writes: > QEMU objects usually have their pointer shared with the "outside > world" very early in their lifetime, for example when they create their > MemoryRegions. Because at this point it is not valid anymore to > create a &mut reference to the device, individual parts of the

Re: [PATCH 10/67] target/arm: Convert XPAC[ID] to decodetree

On 1/12/24 16:05, Richard Henderson wrote: Remove disas_data_proc_1src, as these were the last insns decoded by that function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 99 +- target/arm/tcg/a64.decode | 3 ++ 2 files changed

Re: [PATCH v2 for-10.0 45/54] target/ppc: Set default NaN pattern explicitly

On 12/2/24 07:13, Peter Maydell wrote: Set the default NaN pattern explicitly for ppc. Signed-off-by: Peter Maydell --- target/ppc/cpu_init.c | 4 1 file changed, 4 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index eb9d7b13701..1253dbf622c 100644 --- a/targ

[PATCH v3] tests/functional/aarch64: add tests for FEAT_RME

This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier - v2: - move test to its own file - add sbsa test - check output of `cca-workload-attestation report` v3: - build and

Re: [PATCH v3 0/7] hugetlbfs memory HW error fixes

On 12/2/24 17:00, David Hildenbrand wrote: On 02.12.24 16:41, William Roche wrote: Hello David, Hi, sorry for reviewing yet, I was rather sick the last 1.5 weeks. I hope you get well soon! I've finally tested many page mapping possibilities and tried to identify the error injection reacti

Re: [PATCH v3 08/11] target/riscv: Add counter delegation/configuration support

On Mon, Dec 2, 2024 at 1:49 PM Daniel Henrique Barboza wrote: > > > > On 12/2/24 6:15 PM, Atish Kumar Patra wrote: > > On Thu, Nov 28, 2024 at 4:53 AM Daniel Henrique Barboza > > wrote: > >> > >> > >> > >> On 11/17/24 10:15 PM, Atish Patra wrote: > >>> From: Kaiwen Xue > >>> > >>> The Smcdeleg/S

Re: [PATCH 1/8] vfio/igd: fix GTT stolen memory size calculation for gen 7

On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > Both intel documentation [1][2] and i915 driver shows GGMS represents > GTT stolen memory size in multiple of 1MB, not 2MB starting from gen > 8. > > [1] > https://www.intel.com/content/dam/www/public/us/en/docum

[PATCH V4 02/19] physmem: fd-based shared memory

Create MAP_SHARED RAMBlocks by mmap'ing a file descriptor rather than using MAP_ANON, so the memory can be accessed in another process by passing and mmap'ing the fd. This will allow CPR to support memory-backend-ram and memory-backend-shm objects, provided the user creates them with share=on. Us

Re: [PATCH v3 2/5] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations

On Sat, 2 Nov 2024 at 12:57, Bernhard Beschow wrote: > > imx_fec models the same PHY as lan9118_phy. The code is almost the same with > imx_fec having more logging and tracing. Merge these improvements into > lan9118_phy and reuse in imx_fec to fix the code duplication. > > Some migration state ho

Re: [PATCH 3/7] [BCM2835 AUX 3/7] Asynchronous transmit

On Sun, 17 Nov 2024 at 23:01, Ioan-Cristian CÎRSTEA wrote: > > This commit changes data transmission: instead of using the blocking > function `qemu_chr_fe_write_all()`, the transmit logic using the > asynchronous counterpart `qemu_chr_fe_write()`. This is a nice cleanup -- it's nice to reduce th

Re: [RFC PATCH 0/5] support unaligned access to xHCI Capability

On Fri, 29 Nov 2024 at 03:33, Tomoyuki HIROSE wrote: > OK, thanks! I got understand. I thought MemoryRegionOps had to be > 'static const' . > I will try to improve code so that it does not require the use of > memaccess-testdev.h.inc . Great. The other thing I thought of this weekend is that we s

Re: [PATCH v3 22/24] vfio/migration: Multifd device state transfer support - receive side

Hello Maciej, On 11/17/24 20:20, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" The multifd received data needs to be reassembled since device state packets sent via different multifd channels can arrive out-of-order. Therefore, each VFIO device state packet carries a header indicatin

Re: [PATCH v2 0/3 for 9.2] hw/virtio: fix crash in virtio-balloon and test it

Hi, On 2/12/24 18:05, David Hildenbrand wrote: On 29.11.24 14:55, Daniel P. Berrangé wrote: See patch 1 for the background info on the problem Changed in v2:   * Add qtest coverage for the crash scenario Daniel P. Berrangé (3):    hw/virtio: fix crash in processing balloon stats    tests/qte

Re: [PATCH 04/67] target/arm: Convert CRC32, CRC32C to decodetree

On 12/2/24 08:01, Philippe Mathieu-Daudé wrote: -    if (!dc_isar_feature(aa64_crc32, s) -    || (sf == 1 && sz != 3) -    || (sf == 0 && sz == 3)) { We are not checking the sf bit anymore, is that intended? Yes. +CRC32   0 00 11010110 . 0100 00 . . @rrr_b +CRC32

Re: [PATCH 03/14] ppc/xive2: Support group-matching when looking for target

On 11/21/2024 4:56 PM, Mike Kowal wrote: On 11/18/2024 9:22 PM, Nicholas Piggin wrote: On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote: From: Frederic Barrat If an END has the 'i' bit set (ignore), then it targets a group of VPs. The size of the group depends on the VP index of the

Re: [PATCH 4/7] [BCM2835 AUX 4/7] STAT & IIR registers

On Sun, 17 Nov 2024 at 23:02, Ioan-Cristian CÎRSTEA wrote: > > This commits implements the required logic for STAT & IIR registers. The > STAT register is an extension of the UART 16550 that provides useful > (more helpful than the base state register) insights of the peripheral > state. The STAT

[PATCH 3/6] migration: Fix postcopy listen thread exit

There are a couple of problems with exiting the postcopy listen thread. It does not honor the exit-on-error flag and always exits QEMU upon error. It also does not behave well if a qmp_migrate_cancel() is issued while postcopy is paused, it either hangs during retry or crashes during access of a no

[PATCH 1/6] tests/qtest/migration: Introduce migration_test_add_suffix

Introduce a new migration_test_add_suffix to allow programmatic creation of tests based on a suffix. Pass the test name into the test so it can know which variant to run. Signed-off-by: Fabiano Rosas --- tests/qtest/migration-helpers.c | 24 tests/qtest/migration-helpers

[PATCH 6/6] tests/qtest/migration: Add a cancel test

The qmp_migrate_cancel() command is poorly tested and code inspection reveals that there might be concurrency issues with its usage. Add a test that runs a migration and calls qmp_migrate_cancel() at specific moments. In order to make the test more deterministic, instead of calling qmp_migrate_can

[PATCH 2/6] migration: Kick postcopy threads on cancel

Make sure postcopy threads are released when migrate_cancel is issued. Kick the postcopy_pause semaphore and have the fault thread read 'fault_thread_quit' when joining. While here fix the comment mentioning userfault_event_fd. Signed-off-by: Fabiano Rosas --- migration/migration.c| 14

[PATCH 5/6] migration: Fix hang after error in destination setup phase

If the destination side fails at migration_ioc_process_incoming() before starting the coroutine, it will report the error but QEMU will not exit. Set the migration state to FAILED and exit the process if exit-on-error allows. CC: Thomas Huth Resolves: https://gitlab.com/qemu-project/qemu/-/issue

[PATCH 4/6] migration: Make sure postcopy recovery doesn't hang when cancelling

Make sure postcopy recovery doesn't hang when calling qmp_migrate_cancel() and also doesn't pause the migration once more. Signed-off-by: Fabiano Rosas --- migration/migration.c | 13 + 1 file changed, 13 insertions(+) diff --git a/migration/migration.c b/migration/migration.c index

[PATCH 0/6] migration: Fix issues during qmp_migrate_cancel

Hi, While working on downstream issues with postcopy, I ended up writing a set of tests for issuing qmp_migrate_cancel() at various points during the migration. That exposed some bugs, which this series attempts to fix. There is also a fix for the issue Daniel found: https://gitlab.com/qemu-proj

Re: [PATCH 2/8] vfio/igd: canonicalize memory size calculations

On 12/2/24 17:10, Corvin Köhne wrote: > On Sun, 2024-12-01 at 22:28 -0700, Alex Williamson wrote: >> CAUTION: External Email!! >> On Mon,  2 Dec 2024 00:09:32 +0800 >> Tomita Moeko wrote: >> >>> Add helper functions igd_gtt_memory_size() and igd_stolen_size() for >>> calculating GTT stolen memo

Re: [PATCH v3 08/11] target/riscv: Add counter delegation/configuration support

On 12/2/24 6:15 PM, Atish Kumar Patra wrote: On Thu, Nov 28, 2024 at 4:53 AM Daniel Henrique Barboza wrote: On 11/17/24 10:15 PM, Atish Patra wrote: From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scou

[PATCH v2 for-10.0 34/54] fpu: Allow runtime choice of default NaN value

Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit i

[PATCH v2 for-10.0 44/54] target/openrisc: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for openrisc. Signed-off-by: Peter Maydell --- target/openrisc/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..3ccf85e95f0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/

[PATCH v2 for-10.0 21/54] target/sparc: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a

[PULL 0/1] Migration 20241202 patches

The following changes since commit eb22a064455aeebc105cc89bf77f48aa18b52938: Merge tag 'pull-request-2024-12-02' of https://gitlab.com/thuth/qemu into staging (2024-12-02 16:16:15 +) are available in the Git repository at: https://gitlab.com/peterx/qemu.git tags/migration-202

[PULL 1/1] migration: correct multifd receive thread name

From: Prasad Pandit Multifd receive threads run on the destination side. Correct the thread name marco to indicate the same. Fixes: e620b1e4770b ("migration: Put thread names together with macros") Signed-off-by: Prasad Pandit Reviewed-by: Fabiano Rosas Link: https://lore.kernel.org/r/20241127

Re: [RFC PATCH 2/5] system/memory: support unaligned access

On Fri, Nov 08, 2024 at 12:29:46PM +0900, Tomoyuki HIROSE wrote: > The previous code ignored 'impl.unaligned' and handled unaligned > accesses as is. But this implementation could not emulate specific > registers of some devices that allow unaligned access such as xHCI > Host Controller Capability

Re: [PATCH 47/67] target/arm: Introduce clear_vec

On 1/12/24 16:05, Richard Henderson wrote: In a couple of places, clearing the entire vector before storing one element is the easiest solution. Wrap that into a helper function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 21 - 1 file changed,

Re: [PATCH v2 for-10.0 33/54] target/ppc: Use env->fp_status in helper_compute_fprf functions

On 12/2/24 07:13, Peter Maydell wrote: In the helper_compute_fprf functions, we pass a dummy float_status in to the is_signaling_nan() function. This is unnecessary, because we have convenient access to the CPU env pointer here and that is already set up with the correct values for the snan_bit_i

Re: [PATCH v2 for-10.0 14/54] softfloat: Pass have_snan to pickNaNMulAdd

On 12/2/24 07:13, Peter Maydell wrote: The new implementation of pickNaNMulAdd() will find it convenient to know whether at least one of the three arguments to the muladd was a signaling NaN. We already calculate that in the caller, so pass it in as a new bool have_snan. Signed-off-by: Peter May

[PATCH v2 for-10.0 50/54] target/xtensa: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for xtensa. Signed-off-by: Peter Maydell --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3163b758235..0d4d79b58b4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -13

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