Hello, Daniel
On 26.11.2024 21:32, Daniel P. Berrangé wrote:
On Wed, Nov 13, 2024 at 12:43:40PM +0300, Dmitry Frolov wrote:
Some tests need more time when qemu is built with
"--enable-asan --enable-ubsan"
As was discussed here:
https://patchew.org/QEMU/20241112120100.176492-2-frolov@swemel.r/u
On 2024/11/13 23:23, Phil Dennis-Jordan wrote:
MacOS provides a framework (library) that allows any vmm to implement a
paravirtualized 3d graphics passthrough to the host metal stack called
ParavirtualizedGraphics.Framework (PVG). The library abstracts away
almost every aspect of the paravirtuali
Hello, Daniel.
On 26.11.2024 21:32, Daniel P. Berrangé wrote:
On Wed, Nov 13, 2024 at 12:43:40PM +0300, Dmitry Frolov wrote:
Some tests need more time when qemu is built with
"--enable-asan --enable-ubsan"
As was discussed here:
https://patchew.org/QEMU/20241112120100.176492-2-frolov@swemel.r/
Paolo Bonzini writes:
> QEMU objects usually have their pointer shared with the "outside
> world" very early in their lifetime, for example when they create their
> MemoryRegions. Because at this point it is not valid anymore to
> create a &mut reference to the device, individual parts of the
hvf on Arm is supported since commit a1477da3ddeb ("hvf: Add Apple
Silicon support").
Signed-off-by: Akihiko Odaki
---
docs/about/build-platforms.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst
index 6102f00a
On 2024/11/13 23:23, Phil Dennis-Jordan wrote:
This change wires up the PCI variant of the paravirtualised
graphics device, mainly useful for x86-64 macOS guests, implemented
by macOS's ParavirtualizedGraphics.framework. It builds on code
shared with the vmapple/mmio variant of the PVG device.
S
On 2024/11/21 23:35, Phil Dennis-Jordan wrote:
As we're talking about macOS-only code I'd perhaps have used '#pragma
clang diagnostic' rather than the GCC versions, but clang seems to
understand these just fine too. (Plus, we very much intend for these to
be genuinely temporary.)
Reviewed-by:
On 2024/11/13 23:23, Phil Dennis-Jordan wrote:
MacOS provides a framework (library) that allows any vmm to implement a
paravirtualized 3d graphics passthrough to the host metal stack called
ParavirtualizedGraphics.Framework (PVG). The library abstracts away
almost every aspect of the paravirtuali
On 2024/11/13 23:23, Phil Dennis-Jordan wrote:
From: Alexander Graf
Apple defines a new "vmapple" machine type as part of its proprietary
macOS Virtualization.Framework vmm. This machine type is similar to the
virt one, but with subtle differences in base devices, a few special
vmapple device a
On 26/11/2024 22.17, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/devel/style.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/devel/style.rst b/docs/devel/style.rst
index 2f68b500798..13cb1ef626b 100644
--- a/docs/devel/style.rst
+++ b/docs/devel/s
On Tue, Nov 26, 2024 at 06:46:45PM +0100, Paolo Bonzini wrote:
> Date: Tue, 26 Nov 2024 18:46:45 +0100
> From: Paolo Bonzini
> Subject: Rust in QEMU roadmap
> X-Mailer: git-send-email 2.47.0
>
> [several people are in bcc. You can follow the thread at
>
> https://lore.kernel.org/r/cc40943e-dec
On 26/11/2024 22.17, Pierrick Bouvier wrote:
This attribute is not recognized by clang.
An investigation has been performed to ensure this attribute has no
effect on layout of structures we use in QEMU [1], so it's safe to
remove now.
In the future, we'll forbid introducing new bitfields in pac
On 26/11/2024 23.54, Richard Henderson wrote:
On 11/26/24 11:52, Thomas Huth wrote:
I think we want to continue to maek failing downloads as test failures,
otherwise we'll never notice when an asset is not available from the
internet anymore (since SKIPs just get ignored).
I disagree. Downlo
On 2024/11/13 23:23, Phil Dennis-Jordan wrote:
From: Alexander Graf
Instead of device tree or other more standardized means, VMApple passes
platform configuration to the first stage boot loader in a binary encoded
format that resides at a dedicated RAM region in physical address space.
This pa
On 2024/11/13 23:23, Phil Dennis-Jordan wrote:
From: Alexander Graf
VMApple contains an "aes" engine device that it uses to encrypt and
decrypt its nvram. It has trivial hard coded keys it uses for that
purpose.
Add device emulation for this device model.
Signed-off-by: Alexander Graf
Signed
On Tue, Nov 26, 2024 at 05:11:36PM +0100, Paolo Bonzini wrote:
> Date: Tue, 26 Nov 2024 17:11:36 +0100
> From: Paolo Bonzini
> Subject: Re: [PATCH 1/2] rust: add BQL-enforcing Cell variant
>
> On 11/26/24 15:56, Zhao Liu wrote:
> > > > But this actually applies to _all_ of the device struct! Onc
On Tue, Nov 26, 2024 at 11:52 PM David Hildenbrand wrote:
> On 26.11.24 16:31, Wei Chen wrote:
> > > How can you be sure (IOW trigger) that the system will store
> > > "important data" like EPTs?
> >
> > We cannot, but we have designed the attack (see below) to improve the
> > possibility.
>
Hi Alistair,
You're right.
Initially I thought it might be a good idea to do the whole process from
scratch, but as @Daniel Henrique Barboza suggested
I resubmitted the series with a proper version tag and added some
reviewed-by.
Sorry for the confusion.
Thanks
пн, 25 нояб. 2024 г. в 07:01, Ali
Hi Daniel,
Thanks for the suggestion. I've resubmitted it with the v11 tag and put
some reviewed-bys.
Thanks
пн, 25 нояб. 2024 г. в 16:37, Daniel Henrique Barboza <
dbarb...@ventanamicro.com>:
> Hi Alexey,
>
>
> I believe this is not the second version of this work. When I asked about
> the
> n
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 16
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/targ
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 5 +++
target/riscv/cpu_helper.c | 74 +++
2 files changed, 79 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 417ff45544..74d7076f5a 100644
--- a/targ
From: Alexey Baturo
Zjpm extension is finally ratified. And it's much simplier compared to the
experimental one.
The newer version doesn't allow to specify custom mask or base for pointer
masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e80dcd2e6..fd3ea9ce76 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -186
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 4
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 31 ++-
target/riscv/pmp.c | 14 +++---
target/riscv/pmp.h |
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 19 +++
target/riscv/insn_trans/trans_rvh.c.inc | 11 +++
target/riscv/translate.c| 4
4 files changed, 3
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git
From: Alexey Baturo
Hi,
As suggested on the mailing list by Daniel, I'm resubmitting this series and
keeping the original versioning number.
So that makes this one v11 and previous - v10.
Also I applied previously issues reviewed-by tags on some of the patches that
were present in v9 series, b
On Wed Aug 28, 2024 at 2:33 PM AEST, Nicholas Piggin wrote:
> Fix a couple of issues that Peter found with recent record/replay
> fix for muxed device.
Hi,
I've just realised these never got merged. Sorry for losing track of
them, I was on vacation when doing them and things got a bit neglected.
I would be happy to receive your comments.
ping.
On 2024/11/08 12:29, Tomoyuki HIROSE wrote:
This patch set aims to support unaligned access to xHCI Capability
Registers.
To achieve this, we introduce the emulation of an unaligned access
through multiple aligned accesses. This patch set also ad
QE tested this series patch with regression tests and tested
"check-mac=true" separately. Regression test pass, about the
"check-mac=true" test results, QE also think it is expect result:
1. Boot guest with vdpa device and "check-mac=true", and randomly
setup a mac address.
-netdev type=vhost-vdpa,
On Mon Nov 11, 2024 at 1:39 AM AEST, Philippe Mathieu-Daudé wrote:
> Hi Nick,
>
> On 10/11/24 05:00, Nicholas Piggin wrote:
> > This controller is accepted by IBM Power firmware when the subsystem IDs
> > are set to Power servers. Firmware is picky about device support so the
> > NEC driver does no
There is a bug in the process of resolving the serial port base address
in the fdt of the loongarch VM UEFI. When both serial port information
and rng-seed information are chosen in the fdt, there is a probability
that the serial port base address cannot be resolved correctly.
This problem can be f
On Tue Nov 12, 2024 at 12:32 AM AEST, Fabiano Rosas wrote:
> Nicholas Piggin writes:
>
> > Add tests which init the host controller registers to the point
> > where command and event rings, irqs are operational. Enumerate
> > ports and set up an attached device context that enables device
> > tran
Hi Cedric,
> Subject: Re: [PATCH v2 07/18] aspeed: Fix hardcode attach flash model of spi
> controllers
>
> Hello Jamin,
>
> Sorry for the later answer. I think I missed the question below.
>
> On 10/23/24 04:46, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> Subject: Re: [PATCH v2 07/18] aspeed: Fix
On 11/26/24 13:28, Peter Maydell wrote:
On Tue, 26 Nov 2024 at 21:18, Pierrick Bouvier
wrote:
Signed-off-by: Pierrick Bouvier
---
docs/devel/style.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/devel/style.rst b/docs/devel/style.rst
index 2f68b500798..13cb1ef626b
On 11/26/24 11:52, Thomas Huth wrote:
I think we want to continue to maek failing downloads as test failures, otherwise we'll
never notice when an asset is not available from the internet anymore (since SKIPs just
get ignored).
I disagree. Download failures are not rare.
r~
On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/nanomips16.decode| 8
target/mips/tcg/nanomips48.decode| 8
target/mips/tcg/nanomips_translate.c | 21 +
target/mips/tcg/nan
On Tue, 26 Nov 2024 at 17:13, Nicholas Piggin wrote:
>
> The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
> staging (2024-11-26 14:06:40 +)
>
> are available in the Git repository at:
>
>
On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
Decode the destination register using the xlat() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/mips16e_16.decode | 8
target/mips/tcg/mips16e_32.decode | 9 +
target/mips/tcg/mips16e_translat
On Tue, 26 Nov 2024 at 21:18, Pierrick Bouvier
wrote:
>
> Signed-off-by: Pierrick Bouvier
> ---
> docs/devel/style.rst | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/docs/devel/style.rst b/docs/devel/style.rst
> index 2f68b500798..13cb1ef626b 100644
> --- a/docs/devel/style
On 26.11.2024 20:25, Cédric Le Goater wrote:
On 11/25/24 20:55, Maciej S. Szmigiero wrote:
On 25.11.2024 20:41, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thre
On Thu, Nov 21, 2024 at 04:58:06PM +, Alex Bennée wrote:
> From: Daniel P. Berrangé
>
> The docs for submitting a patch describe using your "Real Name" with
> the Signed-off-by line. Although somewhat ambiguous, this has often
> been interpreted to mean someone's legal name.
>
> In recent ti
On 11/26/24 08:00, Philippe Mathieu-Daudé wrote:
Once the xlat() and simm7() helpers are added,
the decoding is trivial.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/micromips16.decode| 9 +
target/mips/tcg/micromips_translate.c | 19 +++
ta
Prasad Pandit writes:
> From: Prasad Pandit
>
> Refactor ram_save_target_page legacy and multifd
> functions into one. Other than simplifying it,
> it frees 'migration_ops' object from usage, so it
> is expunged.
>
> When both Multifd and Postcopy modes are enabled,
> to avoid errors, the Multif
On 11/25/24 13:47, Pierrick Bouvier wrote:
On 11/25/24 09:05, Peter Maydell wrote:
On Mon, 25 Nov 2024 at 16:48, Pierrick Bouvier
wrote:
Before sending the a series removing gcc_struct and editing the
documentation, do we all agree here it's the right move forward?
If yes, should we apply this
On 26.11.2024 21:52, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Currently, ram_save_complete() sends a final SYNC multifd packet near this
function end, after sending all of the remaining RAM data.
On the receive side, this SYNC packet will cause multifd
On 26.11.2024 20:58, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
A new function multifd_queue_device_state() is provided for device to queue
its state for transmission via a multifd channel.
Signed-off-by: Maciej S. Szmigiero
---
include/migration/misc.
On 26.11.2024 20:37, Cédric Le Goater wrote:
On 11/17/24 20:20, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This QEMU_VM_COMMAND sub-command and its switchover_start SaveVMHandler is
used to mark the switchover point in main migration stream.
It can be used to inform the destinatio
On 26.11.2024 20:29, Cédric Le Goater wrote:
On 11/17/24 20:19, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementation, however it is limited
to queuing AIO operations only
Signed-off-by: Pierrick Bouvier
---
docs/devel/style.rst | 10 ++
1 file changed, 10 insertions(+)
diff --git a/docs/devel/style.rst b/docs/devel/style.rst
index 2f68b500798..13cb1ef626b 100644
--- a/docs/devel/style.rst
+++ b/docs/devel/style.rst
@@ -416,6 +416,16 @@ definitions instead
Windows uses a special mechanism to enable plugins to work (DLL delay
loading). Option for lld is different than ld.
MSYS2 clang based environment use lld by default, so restricting to this
config on Windows is safe, and will avoid false bug reports.
Signed-off-by: Pierrick Bouvier
---
meson.bu
This attribute is not recognized by clang.
An investigation has been performed to ensure this attribute has no
effect on layout of structures we use in QEMU [1], so it's safe to
remove now.
In the future, we'll forbid introducing new bitfields in packed struct.
[1]
https://lore.kernel.org/qemu-
For now, it was only possible to build plugins using GCC on Windows. However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc_struct attribute, which is not
supported by Clang. After investigation, we proved it was safe to drop it.
Built and tested on Windows (all
On Tue, 26 Nov 2024 at 17:56, Daniel P. Berrangé wrote:
>
> On Tue, Nov 26, 2024 at 06:52:57PM +0100, Thomas Huth wrote:
> > On 26/11/2024 18.46, Peter Maydell wrote:
> > > On Tue, 26 Nov 2024 at 17:31, Daniel P. Berrangé
> > > wrote:
> > > >
> > > > On Tue, Nov 26, 2024 at 05:44:29PM +0100, Phi
Prasad Pandit writes:
> From: Prasad Pandit
>
> Remove multifd capability check with Postcopy mode.
> This helps to enable both multifd and postcopy together.
>
> Signed-off-by: Prasad Pandit
> ---
> migration/options.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/migration/opt
Thanks, Daniel. We'll get this patch updated and send it out again.
> it makes sense to allow for a data structure
Whoops, I misread your original message - data structure SGTM.
On Tue, Nov 26, 2024 at 11:04 AM Daniel P. Berrangé
wrote:
> On Mon, Nov 25, 2024 at 03:54:40PM -0500, Andrew Keesle
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Automatic memory management helps avoid memory safety issues.
>
> Signed-off-by: Maciej S. Szmigiero
> ---
> migration/qemu-file.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/migration/qemu-file.h b/migration/qemu-f
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Currently, ram_save_complete() sends a final SYNC multifd packet near this
> function end, after sending all of the remaining RAM data.
>
> On the receive side, this SYNC packet will cause multifd channel threads
> to block, waiting
/qemu into
> staging (2024-11-26 14:06:40 +)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20241126
>
> for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942:
>
> do
Hello Pierrick,
Thanks for including orangepi documentation in your updates.
On Tue, Nov 26, 2024 at 8:00 PM Pierrick Bouvier <
pierrick.bouv...@linaro.org> wrote:
> On 11/22/24 14:50, Pierrick Bouvier wrote:
> > Signed-off-by: Pierrick Bouvier
> > ---
> > docs/system/arm/orangepi.rst | 4 ++-
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Since device state transfer via multifd channels requires multifd
> channels with packets and is currently not compatible with multifd
> compression add an appropriate query function so device can learn
> whether it can actually mak
On 11/25/24 06:14, Richard Henderson wrote:
On 11/25/24 00:59, Pierrick Bouvier wrote:
+self.vm.launch()
+self.wait_for_console_pattern('Welcome to Buildroot')
+time.sleep(0.1)
+exec_command(self, 'root')
+time.sleep(0.1)
There are patches on list or jus
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> A new function multifd_queue_device_state() is provided for device to queue
> its state for transmission via a multifd channel.
>
> Signed-off-by: Maciej S. Szmigiero
> ---
> include/migration/misc.h | 4 ++
> migration/
On 11/17/24 20:20, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This QEMU_VM_COMMAND sub-command and its switchover_start SaveVMHandler is
used to mark the switchover point in main migration stream.
It can be used to inform the destination that all pre-switchover main
migration strea
On 11/17/24 20:19, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementation, however it is limited
to queuing AIO operations only and essentially has a 1:1 mapping between
the
On 11/25/24 20:55, Maciej S. Szmigiero wrote:
On 25.11.2024 20:41, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementation, however it is limited
Pierrick Bouvier writes:
> On 11/13/24 13:13, Fabiano Rosas wrote:
>> Dmitry Frolov writes:
>>
>>> Some tests need more time when qemu is built with
>>> "--enable-asan --enable-ubsan"
>>>
>>> As was discussed here:
>>> https://patchew.org/QEMU/20241112120100.176492-2-fro...@swemel.ru/
>>>
>>> T
On 11/26/24 11:02, Pierrick Bouvier wrote:
When running with a single vcpu, we can return a constant instead of a
load when accessing cpu_index.
A side effect is that all tcg operations using it are optimized, most
notably scoreboard access.
When running a simple loop in user-mode, the speedup is
When running with a single vcpu, we can return a constant instead of a
load when accessing cpu_index.
A side effect is that all tcg operations using it are optimized, most
notably scoreboard access.
When running a simple loop in user-mode, the speedup is around 20%.
Signed-off-by: Pierrick Bouvier
On 11/22/24 14:50, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/system/arm/orangepi.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
index 9afa54213b0..db87e81fec4 100644
--- a/docs/syst
On 11/25/24 09:02, Peter Maydell wrote:
On Fri, 22 Nov 2024 at 22:52, Pierrick Bouvier
wrote:
Signed-off-by: Pierrick Bouvier
---
docs/bypass-iommu.txt| 2 ++
docs/system/arm/virt.rst | 15 +++
2 files changed, 17 insertions(+)
diff --git a/docs/bypass-iommu.txt b/docs/b
On Wed, Nov 13, 2024 at 12:43:40PM +0300, Dmitry Frolov wrote:
> Some tests need more time when qemu is built with
> "--enable-asan --enable-ubsan"
>
> As was discussed here:
> https://patchew.org/QEMU/20241112120100.176492-2-frolov@swemel.r/u
>
> TIMEOUT_MULTIPLIER enviroment variable will be
>
On 11/26/24 08:24, Peter Maydell wrote:
On Fri, 22 Nov 2024 at 22:52, Pierrick Bouvier
wrote:
Reviewed following things:
- system/arm/cpu-features (options)
- system/arm/virt (options)
- boards documented and listed with -machine help (arm and aarch64)
- grep object_class_property_set_descript
On 11/13/24 1:05 PM, Nicolin Chen wrote:
Hi Eric,
On Wed, Nov 13, 2024 at 06:12:15PM +0100, Eric Auger wrote:
On 11/8/24 13:52, Shameer Kolothum wrote:
@@ -181,6 +181,7 @@ static const MemMapEntry base_memmap[] = {
[VIRT_PVTIME] = { 0x090a, 0x0001 },
[VIRT_SE
On 11/26/24 10:14, Fabiano Rosas wrote:
Pierrick Bouvier writes:
On 11/13/24 13:13, Fabiano Rosas wrote:
Dmitry Frolov writes:
Some tests need more time when qemu is built with
"--enable-asan --enable-ubsan"
As was discussed here:
https://patchew.org/QEMU/20241112120100.176492-2-fro...@sw
[several people are in bcc. You can follow the thread at
https://lore.kernel.org/r/cc40943e-dec1-4890-a1d9-579350ce296f@pbonzini.local]
Based on the content presented in the community calls, here are some
ideas for future Rust in QEMU subprojects.
This is by no means exhaustive, for example QAP
On Tue, Nov 26, 2024 at 06:52:57PM +0100, Thomas Huth wrote:
> On 26/11/2024 18.46, Peter Maydell wrote:
> > On Tue, 26 Nov 2024 at 17:31, Daniel P. Berrangé
> > wrote:
> > >
> > > On Tue, Nov 26, 2024 at 05:44:29PM +0100, Philippe Mathieu-Daudé wrote:
> > > > Hi,
> > > >
> > > > On 4/9/24 12:3
On 26/11/2024 18.46, Peter Maydell wrote:
On Tue, 26 Nov 2024 at 17:31, Daniel P. Berrangé wrote:
On Tue, Nov 26, 2024 at 05:44:29PM +0100, Philippe Mathieu-Daudé wrote:
Hi,
On 4/9/24 12:38, Thomas Huth wrote:
fetch() can fail [*] (see previous patch, various Exceptions returned).
What shou
On 11/13/24 13:13, Fabiano Rosas wrote:
Dmitry Frolov writes:
Some tests need more time when qemu is built with
"--enable-asan --enable-ubsan"
As was discussed here:
https://patchew.org/QEMU/20241112120100.176492-2-fro...@swemel.ru/
TIMEOUT_MULTIPLIER enviroment variable will be
a useful opt
On Tue, 26 Nov 2024 at 17:31, Daniel P. Berrangé wrote:
>
> On Tue, Nov 26, 2024 at 05:44:29PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > On 4/9/24 12:38, Thomas Huth wrote:
> > fetch() can fail [*] (see previous patch, various Exceptions returned).
> >
> > What should we do in this case
On Tue, Nov 26, 2024 at 05:44:29PM +0100, Philippe Mathieu-Daudé wrote:
> Hi,
>
> On 4/9/24 12:38, Thomas Huth wrote:
> > From: Daniel P. Berrangé
> >
> > Many tests need to access assets stored on remote sites. We don't want
> > to download these during test execution when run by meson, since t
On Tue, Nov 26, 2024 at 04:45:58PM +, Peter Maydell wrote:
> On Tue, 26 Nov 2024 at 16:44, Philippe Mathieu-Daudé
> wrote:
> >
> > Hi,
> >
> > On 4/9/24 12:38, Thomas Huth wrote:
> > > From: Daniel P. Berrangé
> > >
> > > Many tests need to access assets stored on remote sites. We don't want
On 26/11/24 17:30, Zhao Liu wrote:
HPET_TN_CFG_BITS_READONLY_OR_RESERVED is not used in any place since
HPET_TN_CFG_WRITE_MASK has been already used to check and fix the
writable bits in hpet_ram_write().
Drop this unused macro.
Signed-off-by: Zhao Liu
---
include/hw/timer/hpet.h | 1 -
1 f
By convention, xscom regions get a xscom- prefix.
Fixes: 1adf24708bf7 ("hw/ppc: Add pnv nest pervasive common chiplet model")
Reviewed-by: Glenn Miles
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_nest_pervasive.c | 2 +-
1 file changed, 1 insertion(+), 1 de
From: Harsh Prateek Bora
In case when vcpus are explicitly enabled/disabled in a non-consecutive
order within a libvirt xml, it results in a drc index mismatch during
vcpu hotplug later because the existing logic uses vcpu id to derive the
corresponding drc index which is not correct. Use env->co
powernv CPUs have a set of control registers that can stop, start, and
do other things to control a thread's execution.
Using this interface to stop a thread puts it into a particular state
that can be queried, and is distinguishable from other things that might
stop the CPU (e.g., going idle, or
From: Glenn Miles
The THREAD_SIBLING_FOREACH macro wasn't excluding threads from other
chips. Add chip_index field to the thread state and add a check for the
new field in the macro.
Fixes: b769d4c8f4c6 ("target/ppc: Add initial flags and helpers for SMT
support")
Signed-off-by: Glenn Miles
[n
The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
(2024-11-26 14:06:40 +)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.2-2-20241127
From: BALATON Zoltan
The MV64361 has two PCI buses one of which is used for AGP on
PegasosII. So far we only emulated the PCI bus on pci.1 but some
graphics cards are only recognised by some guests when connected to
pci.0 corresponding to the AGP port. So far the interrupts were not
routed from p
The ppc (pnv and spapr) NMI injection code does not go through the
asynchronous interrupt path and set a bit in env->pending_interrupts
and raise an interrupt request that the cpu_exec() loop can see.
Instead it injects the exception directly into registers.
This can lead to cpu_exec() missing tha
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-id: 2024115049.1617774-3-pierrick.bouv...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
Message-id: 2024115049.1617774-8-pierrick.bouv...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/fby35.rst | 2 +-
1 f
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-id: 2024115049.1617774-2-pierrick.bouv...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/
From: Pierrick Bouvier
We implemented this at the same times as FEAT_SSBS, but forgot
to list it in the documentation.
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-id: 2024115049.1617774-4-pierrick.bouv...@linaro.org
Reviewed-by: Peter Maydell
[PMM: improve commi
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 2024115049.1617774-5-pierrick.bouv...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Pierrick Bouvier
We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
the ID registers call for it. This feature is actually one that must
*not* be implemented in v9.0, but since our documentation lists
everything we can emulate, we should include FEAT_DoubleLock in the
lis
From: Pierrick Bouvier
We already implement FEAT_MTE_ASYNC; we just forgot to list it
in the documentation.
Signed-off-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
Message-id: 2024115049.1617774-6-pierrick.bouv...@linaro.org
[PMM: expand commit message]
Signed-off-by: Peter Maydell
ry at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20241126
for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942:
docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26
From: Pierrick Bouvier
Signed-off-by: Pierrick Bouvier
Reviewed-by: Andrew Jeffery
Message-id: 2024115049.1617774-13-pierrick.bouv...@linaro.org
Signed-off-by: Peter Maydell
---
docs/system/arm/aspeed.rst | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/syst
On Sun, 24 Nov 2024 17:05:32 +0100
Christian Schoenebeck wrote:
> This verifies expected behaviour of previous bug fix patch.
>
> Signed-off-by: Christian Schoenebeck
> ---
Reviewed-by: Greg Kurz
> tests/qtest/virtio-9p-test.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/t
1 - 100 of 242 matches
Mail list logo
